JPH07122899B2 - High speed rotation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a high-speed rotation circuit suitable for use in an image processing system.

(Prior Art) With the progress of office automation, the development of image processing systems has peaked, and a large number of dedicated ICs have emerged with the goal of developing faster and cheaper image processing systems. By the way, in order to rotate the image, the circuit configuration shown in FIG. 5 has been conventionally used. In the figure, reference numeral 51 is a page memory in which an original image and image data after rotation are stored. 52 and 53 are address generation circuits, the former generating a read address of the page memory 51 and the latter generating a write address, and the address (ADR) on the side selected by the selector 54 is given to the page memory 51. Further, RD is read data of the page memory 51, and WD is write data. RD is once latched in the register 55 and then written in the page memory 51. As an example, if the read address of the address generation circuit 52 is generated in the direction shown in FIG. 6 (a) and the write address of the address generation circuit 53 is generated in the direction of FIG. 6 (b), the image rotates 90 degrees to the left. To do.

(Problems to be solved by the invention) However, since a memory circuit used as a page memory is usually configured by arranging one word in the horizontal direction, reading and writing can be performed in word units in the horizontal direction, but in 1-bit units in the horizontal direction. Only can read and write. Therefore, 0-degree rotation and 180-degree rotation can be processed in word units, whereas ± 90-degree rotation is processing in 1-bit units, resulting in a significant reduction in processing speed.

In addition, since this method can only perform memory-to-memory operation, it can be directly connected to other components such as image data compression / expansion circuit and enlargement / reduction circuit when applied to an image processing device. No
It was necessary to exchange data via the shared page memory. For this reason, processing such as compression / expansion and enlargement / reduction is sequentially performed, and thus there is a drawback that it takes more processing time than necessary.

The present invention has been made in view of the above-mentioned drawbacks, and enables pipeline connection with other processing circuits, and realizes processing in word units even in ± 90 degree rotation processing, thereby increasing the speed of the pipeline. An object is to provide a high speed rotation circuit.

[Structure of the Invention] (Means for Solving the Problems) When decompressing image data compressed by a method such as MH-MR-M ² R, the output data is theoretically as shown in FIG. 6 (a). Obtained in order. The main purpose of the present invention is that when the data is obtained in word units instead of bit units, the rotation circuit directly receives the data and can perform processing in word units even in ± 90 degree rotation. Further, the data sent from the page memory in various orders shown in FIGS. 6A to 6D can be rotated and sent in the order shown in FIG. 6A to directly compress the data.

For this reason, the rotation circuit includes a data selector that switches input data bits between forward / reverse order, a vertical / horizontal conversion circuit that performs vertical / horizontal conversion of input data, and a buffer having a capacity of the same number of lines as the bit width of one word. It is composed of a selector that determines whether or not the processing by the vertical / horizontal conversion circuit is valid.

(Operation) In the above configuration, when the transfer mode is the input raster scan mode, the data obtained via the first data selector is sequentially written directly to the buffer RAM until 8 lines (assuming 8 bits per word) are prepared. Put in. When 8 lines are complete, the subsequent input data is written to the other RAM, and the data is read from the other buffer RAM that has already been written. The read data is input to the second vertical / horizontal conversion circuit, and the vertical / horizontal converted contents are written in the page memory in word units. This results in a 90 degree rotation. In the output raster scan mode, the input data obtained from the page memory is supplied to the first vertical / horizontal conversion circuit, where vertical / horizontal conversion processing is performed in word units. The data converted here is written in the corresponding matrix position of the buffer RAM and used for reading, and the subsequent vertical / horizontal conversion processing data is written in the other buffer RAM. Raster scan data is obtained from this buffer RAM.

As a result, pipeline connection with other processing circuits such as compression / expansion / enlargement / reduction can be realized and the speed can be increased.

(Examples) Hereinafter, examples of the present invention will be described in detail. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure,
Reference numerals 11 and 12 are data selectors. The data selectors 11 and 12 output the input data in the normal order (as it is) or in the reverse order (replacement of the data bits on the MSB side and the LSB side).
Composed of LSI. Reference numerals 13 and 14 are vertical / horizontal conversion circuits that perform vertical / horizontal conversion processing in word units. Two 8 × 8 register matrices are used as the vertical / horizontal conversion circuit, and word-by-word processing can be realized by alternately using writing and reading. Details will be described later. Reference numeral 15 is a buffer RAM. Buffer RAM15
When one word is N bits and the total number of dots in the horizontal direction of the image to be handled is M dots, two memories having a capacity of M × N bits (M words) are used. 16, 17 are selectors. The selector 16 receives the data selector 11 output and the vertical / horizontal conversion circuit 13 output as inputs, and according to the data transfer mode described later,
Either one is selectively output to the buffer RAM 15. The selector 17 receives the output of the buffer RAM 15 and the output of the vertical / horizontal conversion circuit 14 as inputs, and selectively outputs one of them to the data selector 12 according to a data transfer mode described later.

2 to 4 are diagrams quoted for explaining the operation of the embodiment of the present invention, and are diagrams showing an example of 90-degree rotation in the input raster scan mode by expanding the memory and an output raster scan, respectively. FIG. 6 is a diagram showing an example of 90-degree rotation in a mode and a table showing an example of a data path according to a data transfer mode. In FIG. 2, (a) is input data, (b) is input data to the vertical / horizontal conversion circuit 14, and (c) is vertical / horizontal conversion circuit 14.
Output data, and (d) is write data to the page memory. In FIG. 3, (a) is input data (read data from the page memory), (b) is input data to the vertical / horizontal conversion circuit 13, (c) is output data from the vertical / horizontal conversion circuit 13, and (d) is external. Is output data for.

The operation of the embodiment of the present invention shown in FIG. 1 will be described in detail below with reference to FIGS.

Prior to the description of the operation of the embodiment, the following preconditions will be briefly described. That is, "a circuit that performs compression / decompression of image data, a circuit that performs expansion / reduction / spatial filtering of decompressed data, a rotation circuit, a page memory or a substitute for the CPU main memory or a bitmap memory for display. It is possible to operate by connecting four members of the memory that store image data such as pipelines. ” In this case, the following two data flows can be considered.

(1) Compressed data → Decompression circuit → Enlargement / reduction / spatial filter → Rotation circuit → Page memory (2) Page memory → Rotation circuit → Enlargement / reduction / spatial filter → Compression circuit → Compressed data In the case of (1), rotation circuit Since the data input to (1) is sent in the order shown in FIG. 6 (a), this will be referred to as the input raster scan mode. In the case of (2), since the normal compression circuit and the expansion / reduction / spatial filter rotation receive data only in the order of (a), the output of the rotation circuit is operated in the order of (a). This is called the output raster scan mode.

Hereinafter, as an operation example, a case of rotating by 90 degrees in each of the input raster scan mode and the output raster scan mode will be described.

First, in the input raster scan mode, the input data is the second
As shown in FIG. 9A, the data is sent in the order of H0, H1, H2, H3, ..., H31. Assuming that the bit width of one word is 8 bits, the buffer will be stored until the input data is aligned for 8 lines.
Write to RAM15 sequentially. That is, the data of H0, H1, H2, ... H15 is written. Although there are two buffer RAM15, writing is performed only on one side, and the input data H16, H17 ,. Buffer RA
The data is read from M15. In the case of this example, the input data is 16 lines, but when there is more data than this, the RAM for writing and the RAM for reading may be interchanged every 8 lines.

Read-out is H0, H2, H4, ..., H14, H1, H as shown in Fig. 2 (b).
3, H5, ..., H15 are performed in this order, and are input to the vertical / horizontal conversion circuit 14. Here, for example, using an 8 × 8 register matrix, first, 8 words of H0, H2, H4, ..., H14 are written in horizontal 8 bits each, and it is 8 words in vertical 8 bits, as shown in FIG. 2 (c). Outputs V0, V1, V2, ..., V7. By using two matrices to write and read alternately, V0, V1,
By writing H1, H3, ... H14 to the other matrix while outputting V7, the vertical-horizontal conversion circuit 14 can process word by word without any difference in input / output speed. That is, by preparing data for 8 lines in an 8 × 8 register matrix and sequentially selecting 1 bit from the MSB of each 8 bits,
Vertical / horizontal conversion can be realized in units of words. The following 8 lines of input data H16, H17, ..., H31 are processed in the same manner as V1.
A rotation of 90 degrees is achieved by obtaining 6, V17, ..., V31 and writing them in the page memory in the order shown in (d).

In the output raster scan mode, the input data is read from the page memory in 8-bit units in the order shown in FIG. (FIG. 3 (b) V0, V1, ..., V15) The vertical / horizontal conversion circuit 13 is also 8 ×
V0, V1, ..., V15 composed of 2 register matrices of 8
Output is obtained in the order of H0, H2, H4, ..., H14, H1, H3, H5 ,. If this data is written in the corresponding matrix of the buffer RAM 15, the data in the buffer RAM 15 is used for reading, and the conversion data H16, H18, ..., H31 of V16, V17, ..., V31 following the other RAM are written. H0 from buffer RAM15,
Raster-scanned data can be obtained by reading H1, H2, ..., H31 in this order.

Circuits that select and output bit forward / reverse order of input data, so-called data selectors 11 and 12, are used differently depending on the rotation angle and the positions of MSB and LSB. As an example, one word in the horizontal direction is MSB.
Is on the left side, and one word in the vertical direction is the MSB on the upper side. The bit order according to the mode and rotation angle, and the data path are as shown in FIG. 4 (Table 1). It should be noted that it is not necessary to prepare two sets for the register matrix forming the vertical / horizontal conversion circuits 13 and 14 since they are not used at the same time as shown in (Table 1). Only one set is prepared, and if necessary, the vertical / horizontal conversion circuit
It should be possible to put it in position 13 or 14.

[Effects of the Invention] According to the present invention as described above, the effects listed below can be obtained.

(1) Since the present invention has a format in which output data is output when input data is given, pipeline connection with other processing (compression / expansion / enlargement / reduction, etc.) circuits is possible. Therefore, the page memory for intermediate work is unnecessary, and a memory for storing the result is sufficient.

(2) Since the processing is performed in word units, high speed can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 to 4 are drawings referred to for explaining the operation of the embodiment of the present invention. Each of them is rotated by 90 degrees in an input raster scan mode. Figure showing expanded example of memory, and showing expanded memory example of 90 degree rotation in output raster scan mode.
It is the figure which showed the example of the data path according to the data transfer mode by the table. FIG. 5 is a block diagram of a conventional example, and FIG. 6 is a diagram showing a scanning direction. 11,12 …… Data selector, 13,14 …… Vertical-to-horizontal conversion circuit, 15
…… Buffer RAM, 16,17 …… Selector.

Claims (1)

[Claims] 1. A first data selector for switching forward / reverse order of bits of input data according to a transfer mode and a rotation mode, and input data supplied via the first data selector. A first vertical / horizontal conversion circuit for performing vertical / horizontal conversion processing in word units, and a first for selectively outputting output data of the first data selector or output data of the first vertical / horizontal conversion circuit according to a transfer mode and a rotation mode. The selector and the data selected by the first selector are supplied and have a capacity of the same number of lines as the data bit width of one word. The order of access for writing and reading is performed according to the transfer mode and the rotation mode. And a second vertical / horizontal conversion circuit for performing vertical / horizontal conversion processing on a word-by-word basis for the output data of the buffer RAM,
A second selector that selectively outputs the output data of the buffer RAM or the output data of the second vertical-horizontal conversion circuit according to the transfer mode and the rotation mode, and the normal order of the bits of the data selected by the second selector. A high-speed rotation circuit comprising: a second data selector that performs reverse order switching according to a transfer mode and a rotation mode.