JPH07122959B2 - Digital I/O Interface - Google Patents

Description

Description: FIELD OF THEINVENTION The present invention relates to a digital I/O interface, and more particularly to a technique for frequency discrimination and frequency switching of sampling signals in a digital system.

<Prior Art> For example, when dubbing with a DAT (Digital Audio Tape Recorder),
When transmitting a digital input signal input from a signal source such as another DAT to a recording DAT, the digital input signal must be transmitted and recorded at the same sampling frequency as the signal source.

However, the sampling frequency differs depending on the recording medium. DAT tapes use 48KHz, 32KHz, and 44.1KHz, while CDs use 44.1KHz.
In the case of the digital input signal sampling frequency change, it is necessary to set a corresponding sampling frequency every time the sampling frequency of the digital input signal changes depending on the recording medium.

A conventional example of a digital I/O interface having such functions is shown in FIG.

In the figure, 2 is a PLL (Phase Locked Loop) circuit, 4
denotes a demodulation circuit, 6 a synchronization detection circuit, 8 a synchronization error detection circuit, 10 a microcomputer, 12 an oscillation frequency switching circuit, and 14a and 14b first and second oscillators (such as crystal oscillators) having mutually different oscillation frequencies.

PLL circuit 2 has a built-in VCO (voltage controlled oscillator).
Either the first or second oscillator 14 a, 14 b is connected to this VCO via a change-over switch in the oscillation frequency change-over circuit 12 .

When the VCO is connected to the first oscillator 14a, it oscillates and outputs a first master clock signal MC1 of 12.288 MHz (corresponding to a multiplied frequency of the first sampling frequency _Fs1 , which is 48 KHz) determined based on the oscillation frequency of the first oscillator _14a , and when the VCO is connected to the second oscillator 14b, it oscillates and outputs a second master clock signal _MC2 of 8.192 MHz (corresponding to a multiplied frequency of the second sampling frequency _Fs2, which is 32 KHz) determined based on the oscillation frequency of the first oscillator 14a.
Each of these is output to the demodulation circuit 4 and the synchronization detection circuit 6 via a signal line l1.

The demodulation circuit 4 includes a frequency division circuit and an arithmetic circuit.

The frequency divider circuit divides the first or second master clock signal _MC1 , _MC2 input from the PLL circuit 2, and converts it into a first or second divided master clock signal whose frequency should be equal to the first or second sampling frequency _Fs1 , _Fs2 .

The arithmetic circuit inputs the first or second frequency-divided master clock signal from the frequency divider circuit, and also inputs a digital input signal DS from a signal source (not shown) via a signal line l2, and calculates the frequency of the first frequency-divided master clock signal to be equal to the first sampling frequency _Fs1
Alternatively, the frequency of the second frequency-divided master clock signal is compared with the second sampling frequency _Fs2 , and an error signal ER corresponding to each frequency difference is fed back to the VCO of the PLL circuit 2 via a signal line l3.

The PLL circuit 2 automatically holds the frequency of the first or second master clock signal _MC1 , _MC2 oscillated by the VCO based on the fed back error signal ER at a constant frequency that accurately corresponds to the first or second sampling frequency _Fs1 , _Fs2 of the digital input signal DS.
Alternatively, the first or second master clock signal MC ₁ , MC 2 may be set to exactly match the second sampling frequency Fs ₁ , Fs _{2 .}
Determine the frequency of ₂ .

In the following, for the sake of simplicity, the first and second master clock signals _MC1 and _MC2 will be collectively referred to as the master clock signal MC, and the first and second sampling frequencies
When Fs ₁ and Fs ₂ are collectively referred to, they are referred to as the sampling frequency Fs.

The demodulation circuit 4 demodulates the digital input signal DS and outputs the demodulated digital signal DS' to the synchronization detection circuit 6 via the signal line 14. The synchronization detection circuit 6 detects the synchronization pattern contained in the demodulated digital signal DS' based on the master clock signal MC input from the PLL circuit 2, and when it matches any of three reference synchronization patterns that are determined in advance as special patterns, it outputs the synchronization signal SYN in the form of a negative pulse on the signal line 14 as shown in FIG.
The signal is outputted via signal line 5 to a recording system in a recording DAT (not shown) and also to a synchronous error detection circuit 8.

The reference sync pattern for determining the sync pattern of the digital input signal DS has a reference period of T (=1/Fs).
As a result, the pattern elements "1T", "2T" and "3T" are appropriately combined.
As shown in (c), there are two patterns: "3T, 1T, 1T, 3T" in which "H" and "L" are alternately repeated, and "3T, 2T, 1T,
There are three patterns: "2T" and "3T, 3T, 1T, 1T".
There are only a few types.

In contrast, the data patterns of the digital input signal DS are various combinations of "1T" and "2T".

The frequency of the master clock signal MC is the digital input signal DS
When the PLL circuit 2 corresponds to the sampling frequency Fs of the first sampling frequency Fs1, more specifically, when a digital input signal DS of the first sampling frequency _Fs1 is input while the PLL circuit ₂ is outputting the first master clock signal _MC1 , or when a digital input signal DS of the second sampling frequency _Fs2 is input while the PLL circuit 2 is outputting the second master clock signal MC2, the detection of the synchronization pattern is performed as specified, and the synchronization signal SYN is output from the synchronization detection circuit 6 at a constant cycle, as shown in FIG. 4(a).

However, when the frequency of the master clock signal MC does not correspond to the sampling frequency Fs, i.e., when the PLL circuit 2
is outputting a first master clock signal _MC1 , a _digital input signal DS
or when a digital input signal DS of the first sampling frequency _Fs1 is input while the PLL circuit 2 is outputting the second master clock signal _MC2 , the detection of the synchronization pattern cannot be performed normally, and the synchronization signal SYN output from the synchronization detection circuit 6 will have missing bits or its period will be disrupted, as shown in FIG. 4(b).

The synchronization error detection circuit 8 counts the synchronization signals SYN, and when a predetermined number of synchronization signals SYN are not detected within a certain time due to the above-mentioned dropout or periodic disturbance, in other words, when a synchronization error is detected, a switching request signal is sent to the microcomputer 10 via a signal line 16 to request that the master clock signal frequency be switched.
Output REQ.

When the microcomputer 10 recognizes the switching request signal REQ from the synchronization error detection circuit 8, it outputs a switching control signal CC to the oscillation frequency switching circuit 12 via the signal line 17. When the switching control signal CC is input, the oscillation frequency switching circuit 12 operates the changeover switch to switch to a state in which the other oscillator is connected to the PLL circuit 2 in place of the oscillator currently connected to the PLL circuit 2.

That is, even though the digital input signal DS has changed to the first sampling frequency Fs ₁ (48 KHz) because the signal source has been switched to one with a different sampling frequency, the PLL circuit 2 continues to operate at the second sampling frequency Fs ₂ (32 KHz).
z) while still connected to the second transducer 14b corresponding to the second
As a result of continuing to output the master clock signal _MC2 , when the switching request signal REQ and the switching control signal CC are output, the oscillation frequency switching circuit 12 switches to a state in which the first oscillator 14a corresponding to the first sampling frequency _Fs1 is connected to the PLL circuit 2.

Conversely, even though the digital input signal DS has changed to the second sampling frequency Fs ₂ (32 KHz), the PLL circuit 2
As a result of the switching request signal REQ and the switching control signal CC being output while the oscillation frequency switching circuit ₁₂ remains connected to the first oscillator 14a corresponding to the first sampling frequency _Fs1 (48 KHz) and continues to output the first master clock signal MC1, the oscillation frequency switching circuit 12 switches to a state in which the second oscillator 14b corresponding to the second sampling frequency _Fs2 is connected to the PLL circuit 2.

By switching the oscillators 14a and 14b in this way, the master clock signal MC is synchronized with the sampling frequency Fs of the digital input signal DS after the signal source has been switched, and the synchronization signal SYN is detected normally.

As described above, in a conventional digital I/O interface, when the sampling frequency Fs of the signal source changes, the missing or periodic disturbance of the synchronization signal SYN that occurs with the change is detected, and the frequency of the master clock signal MC is changed based on the detection result.
It is set to automatically switch to the one corresponding to Fs.

<Problems to be Solved by the Invention> However, in the conventional digital I/O interface, the sampling frequency of the signal source is changed from the second sampling frequency Fs ₂ (32 KHz) to the first sampling frequency Fs
₁ (48KHz), there is no problem.
It has been found that in the initial stage of changing from the first sampling frequency Fs ₁ (48 KHz) to the second sampling frequency Fs ₂ (32 KHz), the following problems may occur.

In the initial stage of changing from a signal source having a first sampling frequency Fs ₁ (48 KHz) to a signal source having a second sampling frequency Fs ₂ (32 KHz), the master clock signal MC output from the PLL circuit 2 does not instantly switch from the first master clock signal MC ₁ to the second master clock signal MC ₂ , but still remains the first master clock signal.
MC ₁ is being output.

In such a state, normally, as already described in detail, the synchronization signal SYN would be lost or its period would be disrupted, and a switch would be made to the second master clock signal _MC2 .
Depending on the combination state of the data pattern consisting of a combination of the pattern elements "2T" and "1T", the switching may not be performed.

As shown in Figure 3(a), the two are mutually "H" and "L".
This is the case of a data pattern of "2T, 2T, 1T, 1T" where the above is repeated.

That is, in the synchronization detection circuit 6, when the "2T" and "1T" of 32KHz after the change are discriminated based on the first master clock signal _MC1 corresponding to 48KHz before the change, the result is 48/
Since 32 = 1.5 times, "2T" at 32KHz is recognized as "3T". Also, "1T" at 32KHz is recognized as "1.5T",
In the discrimination process, this is judged as either "1T" or "2T".
The data pattern at 32KHz after the change is "2T, 2T, 1T, 1T".
Before the switch, at 48KHz, it would distinguish between "3T, 3T, 1T, 1T" or "3T, 3T, 2T, 2T".

Of these, there is no problem with the latter data pattern "3T, 3T, 2T, 2T", but in the case of the former data pattern "3T, 3T, 1T, 1T" shown in FIG. 3(b), the same pattern as this data pattern (FIG. 2(c)) exists among the three types of reference sync patterns, so the sync detection circuit 6 detects the 32KHz data pattern "2
T, 2T, 1T, 1T" to a 48KHz sync pattern of "3T, 3T, 1T, 1T"
The synchronization detection circuit 6 erroneously judges that the synchronization signal SY
This will result in N being output as if it were normal.

If this data pattern "2T, 2T, 1T, 1T" is repeatedly input and the count number of synchronization signals SYN within a certain period of time continues to reach a predetermined number, the synchronization error detection circuit 8 will not output a switching request signal REQ to the microcomputer 10, and therefore the oscillation frequency switching circuit 12 will not perform a switching operation, the first oscillator 14a corresponding to the first sampling frequency _Fs1 (48KHz) will remain connected to the PLL circuit 2, and the PLL circuit 2 will continue to output the first master clock signal _MC1 .

In this way, the signal source has a first sampling frequency Fs ₁ (4
8KHz) to the second sampling frequency Fs ₂ (32KH
z), the master clock signal MC from the PLL circuit 2 remains at the first sampling frequency Fs ₁
Since the first master clock signal _MC1 corresponding to the synchronous synchronous pattern (48KHz) remains the same, the synchronous signal is sent to the recording system at the timing of the data pattern, not at the timing of the synchronous pattern.
SYN will be output, and the recording of the digital input signal DS will become completely random.

The present invention has been devised in view of the above circumstances, and has as its object to reliably detect, when the signal source changes to one with a different sampling frequency, the change and to switch the master clock signal to a frequency that accurately matches the changed sampling frequency.

<Means for Solving the Problems> In order to achieve the above object, the present invention has the following configuration.

That is, the present invention provides a digital I/O device comprising: means for individually generating master clock signals having frequencies corresponding to the sampling frequencies of digital input signals inputted separately at intervals from a plurality of signal sources having different sampling frequencies; means for determining whether a synchronization pattern included in the digital input signal matches a reference synchronization pattern based on the master clock signal and extracting a synchronization signal when they match; and means for switching the frequency of the master clock signal to a state corresponding to the sampling frequency after the change when extraction of the synchronization signal becomes abnormal due to a change in the sampling frequency accompanying a change in the signal source.
The interface is characterized by comprising a means for determining whether or not a synchronization pattern contained in the digital input signal includes pattern elements other than the pattern elements constituting the reference synchronization pattern, and for switching the frequency of the master clock signal when the presence of such pattern elements is determined.

<Function> The above-described configuration of the present invention provides the following functions.

When a change in the sampling frequency of a digital input signal results in the synchronization pattern contained in the digital input signal not matching the reference synchronization pattern and detection of the synchronization signal becomes abnormal, the frequency of the master clock signal is automatically switched so as to correspond to the changed sampling frequency, as in the conventional example.

Then, immediately after the sampling frequency is changed, when the frequency of the master clock signal has not yet been switched, the data pattern contained in the changed digital input signal matches the frequency of the master clock signal before the switch, and the data pattern is erroneously determined to be a synchronization pattern contained in the changed digital input signal and matching the reference synchronization pattern. Even if this data pattern is erroneously determined to be a synchronization pattern that matches the reference synchronization pattern contained in the changed digital input signal, the frequency of the master clock signal can be automatically switched to a state corresponding to the changed sampling frequency in the same manner as described above by determining that the synchronization pattern contained in the digital input signal contains pattern elements other than the reference pattern elements.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the electrical configuration of a digital I/O interface according to an embodiment of the present invention.

2 is a PLL circuit with a built-in VCO, 4 is a demodulation circuit with a built-in divider circuit and arithmetic circuit, 6 is a synchronization detection circuit, 8 is a synchronization error detection circuit, 10 is a microcomputer, 12 is an oscillation frequency switching circuit having a change-over switch, 14a is a first oscillator (crystal oscillator), 14b is a second oscillator, l1 to l7 are each signal line, _MC1 is a first master clock signal, _MC2 is a second master clock signal,
is the master clock signal, DS is the digital input signal, Fs _{is the}
is the first sampling frequency, _Fs2 is the second sampling frequency, DS' is the demodulated digital signal, SYN is the synchronization signal, REQ is the switching request signal, and CC is the switching control signal. Since the configurations and operations of these are the same as those of the conventional example, only the symbol names are listed and the explanations are omitted.

The present embodiment differs from the prior art in that an incorrect synchronization detection circuit 16 is interposed between the demodulation circuit 4 and the synchronization error detection circuit 8.

This false synchronization detection circuit 16 detects whether the synchronization pattern included in the digital input signal DS contains pattern elements other than the pattern elements "1T", "2T" and "3T" constituting the reference synchronization pattern, and transmits the signal line 1 from the PLL circuit 2 to the
The determination is made based on the master clock signal MC input via line 1, and if an incorrect synchronization signal is present, an incorrect synchronization signal IJU is output to a synchronization error detection circuit 8 via a signal line 18.

As mentioned above in the section "Problems to be solved", in the initial stage of changing from the first sampling frequency _Fs1 (48KHz) to the second sampling frequency _Fs2 (32KHz),
Since the master clock signal MC from the PLL circuit 2 has not yet been switched to the second master clock signal _MC2 , the synchronization detection circuit 6 detects the data pattern "2T, 2T, 1T, 1" contained in the digital input signal DS as shown in FIG.
In _this case, under the first master clock signal MC1 corresponding to 48 kHz before the changeover, "3T, 3T, 1T, 1T" becomes "3T, 3T, 1T, 1T", which may be erroneously determined as one of the three reference synchronization patterns, and the synchronization signal SYN is output to the synchronization error detection circuit 8.

In this case, the switch request signal REQ caused by the missing or periodic disturbance of the synchronous signal SYN is not transmitted to the microcomputer 1.
No output for 0.

However, the data pattern "2T,2T,1T,1T" becomes "3T,3T,1T,
When the synchronization pattern becomes "3T, 3T, 1T" in Fig. 2(c),
In the pattern "4T, 4T, 1T, 1T," the pattern element "4T" does not actually exist when normal synchronization detection is being performed.

When the false synchronization detection circuit 16 detects this pattern element "4T" which does not actually exist, it outputs an false synchronization signal IJU to the synchronization error detection circuit 8 via the signal line 18, and the synchronization error detection circuit 8 outputs a switch request signal REQ to the microcomputer 10 based on this false synchronization signal IJU.

As a result, the microcomputer 10 outputs a switching control signal CC to the oscillation frequency switching circuit 12, and the oscillation frequency switching circuit 12 operates the change-over switch to connect the second oscillator 14b to the PLL circuit 2 in place of the currently connected first oscillator 14a, and outputs a second master clock signal MC corresponding to the second sampling frequency _Fs2 (32 KHz) from the PLL circuit 2.
_2. As a result, the synchronization signal SYN is extracted at the desired frequency, and the digital input signal DS can be accurately recorded based on this synchronization signal SYN.

Effects of the Invention According to the present invention, the following effects are achieved.

Immediately after the sampling frequency of the digital input signal changes due to a change in the signal source, the data pattern included in the digital input signal after the change matches the frequency of the master clock signal before the change, when the frequency of the master clock signal has not yet been switched.
Even if the data pattern is erroneously determined to match the reference synchronization pattern contained in the changed digital input signal, the frequency of the master clock signal can be automatically switched to a state corresponding to the changed sampling frequency by determining that the synchronization pattern contained in the digital input signal contains pattern elements other than the reference pattern elements.

As a result, the sync signal is correctly extracted at the desired frequency, and the digital input signal can be accurately recorded based on this sync signal.

[Brief description of the drawings]

Fig. 1 is a block diagram showing the electrical configuration of a digital I/O interface according to an embodiment of the present invention. Figs. 2 to 4 are waveform diagrams commonly used in the embodiment and the conventional example, where Fig. 2 is a waveform diagram of a sync pattern, Fig. 3 is a waveform diagram of a data pattern, and Fig. 4 is a waveform diagram of a sync signal. Fig. 5 is a block diagram showing the electrical configuration of a digital I/O interface according to the conventional example. 2: PLL circuit as a means for generating a master clock signal; 4: demodulation circuit; 6: synchronization detection circuit as a means for extracting a synchronization signal; 8: synchronization error detection circuit as an element of a means for switching a master clock signal frequency when an abnormality in the extraction of a synchronization signal is detected; 10: microcomputer as an element of the switching means; 12: oscillation frequency switching circuit as an element of the switching means; 14a: first oscillator; 14b: second oscillator; 16: false synchronization detection circuit as a means for switching a master clock signal frequency when a pattern element other than a reference pattern element is detected; _MC1 , _MC2 : master clock signal; DS: digital input signal; _Fs1 , _Fs2 : sampling frequency; SYN:
Synchronization signal, REQ...switching request signal, CC...switching control signal, IJU...incorrect synchronization signal

Claims (1)

[Claims] [Claim 1] A digital I/O interface comprising: means for individually generating master clock signals of frequencies corresponding to the respective sampling frequencies of digital input signals which are individually input at intervals from a plurality of signal sources having different sampling frequencies; means for determining based on the master clock signal whether a synchronization pattern contained in the digital input signal matches a reference synchronization pattern and extracting a synchronization signal when they match; and means for switching the frequency of the master clock signal to a state corresponding to the changed sampling frequency when an abnormality occurs in the extraction of the synchronization signal due to a change in the sampling frequency accompanying a change in the signal source, said digital I/O interface further comprising means for determining whether the synchronization pattern contained in the digital input signal contains pattern elements other than the pattern elements which constitute the reference synchronization pattern, and for switching the frequency of the master clock signal when the presence of such pattern elements is determined.