JPH07123222B2 - Gate drive circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate drive circuit for driving a gate of a field effect transistor or the like used in an inverter device, a switching regulator or the like.

[Prior Art] In using a field-effect transistor, the quality of gate drive has a great influence on reliability such as operation loss and element destruction, and therefore an optimum drive method has been desired.

Conventionally, this type of gate drive circuit has a configuration as shown in FIG. In FIG. 2, a pulse transformer 7 has input terminals 15a and 15b on its primary side, one end on the secondary side is connected to the source terminal of the first field effect transistor 8, and the other end is 2 is connected to the source terminal of the field effect transistor 9 and the gate terminal of the first field effect transistor 8. The drain terminal 16 of the first field effect transistor 8 is connected to the gate terminal of the second field effect transistor 9. The conventional gate drive circuit 12 is composed of these pulse transformer 7, first field effect transistor 8 and second field effect transistor 9. In the practical circuit, the gate drive circuit 12 is used.
The drain terminal 16 of the first field effect transistor 8 in
Is connected to the gate terminal of the third field effect transistor 11 via a resistor 10, the source terminal of the third field effect transistor 11 is connected to the drain terminal 17 of the second field effect transistor 9, and the drain terminal 16 and the drain A part of the circuit led from the terminal 17 serves as the output terminals 18a and 18b of the gate drive circuit.

With such a configuration circuit, one of the pulse transformer 7
The third field effect transistor 11 is driven by transmitting the control pulse signal from the secondary side to the secondary side and alternately turning on and off the first field effect transistor 8 and the second field effect transistor 9.

[Problems to be Solved by the Invention] In such a conventional configuration circuit, as shown in FIG.
Since the field effect transistor 13 generally has a built-in diode 14, the signal from the pulse transformer 7 causes the second diode
When the field effect transistor 9 is turned on, the internal diode potential drop of the first field effect transistor 8 (about 0.7
V) signal is attenuated only.

At the time of off, the signal transmission is delayed due to the reverse recovery time of the built-in diode of the first field-effect transistor 8, and the gate terminal of the second field-effect transistor 9 is pulsed through the drain terminal 16 of the first field-effect transistor 8.
Since it is connected to the secondary side of the transformer 7, the wiring becomes long, and due to stray inductance during on / off,
The operation was unstable due to signal ringing. Furthermore, when this gate drive circuit 12 is used in the inverter device, when the third field effect transistor 11 is switched at high speed, the diode built in the first field effect transistor attenuates the signal, the operation loss increases due to the delay, and There is a problem such as damage of the third field effect transistor 11 due to simultaneous turn-on of phases, and there is a drawback that reliability is lowered.

The present invention solves such a problem and eliminates the influence on the built-in diode of the field effect transistor.
The present invention proposes a gate drive circuit that reduces operational loss and improves reliability in driving a field effect transistor.

[Means for Solving the Problem] In order to solve this problem, in the gate drive circuit of the present invention, one end of the secondary side of the pulse transformer having the input terminal on the primary side is the first field effect transistor. Of the pulse transformer and the other end of the secondary side of the pulse transformer to the gate terminal of the first field effect transistor and the source terminal of the second field effect transistor. They are connected to each other.

[Operation] With this configuration, when the third field effect transistor is driven, the built-in diode of the first field effect transistor is not affected, and therefore, the third field effect transistor can be driven at high speed and stably, and switching can be performed. This will reduce loss and improve reliability.

[Embodiment] An embodiment of the present invention will be described below with reference to FIG. First
In the figure, reference numeral 1 is a pulse transformer for insulating the primary side and the secondary side and transmitting signals. With respect to the primary side input terminals 19a and 19b of the pulse transformer 1, one end on the secondary side is connected to the source terminal of the first field effect transistor 2 and the gate terminal of the second field effect transistor 3. ,
The other end on the secondary side of the pulse transformer 1 is connected to both the gate terminal of the first field effect transistor 2 and the source terminal of the second field effect transistor 3. Such a circuit constituted by the pulse transformer 1 and the first field effect transistor 2 and the second field effect transistor 3 on the secondary side thereof is the gate drive circuit 6 of the present invention.
Is. The drain terminal 20 of the first field effect transistor 2 of the gate drive circuit 6 is connected to one end of the resistor 4, and the drain terminal 21 of the second field effect transistor 3 is
While being connected to the source terminal of the third field effect transistor 5, the other end of the resistor 4 is connected to the gate terminal of the third field effect transistor 5. Therefore, a part of the circuit led from the drain terminal 20 of the first field effect transistor 2 and the drain terminal 21 of the second field effect transistor 3 becomes the output terminals 22a and 22b of the gate drive circuit of the present invention, respectively. .

The operation of the circuit configured as described above will be described next. First, a signal (voltage ±
When a pulse signal of E) is input, the signal is induced to the secondary side by electromagnetic induction. The induced signal causes the second field effect transistor 3 to conduct when the voltage of the gate terminal with respect to the source terminal of the second field effect transistor 3 becomes higher than the ON voltage, that is, V _IN + E. At this time, the other end on the secondary side of the pulse transformer 1 and the source terminal of the third field effect transistor 5 have the same potential, while the other end on the secondary side of the pulse transformer 1 has the first field effect transistor 2 built-in. The third field effect transistor 5 is charged via the resistor 4 via the diode, and the third field effect transistor 5 is thereby rendered conductive.

Next, when V _IN = −E, the second field effect transistor 3 is turned off and the first field effect transistor 2 is turned on.
Therefore, one end of the pulse transformer 1 and one end of the resistor 4 have the same potential, and the other end of the pulse transformer 1 and the third end
The source terminal of the field effect transistor 5 is connected through the built-in diode of the second field effect transistor 3, the gate terminal of the third field effect transistor 5 is discharged through the resistor 4, and the third field effect transistor 5 is turned off.

[Effects of the Invention] As described above, according to the present invention, by preventing the built-in diode of the field effect transistor from being affected, the signal from the pulse transformer is transmitted without being attenuated, and the high speed signal is transmitted. Also, it is possible to improve followability. By directly connecting the gate terminals of the two field-effect transistors in the gate drive circuit to the secondary side of the pulse transformer, the wiring can be shortened, stray inductance can be reduced, and signal ringing can be eliminated to ensure reliable operation. Could be done. In addition, since the gate voltage can be charged without being attenuated until it reaches the peak value of the pulse signal, the switching loss is reduced, and even when this gate drive circuit is used in the inverter device, the gate voltage of the third field effect transistor is reduced. It is possible to prevent the third field effect transistor from being damaged due to a reduction in noise resistance due to the attenuation, and as a result, it is possible to improve reliability and obtain a practically large effect.

[Brief description of drawings]

FIG. 1 is a connection diagram of a gate drive circuit in one embodiment of the present invention, FIG. 2 is a connection diagram showing a conventional gate drive circuit, and FIG. 3 is an equivalent circuit diagram of a field effect transistor. . 1 ... Pulse transformer 2 ... First field-effect transistor 3 ... Second field-effect transistor 6 ... Gate drive circuit 19a ... Input terminal 19b ... Input terminal 20 ... Drain terminal of first field-effect transistor 21 …… Drain terminal of the second field effect transistor 22a …… Output terminal 22b …… Output terminal

Claims (1)

[Claims] 1. A primary side of a pulse transformer is used as an input terminal, and one end of a secondary side of the pulse transformer is connected to a source terminal of a first field effect transistor and a gate terminal of a second field effect transistor, The other end of the secondary side of the pulse transformer is connected to the gate terminal of the first field effect transistor and the source terminal of the second field effect transistor, and the drain terminal of the first field effect transistor and the second field effect transistor A gate drive circuit that uses the drain terminal as the output terminal.