JPH0714005B2 - Semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a first semiconductor region of a second conductivity type formed in a semiconductor substrate of a first conductivity type, and a first semiconductor region of the second conductivity type. The present invention relates to a semiconductor device including a first-conductivity-type semiconductor region formed in a semiconductor region and a second-conductivity-type second semiconductor region formed in the first-conductivity-type semiconductor substrate.

Background Art and Its Problems CMOS has various advantages such as low power consumption, high noise margin, wide operating power supply voltage range, and high load drive capability, and thus is the most promising element for future VLSI. Is being watched. In this CMOS, for example, as shown in FIG. 1, a source region 2 composed of ap ⁺ layer in an n-type silicon substrate 1 is formed.
And the drain region 3 is formed. A p-well 4 is formed in a portion of the n-type silicon substrate 1 adjacent to the drain region 3, and a source region 7 and a drain region 8 made of an n ⁺ layer are formed in the p-well 4. On the other hand, a gate insulating film 10 made of a SiO ₂ film is formed on the n-type silicon substrate 1, and a gate electrode 11 made of a polycrystalline silicon film is formed on the gate insulating film 10. Similarly, a gate insulating film made of a SiO ₂ film is formed on the p-well 4.
14 is formed, and a gate electrode 15 made of a polycrystalline silicon film is formed on the gate insulating film 14. The gate electrode 11, the gate insulating film 10, the source region 2 and the drain region 3 constitute the p-channel MOS FET 17, and the gate electrode 15, the gate insulating film 14, the source region 7 and the drain region 8 form the n-channel. A MOS FET 18 is formed, and a CMOS is composed of these p-channel MOS FET 17 and n-channel MOS FET 18.

In the CMOS shown in FIG. 1 described above, for example, the p ⁺ layer forming the drain region 3, the n-type silicon substrate 1, the p well 4, and the n ⁺ layer forming the source region 7, for example, have a pnpn structure, That is, since it has a parasitic thyristor structure, it has the following problems. That is, the above-mentioned parasitic thyristor is turned on by the trigger current generated due to external noise or the like.
When the power is turned on, as a result, a through current may flow from the power supply side to the ground side to destroy the transistor or blow the Al wiring. Note that the terminal A in the above-mentioned parasitic thyristor,
The relationship between the voltage V _AK between K and the current I _AK flowing between these terminals A and K is as shown in FIG. 2, and the through current I _H is approximately 5 mA in this FIG.

The above-mentioned thyristor phenomenon, that is, so-called latch-up, is caused by, for example, a parasitic pnp transistor including a p ⁺ layer forming the drain region 3, an n-type silicon substrate 1 and a p-well 4, an n-type silicon substrate 1, a p-well 4 and It is known that this occurs when the parasitic npn transistor formed of the n ⁺ layer forming the source region 7 is turned on at the same time. Therefore, in the conventional CMOS having a rule of about 2 μm, the junction depth of the p well 4 is increased to about 3 to 6 μm, and
By increasing the impurity concentration of the p-well 4 to reduce β _n of the above-mentioned parasitic npn transistor, and by taking a sufficiently large distance between the p-well 4 and the p ⁺ layer forming the drain region 3,
A p ⁺ layer (shown by a broken line) having a concentration of p-type impurities lower than that of the source region 2 and drain region 3 of the p-channel MOS FET 17 but higher than that of the p-well 4 is formed around the p-well 4 to form a parasitic pnp transistor. Latch-up was prevented by reducing β _p . However, 1.5 μm
It is difficult to prevent the latch-up from occurring by the above-mentioned method in the CMOS with the rule or less.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device in which the above-described drawbacks of a conventional CMOS are corrected.

SUMMARY OF THE INVENTION A semiconductor device according to the present invention includes a second conductive type first semiconductor region (for example, a p-well) formed in a first conductive type semiconductor substrate, and a second conductive type first semiconductor region. A first conductivity type semiconductor region (for example, a source region and a drain region formed of an n ⁺ layer) formed in the semiconductor region, and a second conductivity type second semiconductor region formed in the first conductivity type semiconductor substrate. Two
Semiconductor device including a semiconductor region (e.g., p ⁺ source and drain regions consist of a layer) and the respective (e.g. LS
In the CMOS constituting I), the first conductive type semiconductor substrate is formed of a first conductive type epitaxial growth layer formed on a first conductive type low resistance semiconductor substrate, and The second conductivity type first semiconductor region is formed so that the peak of the impurity concentration is located at a position deeper than the junction between the semiconductor region and the second conductivity type first semiconductor region. The interval between the conductive type first semiconductor region and the first conductive type low resistance semiconductor substrate is 0.5 μm or more. With this configuration, the second conductive type second semiconductor region, the first conductive type epitaxial growth layer, the second conductive type first semiconductor region, and the first conductive type semiconductor region are formed. It is possible to effectively prevent the latch-up caused by the formed parasitic thyristor, particularly the latch-up at the time of power-on.

Embodiment An embodiment in which the semiconductor device according to the present invention is applied to a CMOS forming an LSI will be described below with reference to the drawings.
In FIGS. 3A to 3G, the same parts as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted as necessary.

As shown in FIG. 3A, first, an epitaxial growth layer 21 having a film thickness of 2.5 μm and a resistivity of 2 Ωcm is formed on a low-resistance n-type silicon substrate 1 having a resistivity of 0.01 Ωcm.

Next, as shown in FIG. 3B, after the SiO ₂ film 22 having a film thickness of 300 Å is formed on the surface of the epitaxial growth layer 21 by, for example, the thermal oxidation method, the SiO ₂ film 22 is formed on the SiO ₂ film 22 by, for example, the CVD method so that the film thickness is A 1000 Å Si ₃ N ₄ film 23 is deposited.

Next, as shown in FIG. 3C, predetermined portions of the Si ₃ N ₄ film 23 are removed by etching to form Si ₃ N ₄ films 23a and 23b having a predetermined shape.
Next, for example, a thick photoresist is applied to the entire surface, and then a predetermined portion of this photoresist is removed to form a photoresist 24 having a predetermined shape.

Next, using the photoresist 24 as a mask, a p-type impurity such as boron B is accelerated in the epitaxial growth layer 21 through the Si ₃ N ₄ films 23a and 23b and the SiO ₂ film 22, for example, at an acceleration energy of 550 KeV.
As shown in FIG. 3D, the p well 4 is formed in the epitaxial growth layer 21 by ion implantation. Since the peak of the impurity concentration in the p-well 4 is located in the lower part of the p-well 4, the protrusions 4a and 4b are formed at both ends of the lower part of the p-well 4.

Next, after removing the photoresist 24, as shown in FIG. 3E, p-type impurities such as B (dose amount is 5 × 10 ¹³
cm ^-2 ) and N-type impurities such as P (dose amount is 1.
5 × 10 ¹² cm ⁻² ) is ion-implanted into the epitaxial growth layer 21 through the SiO ₂ film 22 (B in the epitaxial growth layer 21 is represented by o and P is represented by ·).

Next, the epitaxial growth layer 21 is thermally oxidized using the Si ₃ N ₄ films 23a and 23b as an oxidation mask to form a thick SiO ₂ film 25 (field oxide film) continuous with the SiO ₂ film 22 as shown in FIG. 3F. To do. Further, during this thermal oxidation, P and B ion-implanted in the epitaxial growth layer 21 in the step shown in FIG. 3E are diffused in the depth direction to form channel stoppers 26 and 27 below the SiO ₂ film 25. Formed and p-well 4
Are annealed.

Next, after removing the Si ₃ N ₄ films 23a and 23b by etching, as shown in FIG. 3G, the gate electrodes 11 and 15 made of a polycrystalline silicon film are formed on the SiO ₂ film 22. Next, using the gate electrode 11 as a mask, a p-type impurity such as B is formed on the epitaxial growth layer 21 between the SiO ₂ film 25a and the SiO ₂ film 25b via the SiO ₂ film 22.
Source region 2 and drain region 3 made of p ⁺ layers are formed by high-concentration ion implantation, and the p-well 4 between the SiO ₂ film 25b and the SiO ₂ film 25c is covered with SiO ₂ film 25b using the gate electrode 15 as a mask. n-type impurity via the ₂ film 22, for example,
By ion-implanting As, a source region 7 and a drain region 8 made of an n ⁺ layer are formed. In this way, p
CM consisting of channel MOS FET17 and n-channel MOS FET18
OS is completed. The junction depth of p-well 4 is about 1.5μ.
m, and the distance x between the p-well 4 and the n-type silicon substrate 1 is about 1 μm.

FIG. 4 shows the impurity concentration distribution in the direction of arrow A in the CMOS shown in FIG. 3G. As is clear from FIG. 4, the peak of the impurity concentration of the p-well 4 is located in the deep portion of the epitaxial growth layer 21, and the p-well 4 having such an impurity concentration distribution is called retrograde well. .

With respect to the CMOS shown in FIG. 3G manufactured by the above-described embodiment, the relation between V _AK and I _AK is examined in the same manner as in FIG.
When I _H was obtained, it was I _H ∞. From this, it is understood that latch-up is almost completely prevented in the CMOS shown in FIG. 3G. The latch-up is thus prevented by first implanting B with an extremely high accelerating energy of 550 KeV so that the p well 4 has a retrograde well structure as shown in FIG.
This is because β _n of the transistor could be made extremely small. Secondly, the epitaxial growth layer 21 formed on the n-type silicon substrate 1 having an extremely low resistance of 0.01 Ωcm 21.
Since the CMOS is formed in the resistor, the resistance Rs (see Fig. 3G) is greatly reduced, and therefore I _RS × Rs <0.6 (V) (I _RS : current flowing through Rs), which is positive to the parasitic pnp transistor. This is because there is no return.

In the conventional CMOS manufacturing method, B is ion-implanted into the epitaxial growth layer 21 at a relatively low energy, and then heat treatment (drive-in diffusion) is performed at a high temperature of, for example, 1200 ° C. for a predetermined time to obtain a desired junction depth. Since the p-well 4 is formed, the B diffuses laterally by, for example, about 1.5 to 3 μm during the heat treatment, which makes it difficult to reduce the planar size of the p-well 4. On the other hand, according to the present embodiment, since the p well 4 having a desired junction depth can be formed by the high energy ion implantation of B, the p well 4 is required to have a required junction depth. There is no need to perform heat treatment at high temperature for a long time. For this reason, the lateral diffusion of B becomes substantially zero, and therefore the planar size of the p-well 4 can be made extremely small as compared with the conventional one, so that the CMOS can be miniaturized.

Further, according to the above embodiment, there are the following advantages.
That is, if the capacitance C _j between the p-well 4 and the epitaxial growth layer 21 is large, latch-up is likely to occur when the CMOS power is turned on, so the smaller C _j is, the better it is. Distance x from n-type silicon substrate 1
(See FIG. 3G) is selected to be about 1.0 μm, so that C _j is extremely small as shown in FIG. 5, and is almost equal to the bulk value. Therefore, it is possible to effectively prevent the occurrence of latch-up especially when the power is turned on. The breakdown voltage between the p-well 4 and the epitaxial growth layer 21 is about 15 V, which is practically no problem. Furthermore, p-well 4
Since it is a retrograde well, as is apparent from FIG. 4, the impurity concentration of the p well 4 at the junction with the source region 7 and the drain region 8 of the n-channel MOS FET 18 is lower than that of a normal well. Therefore, the depletion layer easily extends at this junction and the junction capacitance is small, which is suitable for speeding up.

The present invention is not limited to the above-mentioned embodiments, but various modifications can be made based on the technical idea of the present invention. For example, in the above-described embodiment, the acceleration energy at the time of ion implantation of B for forming the p well 4 is 550 KeV, but it is deeper than the junction between the source region 7 and the drain region 8 and the p well 4. If the peak of the impurity concentration is located, the acceleration energy can be changed as necessary. Also, the specific resistance of the n-type silicon substrate 1 is not limited to the value used in the above-mentioned embodiment, but it is difficult to reduce Rs when the specific resistance is large, so it is preferable to set it to, for example, 0.1 Ωcm or less. . Similarly, the epitaxial growth layer 21
The film thickness and the specific resistance of the film are not limited to the values used in the above-mentioned examples, but if the film thickness is too large, the crystallinity of the film deteriorates, and projections are generated during the growth of the film. Since the cost required for film formation is high, the film thickness is 5
It is preferable that the thickness is μm or less. The distance x between the p-well 4 and the n-type silicon substrate 1 can be changed as necessary, but since x is too small, C _j is large, so x is preferably 0.5 μm or more.

Although the p-well 4 is formed in the above embodiment,
It is also possible to reverse the conductivity type of each part of the CMOS shown in FIG. 3G to form an n-well structure.

According to the semiconductor device of the present invention, the first-conductivity-type semiconductor substrate is formed of the first-conductivity-type epitaxial growth layer formed on the first-conductivity-type low-resistance semiconductor substrate. The second conductivity type first semiconductor region is formed so that the peak of the impurity concentration is located at a position deeper than the junction between the first conductivity type semiconductor region and the second conductivity type first semiconductor region. Since the distance between the second conductive type first semiconductor region and the first conductive type low resistance semiconductor substrate is 0.5 μm or more, the second conductive type second semiconductor region and the first conductive region A conductive type epitaxial growth layer and a second conductive type first
It is possible to effectively prevent the latch-up caused by the parasitic thyristor composed of the semiconductor region of (1) and the semiconductor region of the first conductivity type, in particular, the latch-up when the power is turned on.

[Brief description of drawings]

FIG. 1 is a sectional view showing the structure of a conventional CMOS constituting an LSI, FIG. 2 is a graph showing the relationship between V _AK and I _AK of a parasitic thyristor, and FIGS. 3A to 3G are semiconductors according to the present invention. FIG. 4 is a cross-sectional view showing an example of a method of manufacturing a CMOS constituting an LSI as an embodiment of the apparatus in the order of steps, FIG. 4 is a graph showing an impurity concentration distribution in the direction of arrow A in FIG. 3G, and FIG. 3 is a graph showing the relationship between the voltage V and C _j applied between the p-well and the n-type silicon substrate with the distance x between them as a parameter. In the reference numerals used in the drawings, 2 ... source region (second conductivity type second semiconductor region) 3 ... drain region (second conductivity type second semiconductor region) 4 ... p well (second Conductive type first semiconductor region) 7 ... Source region (first conductive type semiconductor region) 8 ... Drain region (first conductive type semiconductor region) 10,14 ...... Gate insulating film 11,15,22 ...... Gate electrode 17 …… p channel MOS FET 18 …… n channel MOS FET 21 …… Epitaxial growth layer.

Claims (1)

[Claims] 1. A first conductivity type semiconductor region formed in a first conductivity type semiconductor substrate, and a first conductivity type formed in the second conductivity type first semiconductor region. A semiconductor device having a first conductivity type semiconductor region and a second conductivity type second semiconductor region formed in the first conductivity type semiconductor substrate. A first conductivity type epitaxial growth layer formed on a conductivity type low resistance semiconductor substrate, and more than a junction between the first conductivity type semiconductor region and the second conductivity type first semiconductor region. The second conductivity type first semiconductor region is formed so that the peak of the impurity concentration is located at a deep position, and the second conductivity type first semiconductor region and the first conductivity type low resistance semiconductor are formed. It is characterized in that the distance from the substrate is 0.5 μm or more Conductor device.