JPH0714006B2 - Dynamic memory - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a dynamic memory, and more particularly to a dynamic memory having an improved arrangement of memory cells.

[Technical background of the invention]

As shown in FIGS. 8 and 9, the conventional dynamic memory has a structure in which memory cells are displaced by 1/2 pitch in the channel length direction of a transistor. That is, 1 in the figure is an island region that constitutes two memory cells separated by a field oxide film (not shown) on the surface of a p-type semiconductor substrate (not shown), and these island regions 1 are arranged with a 1/2 pitch shift. ing. An n ⁻ -type diffusion layer (not shown) that constitutes one electrode of a capacitor is formed on the pentagonal portions at both ends of the island region 1, and a predetermined distance from the diffusion layer is formed in the center thereof. An n ⁺ type diffusion layer (not shown) connected to the bit line is formed. Reference numeral 2 in the figure is a cell plate electrode made of, for example, the first-layer polycrystalline silicon. As shown in FIG. 9, the cell plate electrode 2 covers the pentagonal n ⁻ type diffusion layer of each island region 1 via a capacitor insulating film, and serves as a common electrode for each memory cell. Further, the cell plate electrode 2 is formed with an opening 3 corresponding to the transistor region, and each opening 3 is formed.
Are shifted by 1/2 pitch. Reference numeral 4 in the drawing denotes a transfer gate made of the second-layer polycrystalline silicon provided over one memory cell region of the island region 1 adjacent in the row direction. Reference numeral 5 in the figure denotes a third line extending in the row direction which is connected to the n ⁺ type diffusion layer through the contact hole 6.
The layer is a bit line made of polycrystalline silicon. 7 in the figure
Is the transfer gate 4 and the contact hole 8
A word line made of Al connected in the column direction and extending in the column direction.

[Problems of background technology]

However, in the arrangement of the memory cells of the dynamic type memory shown in FIGS. 8 and 9, when the memory cells become smaller with the miniaturization, the distance between the adjacent hole portions 3 of the cell plate electrode 2 becomes smaller and the cutting is performed. The problem arises that That is, if the dimensions of the memory cells are all reduced at the same rate and the design rule can be reduced at the same rate, the problem of the disconnection of the cell plate electrode does not occur even in the memory cell having the conventional structure described above simply by proportional reduction.
However, due to the increase in the storage capacity required for the dynamic memory and the limitation on the chip size due to the size of the package, the storage capacitor is too small and the read signal becomes too small to be used by simple proportional reduction. Therefore, it is expected that the capacitance will be increased in the future by either embedding the capacitor or using a high dielectric insulating film. At this time, the capacitor portion of the memory cell is surely reduced in plan as compared with the conventional proportional reduction ratio, but the other transfer gate 4, the bit line 5, and the contact hole 6 between the n ⁺ type diffusion layer are reduced. Only the proportion reduction ratio is reduced, and as a result, the capacitor portion is smaller than the opening portion 3 of the cell plate electrode 2 for forming the contact hole 6 and the like. In this way, the area of the capacitor portion is reduced, while the opening 3 of the cell plate electrode 2 for forming the contact hole 6 between the bit line 5 and the n ⁺ type diffusion layer is relatively small. Since it becomes larger, that is, the whole is not proportionally reduced, there arises a problem that the distance between the opening portions 3 becomes shorter and the cell plate electrode 2 is cut at those portions.

[Object of the Invention]

According to the present invention, the contact hole between the diffusion layer of the transistor and the bit line is proportionally reduced, and the cell plate electrode can be prevented from being cut even if the capacitor portion is further reduced compared to the contact hole, and a common potential can be applied to the electrode. It is intended to provide a highly reliable dynamic memory that can be provided.

[Outline of Invention]

The present invention provides a dynamic memory having a structure in which a plurality of memory cells each including one transistor and one capacitor are arranged on a semiconductor substrate in a row direction orthogonal to a channel direction of the transistor and a column direction parallel to the channel direction. The plurality of memory cells are arranged with a pitch shift of 1/2 ⁿ (where n is a natural number of 2 or more) in the column direction of the substrate, and the capacitors are arranged on the substrate at least via a capacitor insulating film. Common cell plate electrodes arranged in parallel, the cell plate electrodes are connected in the column direction of the substrate in the same pitch as the memory cells and connected in a stepwise manner, and at least bit lines are connected to the diffusion layer on the surface of the substrate. A dynamic memory characterized in that it has an opening for That. According to the present invention, as described above, the contact hole between the diffusion layer of the transistor and the bit line is proportionally reduced, and the cell plate electrode can be prevented from being cut even if the capacitor portion is further reduced as compared with the contact hole. It is possible to obtain a dynamic memory capable of applying a common electric potential to the same electrode.

Example of Invention

Hereinafter, the present invention will be described in detail with reference to FIGS. 1 to 7 by taking a dynamic memory in which memory cells are displaced by 1/4 pitch as an example.

FIG. 1 is a plan view of a dynamic memory, FIG. 2 is a sectional view taken along the line AA of FIG. 1, and FIG. 3 is BB of FIG.
FIG. 4 is a plan view showing a state when a cell plate is formed, FIG. 5 is a plan view of a cell plate electrode, and FIG. 6 is a plan view showing a state when a transfer gate is formed. , FIG. 7 is a plan view showing a state when the bit line is formed. Reference numeral 11 in the figure denotes a p-type semiconductor substrate. A field oxide film 12 is selectively provided on the surface of the substrate 11, and an island region 13 is formed on the surface of the substrate 11 to form two memory cells separated by the field oxide film 12. Has been done. These island areas 13
Are shifted by 1/4 pitch as shown in FIG. In addition, embedded capacitors 14 are provided near both ends of the island region 13. This embedded capacitor
Reference numeral 14 denotes a groove portion 15 formed in the substrate 11, a capacitor insulating thin film 16 formed on the surface of the substrate 11 around the groove portion 15 and an inner surface of the groove portion 15, and on the surface of the substrate 11 including the groove portion 15. And a cell plate electrode 17 made of first-layer polycrystalline silicon selectively provided in the first layer. The cell plate electrode 17 has an island region as shown in FIGS.
It covers the vicinity of the groove portion 15 of 13 and has a step-like opening portion 18, and has a shape integrated with each other in the periphery. A first interlayer insulating film 19 is provided on the peripheral surface of the cell plate electrode 17.

On the surface of the island region 13 except the region under the cell plate electrode 17, three n ⁺ type diffusion layers 20 _{1 to} 20 ₃ (20 ₃ are not shown) are electrically isolated from each other. ing. On the surface of the island region 13 of the substrate 11 including the channel region between these diffusion layers 20 ₁ , 20 ₂ and 20 ₂ , 20 ₃ (not shown), as shown in FIGS. A transfer gate 21 made of polycrystalline silicon is provided via a gate oxide film 22. These transfer gates 21 extend not only in one island region 13 but also in the other island region 13 where the other end crosses over the first interlayer insulating film 19 and is adjacent thereto.

In addition, the first interlayer insulating film 19 and the transfer gate
The entire surface including 21 is covered with a second interlayer insulating film 23.
On the second interlayer insulating film 23, and a third layer polycrystalline silicon extending connecting row direction through the n ⁺ -type diffusion layer 20 ₂ and the contact hole 24 as shown in FIG. 2 and FIG. 7 Bit line 25 is provided. Furthermore, the bit line
A third interlayer insulating film 26 is coated on the second interlayer insulating film 23 including 25. As shown in FIGS. 1 and 3, the third interlayer insulating film 26 extends in the column direction connected through the transfer gate 21 and the contact hole 27.
A word line 28 made of Al is provided.

Therefore, according to the present invention, by arranging the memory cells so as to be shifted by 1/4 pitch, as shown in FIGS. 1, 2, 4, and 5, the minimum value of the width of the cell plate electrode 17 is reduced. Is equivalent to the length of the embedded capacitor 14, no matter how the memory cell is miniaturized, as long as the cell plate electrode 17 is present on the capacitor 14, the electrode 17 is connected diagonally, One is never isolated. Therefore, as shown in FIG. 5, by surrounding the cell array with the first-layer polycrystalline silicon and applying a predetermined potential around it, the same potential can be applied to all cell plate electrodes 17.

Also, by arranging the memory cells with a shift of 1/4 pitch, compared with the conventional dynamic type memory shown in FIG. 8, one bit line 25 and a contact hole 2 between the diffusion layer 20 ₂ are provided.
Because it can halve the number of 4, the diffusion layer 20 ₂ and the p-type semiconductor substrate 11
The depletion layer capacitance between and is reduced, and the bit line capacitance can be reduced compared to the conventional case. In particular, from the viewpoint of keeping the electric field strength in the transistor constant with the miniaturization of the transistor in the future, the impurity concentration of the diffusion layer tends to be high, and the capacitance between the diffusion layer and the substrate is increased. Reducing the number of contact holes between the layers and the bit lines brings great advantages.

Although the above embodiment has described the example in which the memory cells are arranged with a shift of 1/4 pitch, the same effect can be achieved even with a shift of 1/8 or 1/16 pitch. However, considering the arrangement of transfer gates and contact holes, the pitch of word lines, and the like, it is most preferable to shift them by 1/4 pitch.

In the above-mentioned embodiment, the embedded type capacitor is described as an example of the capacitor, but the same effect can be achieved when a capacitor having a high dielectric insulating film as a capacitor insulating film is used.

〔The invention's effect〕

As described above in detail, according to the present invention, the contact hole between the diffusion layer of the transistor and the bit line is proportionally reduced, and the cell plate electrode can be prevented from being cut even if the capacitor portion is further reduced as compared with the contact hole. It is possible to provide a dynamic memory that can apply a common potential to the same electrode, can reduce the bit line capacitance, and can achieve high reliability and high speed.

[Brief description of drawings]

FIG. 1 is a plan view of a dynamic memory showing an embodiment of the present invention, FIG. 2 is a sectional view taken along the line AA of FIG.
3 is a sectional view taken along the line BB of FIG. 1, FIG. 4 is a plan view showing a state when a cell plate is formed, FIG. 5 is a plan view of a cell plate electrode, and FIG. 6 is a transfer. FIG. 7 is a plan view showing a state when a gate is formed, FIG. 7 is a plan view showing a state when a bit line is formed, FIG. 8 is a plan view showing a conventional dynamic memory, and FIG. 9 is FIG. FIG. 6 is a plan view showing a state when a cell plate is formed in the memory of FIG. 11 ... P-type semiconductor substrate, 12 ... Field oxide film, 13 ... Island region, 14 ... Buried capacitor, 15 ... Groove part, 17 ... Cell plate electrode, 20 ₁ , 20 ₂ ... N ⁺ type diffusion layer, 21 ... Transfer gate , 24, 27 ... Contact hole, 25 ... Bit line, 28
… Word line.

Claims (4)

[Claims] 1. A dynamic memory having a structure in which a plurality of memory cells each including one transistor and one capacitor are arranged on a semiconductor substrate in a row direction orthogonal to a channel direction of the transistor and a column direction parallel to the channel direction. The plurality of memory cells are arranged with a pitch of 1/2 ⁿ (where n is a natural number of 2 or more) shifted in the column direction of the substrate, and each of the capacitors has at least a capacitor insulating film on the substrate. A common cell plate electrode disposed via the cell plate electrode, the cell plate electrode is connected in a stepwise manner by shifting the same pitch as the memory cells in the column direction of the substrate, and at least bit lines are formed in the diffusion layer on the substrate surface. A dynamic memory having an opening for connection and having an integrated shape with a peripheral frame 2. The dynamic memory according to claim 1, wherein the capacitor insulating film is a high dielectric insulating film. 3. The capacitor is disposed on the substrate with a groove formed in the substrate, a capacitor insulating film formed on the surface of the substrate including the inner surface of the groove, and at least the capacitor insulating film on the substrate. The dynamic memory according to claim 1, wherein the dynamic memory is an embedded capacitor having the cell plate electrode. 4. The dynamic memory according to claim 1, wherein the plurality of memory cells are arranged with a 1/4 pitch offset in the column direction of the substrate.