JPH0714047B2 - Charge transfer device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device, and in particular, an inversion layer is included in a surface of a semiconductor of a part of each cell, and the cell region is gate-induced by a function of the inversion layer as a virtual electrode. The present invention relates to a buried channel charge transfer device (CCD) that is protected from potential changes.

BACKGROUND ART A single-phase CCD is known, for example, in which a continuous conductor gate layer is provided on a signal channel of the CCD. This single-phase CCD is a surface channel device, that is, a CCD that allows signal charge packets to move across a semiconductor surface. Such a single phase C
CD has a smaller signal processing capacity than a normal multi-phase CCD,
It has the drawback of requiring large amplitude clock pulses.

In the buried channel type CCD, mobile charges are accumulated and transferred in an induction channel in a semiconductor thin layer.
In a general surface transfer CCD, a trapping effect usually occurs at the interface between oxide and silicon, but in a buried channel CCD, the trapping effect can be prevented, and thus charge transfer efficiency is improved. Further, since carrier dispersion at the interface is eliminated, charge transfer efficiency is also improved. As a result, it is possible to operate at a higher frequency than before.

As such a buried channel type single-phase CCD, VP-CCD
There is (Virtual Phase CCD). This is because, for example, each cell included in the multi-cell type signal channel has four regions I.
II III IV, in which impurity implantation or diffusion is performed from the semiconductor surface to an appropriate depth in these regions, and the impurity distribution in each region is different. A gate electrode is provided at least on the upper surface of the region III, and the maximum potential generated in each region when the gate is on and when the gate is off is determined by the impurity distribution unique to each region. An inversion layer is provided on the semiconductor surface of the region III IV, and the inversion layer protects the region III IV from the potential change due to the voltage applied to the gate electrode, and the potential is turned on and off by the voltage applied to the gate electrode. It does not change. Therefore, by applying a single-phase clock signal to the gate electrode, the potential maximum value in the region I II repeatedly rises and falls on the basis of the fixed potential maximum value in the region III IV. In both gate states, the maximum potential of region II is higher than that of region I,
Since the maximum potential of is kept higher than that in the region III, the directionality of charge transfer can be obtained.

When such a VP-CCD is used as an imaging device, unlike the conventional FT-CCD in which the front surface of the semiconductor layer is covered with a polysilicon electrode for charge transfer, only the region I II is polysilicon. Since it may be covered with electrodes, the sensitivity to incident light is good.

However, such a VP-CCD is difficult to manufacture because the potential maximum value of each region is different, and the impurity is implanted or diffused in each region so that the impurity distribution of each region is different. That is, the impurity distribution can be made to be a desired one by overlapping the implanted or diffused regions of the impurity distribution at the boundary between the regions or by forming a gap having no impurity distribution between the regions. There wasn't. In particular, in the region where the gate electrode is not formed, the inversion layer is provided at the uppermost portion. Therefore, after two regions having different maximum potentials are formed by implanting or diffusing impurities, the implanting of impurities is uniformly performed on the upper part of these two regions. Alternatively, the region of the inversion layer must be formed by performing diffusion, which is difficult to manufacture.

Aim The present invention solves the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide a charge transfer device which can be manufactured easily and can be densified.

DISCLOSURE OF THE INVENTION According to the present invention, a reverse conduction type buried channel including a plurality of cells is formed on one main surface of a single conduction type semiconductor substrate, and a gate electrode is formed on a part of the semiconductor surface of each cell. In addition, in the charge transfer device in which a part of each cell is selectively protected from the potential change due to gate induction by the inversion layer formed on the semiconductor surface where the gate electrode is not formed, the inversion layer of each cell is formed. The region in which the gate electrode is formed has a uniform potential, and at least two potentials are formed in the region where the gate electrode is formed.

Description of Embodiments Embodiments of the charge transfer device according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a cross section in the channel direction of a charge transfer device according to the present invention.

The n-type region 4 formed on the substrate 2 made of p-type silicon provides n
Type CCD channels are formed. A plurality of cells extending in the longitudinal direction of the channel, separated from each other,
Each cell has three regions I II III. The n-type region 4 forming the n-type channel is implanted with different amounts of impurities (donors) in each of the three regions I II III as described later. A p-type region 6 is formed on the n-type region 4 in the region III. In the region III, the p-type region 6 functions as a virtual electrode having a shielding effect for preventing the potential change due to gate induction. The thickness of the p-type region 6 is 0.15 to 0.7 μm, preferably 0.2 to 0.4 μm. In Region III, n
A gate electrode 10 for applying a clock pulse for charge transfer is arranged above the mold region 4 via an insulating film 8, and the gate electrode 10 is connected to a clock pulse source by an accordion switch. Gate electrode 10 and region II
The upper surface of I is a passivation film formed of PSG, etc.
Covered by 12.

The upper limit potential of the n-type channel in the region III is determined and fixed by the amount of implanted donor impurities. On the other hand, the potential upper limit value of the n-type channel in the region I II is variable and determined by the gate potential by the clock pulse applied to the gate electrode 10 and the amount of the donor impurity implanted. The charges are transferred by the three potentials of these three regions.

The doping density of the substrate 2 is 1 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ³
Is.

FIG. 2 shows the impurity concentration distribution in the region I II III. The doping amount of phosphorus is small in the region I, large in the region II, and large in the region III. In the region III, the doping amount of boron is shallower than that of phosphorus.

3 (a) and 3 (b), the potential states of the three buried channel regions in each cell under given gate potential conditions are shown as a function of the distance from the surface of the semiconductor. FIG. 3 (a) shows the potential state of the region I II III when the gate is turned on (the state where the voltage is applied to the gate electrode 10 with respect to the substrate).

FIG. 3 (b) shows the potential state of the region I II III when the gate is off (state where no voltage is applied to the gate electrode 10).

As can be seen from FIGS. 3 (a) and 3 (b), the following relationship holds between the maximum potential values φmax of the respective regions when the gate is on.

φmax II> φmax I> φmax III On the other hand, the following relationship holds when the gate is off.

φmax III> φmax II> φmax I The charge transfer is performed by repeating the on / off state of the gate voltage (voltage applied to the gate electrode 10).

In FIG. 4, the maximum value φmax of the potential in each region is represented by a stepwise pattern of potential wells. In the case of the gate-on state, it is represented by a potential well pattern indicated by a thick line, and the pattern is a three-stage potential pattern starting from the region III and moving down to the right side, and the region II is at the lowest level. On the other hand, in the case of the gate-off state, the potential is a three-step potential pattern that starts from the region I and moves down to the right.

For example, considering the signal charge accumulated in the area II,
Since φmax in the region II is the highest when the gate is on, the electron charge is confined in this region. When the gate is turned off, both φmax II and φmax I decrease. At this time, since the region III is shielded from the gate potential by the inversion layer of the p-type region 6, φmax III
Is constant. At this point, the potential of the region III becomes higher than that of the region II, so that the signal charges move to the region III. The P-type region 6 forms a virtual electrode. When the gate potential is pulled up to the ON state again, the charge is directed in the region II because the charge is directional as described later.
Flow from I to region II through region I to the right in FIG. In this way, charge transfer is performed by applying a pulse to the gate electrode 10.

FIG. 5 shows a cross section of another embodiment of the charge transfer device according to the present invention.

In this embodiment, the buried channel of the region I II is formed to have the same potential, and the potential of the region II is changed to the potential of the region I by applying different voltages to the gate electrodes 10a and 10b on the region I II. It is supposed to be larger than.

The charge transfer operation by applying a voltage to the gate electrode 10 of the embodiment shown in FIG. 1 will be described with reference to FIG.

Each gate electrode is sequentially connected to three-phase pulse generation sources 132, 134 and 136 through the accordion circuit 120. It is assumed that no charge is stored in the region III of the cell 201. First, when a pulse is applied to the electrode 201, the region I II below the electrode 201 has a large potential, and the charges accumulated in the region III of the cell 202 move to the region II through the region I below the electrode 101. Next, when the pulse is not applied to the electrode 201, the potential of the region I II below the electrode 201 becomes smaller and the potential of the region II becomes smaller than that of the region III, so that the charges accumulated in the region II are stored in the cell 201.
Move to Area III.

Next, the electrode 101 is not applied with a voltage, and the electrode 102 is
When a pulse is applied to the electrode 102, the potential under the electrode 102 becomes large, and the region I II under the electrode 102 becomes the region II of the cell 203.
Since the potential is larger than I, the area II of cell 203
The charges stored in I move to the region II through the region I below the electrode 102. At this time, the region II below the electrode 102 has a larger potential than the region III of the cell 202, but the charge accumulated in the region III of the cell 202 moves to the region III of the cell 201 by the above operation. Therefore, the electric charge accumulated in the region III of the cell 202 is stored in the electrode 102.
It does not enter the lower area II.

When the pulse is no longer applied to the electrode 102, the potential of the region I II below the electrode 102 becomes small, and the charges that have moved to the region II below the electrode 102 move to the region III of the cell 202.

Similarly, by turning the pulse on and off to the electrode 103, the cell 2
The charge accumulated in the region III of 04 is stored in the region III of cell 203.
Move to. Next, by similarly turning on / off a pulse to the electrode 104, the charge accumulated in the region III of the cell 205 is moved to the region III of the cell 204. At this time, a pulse is applied to the gate electrode (not shown) on the right side of the electrode 101 at the same time, so that the charges accumulated in the region III of the cell 201 are changed to other charges.
It is transferred to a CCD or the like (not shown).

A pulse is then applied to electrodes 102 and 105, causing cell 20
The charge accumulated in the region III of cell 3 is transferred to the region III of cell 202.
And the charge stored in the region III of the cell 206 is transferred to the cell 205.
Move to Region III of. In this way, charges are sequentially transferred. That is, a pulse is sequentially applied to the first three electrodes to transfer three charges, and then a pulse is sequentially applied to the first three electrodes and the next three electrodes to transfer six charges. Further, pulses are sequentially applied to these 6 electrodes and the next 3 electrodes to transfer 9 charges. The accordion circuit 120 controls the pulse applied to each electrode in this way.

As shown in FIG. 7, when the gate electrodes are provided above the regions 12, respectively, the pair of gate electrodes above the regions I II are different so that the region II has a larger potential than the region I. The voltage may be applied simultaneously, or the voltage may be applied to the pair of electrodes sequentially.

FIG. 8 shows an example of the charge transfer and the pulse voltage applied to each gate electrode when the charge transfer device of the present invention is used as an imaging device.

In FIG. 8, at time 0, gates 114 and 113
Pulse is applied to the gates and no pulse is applied to the gates 111 and 112. Therefore, the electric charge A accumulated in the cell 215 has moved to the region II below the gate 114. Time t
When the gate 112 is turned on at 1 and the gate 114 is turned off at time t2, the charge A that has moved to the region II below the gate 114 moves to the region II below the gate 113. When the gate 111 is turned on at the time t3 and the gate 113 is turned off at the time t4, the charge A that has moved to the region II below the gate 113 moves to the region II below the gate 112. When the gate 112 is turned off at time t6, the gate 1
The charge A that has moved to the region II below 12 moves to the region II below the gate 111. Further, at time t8, gate 111
Is turned off, the charge A that has moved to the region II below the gate 111 moves to the horizontal transfer CCD 302. In this way, the charges A accumulated in the cell 215 are horizontally transferred to the horizontal transfer CCD 302 horizontally one row at a time. The charge A transferred to the horizontal transfer CCD 302 is horizontally transferred by the horizontal transfer CCD 302 and output as an output of one scanning line in the horizontal scanning period T11.

During the vertical transfer of the electric charge A, the gate 111 is turned on at the same time as the gate 111 is turned on at time t3, and the electric charge B accumulated in the region III of the cell 216 is gated.
115 Move to Region II below. Further, when the gate 114 is turned on at time t5, the gate 113 is turned on at time t7, and the gate 115 is turned off at time t8, the charge B transferred to the region II below the gate 115 is transferred to the region I below the gate 114.
Go to I. Similarly, the charge B is transferred to the horizontal transfer CCD 302, is horizontally transferred by the horizontal transfer CCD 302, and is output as an output of one scanning line in the horizontal scanning period T12.

The charges thus accumulated are sequentially read out.

According to the present embodiment, all the parts without the gate electrode are the regions.
III, and the p-type region 6 is formed on the n-type region 4 having a uniform impurity distribution. Therefore, for example, after forming the gate electrode on the surface of the region I II, the region III can be formed by implanting or diffusing the impurity into the region III using the gate electrode as a mask. In the region III, the p-type region 6 may be formed on the n-type region 4 having a uniform impurity distribution.
It is easier to manufacture than an n-type region 4 having a different impurity distribution and a p-type region formed thereon.

In addition, all the parts without the gate electrode are the region III,
Since the regions I II and III are composed of three regions having different potentials, the density can be increased as compared with the conventional region composed of four regions, and the resolution is improved when used as an image sensor.

An embodiment of the manufacturing process of the charge transfer device of the present invention is the ninth embodiment.
This is shown in Figures (a)-(d).

First, a p-type single crystal silicon substrate 2 having a doping density of 2 × 10 ¹⁵ / cm ³ as shown in FIG. 9A is used. An oxide layer 14 is formed on the surface of the p-type substrate 2 by an oxidation method.
To a desired thickness, eg 300 Angstroms.

Next, as shown in FIG. 9A, phosphorus (P) is implanted through the oxide layer 14 at an energy of 200 keV and a dose of 3 × 10 ¹² / cm ² . As a result, the n channel portion of the region I is formed.

Next, as shown in FIG. 9B, a mask 22 having an opening in the region II is formed, and phosphorus (P) is implanted through the oxide layer 14 at an energy of 200 keV and a dose of 1 × 10 ¹² / cm ² . By this implantation and the implantation shown in FIG. 9A, the n-channel portion of the region II is formed.

Further, as shown in FIG. 9C, a mask 24 having an opening in the region III is formed, and phosphorus (P) is passed through the oxide layer 14.
With energy of 200 keV and a dose of 3 × 10 ¹² / cm ² . By this implantation and the implantation of FIGS. 9 (a) and 9 (b), the area
The n-channel portion of III is formed.

Further, as shown in FIG. 9 (d), a mask 24 similar to that shown in FIG. 9 (c) is formed, and boron (B) is implanted through the oxide layer 14 at an energy of 200 keV and a dose of 1 × 10 ¹³ / cm ² . By this implantation, the p-type region 6 to be the virtual electrode of the region III is formed.

Note that heat treatment is performed after the implantation of each impurity, and the implanted impurities are diffused into silicon to an appropriate depth to form a correct potential distribution state.

After the n-type region 4 and the p-type region 6 are formed in this manner, the gate electrode 10 is formed on the oxide layer 14 in the region III, and the PSG passivation film 12 is formed on the upper surfaces of the gate electrode 10 and the region III. For example, the charge transfer device shown in FIG. 1 can be obtained.

It should be noted that CC of p-type channel is made of n-type silicon substrate
When manufacturing D, the polarities may be reversed. Also,
A semiconductor containing a III-V or II-IV compound such as indium antimonide or mercury cadmium telluride may be used.

Effect Since the charge transfer device according to the present invention has a uniform potential in the region where the inversion layer without a gate electrode is formed, it is easy to implant or diffuse impurities.
Easy to manufacture.

Further, the density can be increased as compared with the conventional case where the region where the inversion layer is formed is composed of two regions.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the charge transfer device according to the present invention, FIG. 2 is a graph showing an impurity concentration distribution in a region I II III, and FIG. 3 (a) is a region I II III when the gate is on.
Fig. 3 (b) is a graph showing the potential state of the region I II III when the gate is off.
4 is a graph showing potential states in FIG. 4, FIG. 4 is a graph showing potential wells in respective regions, FIG. 5 is a sectional view showing another embodiment of the charge transfer device according to the present invention, and FIG. 6 is charge transfer of FIG. FIG. 7 is a diagram showing a drive circuit of the device, FIG. 7 is a diagram showing a drive circuit of the charge transfer device of FIG. 2, and FIG. 8 is a charge transfer of an apparatus using the charge transfer device of FIG. The figure which shows the example of the pulse voltage applied to a gate electrode, FIGS. 9 (a)-(d) are figures which show the manufacturing process of the charge transfer device shown in FIG. Explanation of symbols for main parts 2 ... Substrate 4 ... N-type region 6 ... P-type region 8 ... Insulating film 10 ... Gate electrode 10a ... Gate electrode 10b ... Gate electrode

Claims (4)

[Claims] 1. A one-conductivity-type semiconductor substrate on one main surface,
Having a reverse conduction type buried channel including a plurality of cells,
A gate electrode is formed on a part of the semiconductor surface of each cell, and a part of each cell is selectively protected from a gate-induced potential change by an inversion layer formed on the semiconductor surface where the gate electrode is not formed. In the charge transfer device, the potential of each device is uniform in the region where the inversion layer is formed, and at least two potentials are formed in the region where the gate electrode is formed. A charge transfer device characterized in that 2. The charge transfer device according to claim 1, wherein the region where the gate electrode is formed is composed of two regions having different impurity concentrations. 3. The device according to claim 1, wherein the region where the gate electrode is formed has a uniform potential, and the gate electrode formed in the region is composed of a pair of electrodes. Charge transfer device characterized by. 4. The device according to any one of claims 1 to 3, wherein the semiconductor substrate is p-type silicon and the buried channel exhibits n-type conductivity. Charge transfer device.