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JPH0714057B2 - Field effect transistor - Google Patents
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JPH0714057B2 - Field effect transistor - Google Patents

Field effect transistor

Info

Publication number
JPH0714057B2
JPH0714057B2 JP61311365A JP31136586A JPH0714057B2 JP H0714057 B2 JPH0714057 B2 JP H0714057B2 JP 61311365 A JP61311365 A JP 61311365A JP 31136586 A JP31136586 A JP 31136586A JP H0714057 B2 JPH0714057 B2 JP H0714057B2
Authority
JP
Japan
Prior art keywords
layer
effect transistor
gaas
channel
algaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP61311365A
Other languages
Japanese (ja)
Other versions
JPS63161678A (en
Inventor
薫 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61311365A priority Critical patent/JPH0714057B2/en
Publication of JPS63161678A publication Critical patent/JPS63161678A/en
Publication of JPH0714057B2 publication Critical patent/JPH0714057B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/40FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/473High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
    • H10D30/4732High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
    • H10D30/4738High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material having multiple donor layers

Landscapes

  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明はヘテロ接合を用いた電界効果トランジスタに関
するものである。
TECHNICAL FIELD The present invention relates to a field effect transistor using a heterojunction.

従来の技術 ヘテロ接合を用いた電界効果トランジスタとして、従来
より、N型AlGaAsとノンドープGaAsのヘテロ接合界面に
たまる高移動度の2次元電子ガスを用いた高電子移動度
トランジスタ(High Electron Mobility Transistor;HE
MT)がよく知られている。
2. Description of the Related Art Conventionally, as a field effect transistor using a heterojunction, a high electron mobility transistor (High Electron Mobility Transistor) using a high mobility two-dimensional electron gas accumulated at the heterojunction interface between N-type AlGaAs and non-doped GaAs has been used. HE
MT) is well known.

発明が解決しようとする問題点 HEMTの欠点として、ヘテロ界面にたまる2次元電子ガス
の飽和濃度が低く(〜1×1012/cm2)、チャンネルの導
電率が室温で通常のGaAsのMESFETに比べて同程度かそれ
以下になること、N型AlGaAs中のDXセンターと呼ばれる
深い準位のため、光や温度に対して素子特性の変化が大
きくまた不安定であるという点があげられる。さらに、
N型AlGaAsとGaAsのコンダクションバンドの不連続量、
ΔEcが小さいため、高電界での2次元電子ガスは、AlGa
Asの障壁を越えて、GaAsよりAlGaAsにあふれ出すという
問題もある。
Problems to be Solved by the Invention The drawbacks of the HEMT are that the saturation concentration of the two-dimensional electron gas accumulating at the hetero interface is low (up to 1 × 10 12 / cm 2 ), and the conductivity of the channel is at room temperature. Compared with this, it is about the same or less, and because of the deep level called DX center in N-type AlGaAs, the change in device characteristics is large and unstable with respect to light and temperature. further,
Discontinuity of N-type AlGaAs and GaAs conduction band,
Since ΔEc is small, the two-dimensional electron gas in a high electric field is AlGa
There is also a problem that AlGaAs is overflowed from GaAs beyond the As barrier.

問題点を解決するための手段 本発明は、以上のような従来の問題点を解決する新しい
構造のヘテロ接合電界効果トランジスタを提供するもの
である。電子濃度を高めるために、チャンネル層をN型
GaAs層とノンドープのInZGa1-ZAsよりなる構成とし、さ
らに、チャンネル層を電子に対し障壁となるAlGaAs層で
挟んだ構造とするものである。チャンネル層の両側のAl
GaAs層は、ノンドープでも、N型にしてもよいが、N型
のAlGaAsを用いる場合にはAlGaAs中のAlAs組成を0.2以
下とすることにより、DXセンターの悪影響を除くことが
できる。
Means for Solving the Problems The present invention provides a heterojunction field effect transistor having a new structure that solves the above conventional problems. N-type channel layer to increase electron concentration
The structure is composed of a GaAs layer and non-doped In Z Ga 1-Z As, and the channel layer is sandwiched between AlGaAs layers that serve as barriers to electrons. Al on both sides of the channel layer
The GaAs layer may be undoped or N-type, but when N-type AlGaAs is used, the adverse effect of the DX center can be eliminated by setting the AlAs composition in AlGaAs to 0.2 or less.

作用 本発明の構造を用いることにより、電界効果トランジス
タの特性を向上させることができる。チャンネル層にた
まる電子の濃度をさらに増加するためには、チャンネル
層の両側、あるいは片側のAlGaAsにN型不純物を添加す
ればよい、この場合には、DXセンターによる悪影響を除
くためにAlGaAsのAlAs組成比を0.2以下とすることが必
要となる。
Function By using the structure of the present invention, the characteristics of the field effect transistor can be improved. In order to further increase the concentration of electrons accumulated in the channel layer, N-type impurities may be added to AlGaAs on both sides or one side of the channel layer. In this case, AlAs of AlGaAs should be removed in order to eliminate the adverse effect of the DX center. It is necessary to make the composition ratio 0.2 or less.

実 施 例 本発明の第1の実施例を第1図に示す。第1図(a)の断
面構造において、1は半絶縁性GaAs基板、2は0.1μm
の厚さのノンドープGaAs層、3は0.2μmの厚さのノン
ドープAl0.3Ga0.7As層、4及び6は、ドナー濃度4×10
18/cm3の膜厚が50ÅのN型GaAs層、5はノンドープのIn
ZGa1-ZAs層、7は、膜厚200ÅのノンドープのAl0.3Ga
0.7As層である。InZGa1-ZAs層の厚さは100Å、zは0.25
とした。N型GaAs層(4及び6)とIn0.25Ga0.75As層5
によってチャンネル層が形成され、電子濃度は最大4×
1012/cm2と非常に高い値を示した。Al0.3Ga0.7As層(3
及び7)は、チャンネル層に閉じ込めるための障壁層で
ある。8はソース電極、9はドレイン電極、10はゲート
電極を示し、MIS(Metal−Insulator−Semiconductor)
型の電界効果トランジスタが構成される。第1図(b)
は、チャンネル層近傍のバンドダイアグラムを示す。
Example 1 A first example of the present invention is shown in FIG. In the sectional structure of FIG. 1 (a), 1 is a semi-insulating GaAs substrate, 2 is 0.1 μm.
Non-doped GaAs layer with a thickness of 3 μm, a non-doped Al 0.3 Ga 0.7 As layer with a thickness of 0.2 μm, and a donor concentration of 4 × 10 4.
18 / cm 3 N-type GaAs layer with a film thickness of 50 Å, 5 is undoped In
Z Ga 1-Z As layer, 7 is undoped Al 0.3 Ga with a film thickness of 200Å
It is the 0.7 As layer. In Z Ga 1-Z As layer thickness is 100Å, z is 0.25
And N-type GaAs layers (4 and 6) and In 0.25 Ga 0.75 As layer 5
The channel layer is formed by the
It showed a very high value of 10 12 / cm 2 . Al 0.3 Ga 0.7 As layer (3
And 7) are barrier layers for confining in the channel layer. MIS (Metal-Insulator-Semiconductor) 8 is a source electrode, 9 is a drain electrode, and 10 is a gate electrode.
Type field effect transistor is constructed. Fig. 1 (b)
Shows a band diagram near the channel layer.

チャンネル層のN型GaAsは、それ自身導電層としても働
くが、InZGa1-ZAs層への電子供給層としても作用する。
すなわち第1図(b)のバンドダイアグラムに示すよう
に、InZGa1-ZAsの量子井戸にN型GaAs層から電子が供給
されN−AlGaAs/GaAsで構成されたHEMTにおけるN−AlG
aAsと同様な役目を果すことになる。N型GaAsを電子供
給層として用いる利点は、高いドナー濃度(6〜8×10
18/cm3)を得ることができるため、所望の電子濃度をIn
ZGa1-ZAs層にためるためのN型GaAs層厚を薄くできるこ
と、N−AlGaAsのようにDXセンターの悪影響がないこと
であり、高い相互コンダクタンスをもつ、素子特性の安
定な電界効果トランジスタを得るのに好適である。また
チャンネル層をAlGaAs層で挟んだ構造とすることによ
り、InZGa1-ZAsにたまった電子から見て、障壁の高さを
十分に高くでき、高電界での熱い電子が、InZGa1-ZAs量
子井戸をあふれ出したとしても、AlGaAs層の障壁によ
り、電子の、チャンネル層内にとどまる確率が増える。
チャンネル層はGaAsと、InZGa1-ZAs層で構成されている
ので、電子が、チャンネル層内にとどまる限り、高い飽
和速度が維持されることになる。また、チャンネル層内
の電子の大部分は、ノンドープInZGa1-ZAs層にたまるた
め、電子の移動度及び、飽和速度もGaAs単独のチャンネ
ル層に比べて高くなる。
N-type GaAs channel layer is also serves as its own conductive layer also acts as an electron supply layer of the In Z Ga 1-Z As layer.
That is, as shown in the band diagram of FIG. 1 (b), N-AlG in HEMT constituted by an In Z Ga 1-Z electrons from N type GaAs layer into the quantum well of As are supplied N-AlGaAs / GaAs
It will play the same role as aAs. The advantage of using N-type GaAs as the electron supply layer is that it has a high donor concentration (6-8 × 10
18 / cm 3 ) can be obtained, so the desired electron concentration
A field-effect transistor that has a high mutual conductance and stable element characteristics, because the N-type GaAs layer for accumulating the Z Ga 1-Z As layer can be thinned and the DX center does not have a bad effect unlike N-AlGaAs. Is suitable for obtaining Further, by the sandwiched channel layer of AlGaAs layers, In viewed from Z Ga 1-Z As the accumulated electrons can sufficiently increase the height of the barrier, the hot electrons in the high electric field, In Z Even if the Ga 1-Z As quantum well overflows, the barrier of the AlGaAs layer increases the probability of electrons staying in the channel layer.
Channel layer and GaAs, which is configured by In Z Ga 1-Z As layer, electrons, as long stay in the channel layer, so that high saturation velocity is maintained. The electronic majority of the channel layer, since the accumulated non-doped In Z Ga 1-Z As layer, the electron mobility and saturated velocity becomes higher than the channel layer of GaAs alone.

本発明の第2の実施例を第2図に示す。第2図は、第1
図(a)におけるチャンネル層の構成を、N型GaAs層4
と、その上に形成した100ÅのノンドープIn0.25Ga0.75A
sとしたもので、N型GaAsの膜厚を100Å、ドナー濃度を
4×1018/cm3とした。この場合にも、チャンネルにたま
る電子濃度として4×1012/cm2が得られた。
A second embodiment of the present invention is shown in FIG. FIG. 2 shows the first
The structure of the channel layer in FIG.
And 100Å undoped In 0.25 Ga 0.75 A formed on it
s, the N-type GaAs film thickness was 100Å, and the donor concentration was 4 × 10 18 / cm 3 . Also in this case, the electron concentration accumulated in the channel was 4 × 10 12 / cm 2 .

第1の実施例および第2の実施例におけるノンドープの
Al0.3Ga0.7As層をAl0.2Ga0.8As層に置きかえ、かつ、Al
0.2Ga0.8As層の1部にN型不純物を1×1018/cm3ドープ
したところ、どちらの場合にも電子濃度として5〜6×
1012cm2という値を得た。
In the first and second embodiments, the undoped
Replace the Al 0.3 Ga 0.7 As layer with the Al 0.2 Ga 0.8 As layer, and
One part of the 0.2 Ga 0.8 As layer was doped with N-type impurities at 1 × 10 18 / cm 3 and the electron concentration was 5-6 × in both cases.
A value of 10 12 cm 2 was obtained.

以上の実施例における電界効果トランジスタでは、温度
や光によるしきい値電圧の変化やFET特性の大幅な変化
は見られず、従来のN−AlGaAs/GaAs系HEMTに比べ特性
が安定であった。
In the field effect transistor in the above-described examples, no change in the threshold voltage due to temperature or light and no drastic change in FET characteristics were observed, and the characteristics were stable as compared with the conventional N-AlGaAs / GaAs HEMT.

発明の効果 以上述べたように、本発明のヘテロ接合電界効果トラン
ジスタでは、従来のHEMTの様なN型AlXGa1-XAs(x〜0.
3)中のDXセンターによる特性の不安定さを無くすこと
ができるばかりでなく、チャンネル層に、高い電子濃度
を供給するN型GaAsと電子のたまるInZGa1-ZAsを用いて
いるので、チャンネル内に高移動度の高い電子濃度を実
現できる。また、InZGa1-ZAsの量子井戸中を電子は主と
して走行するので、チャンネル外部のAlGaAs障壁層のAl
組成比が0.2以下であっても、電子に対して十分高い障
壁となり、高電界において電子がチャンネルよりあふれ
出す確率を低下させられる。従って本発明の構造を用い
ることにより、高い相互コンダクタンスを有した、温
度、光に対して特性の安定なヘテロ接合電界効果トラン
ジスタを実現できる。なお、InZGa1-ZAs層の膜厚として
は、50Å〜150Åが適切であり、zの値としては0.25以
下が、膜内に転位の入らない条件として適している。
Effect of the Invention As described above, in the heterojunction field effect transistor of the present invention, N-type Al X Ga 1-X As (x to 0.
3) it is possible not only to eliminate the DX center by instability of the characteristics in, the channel layer, because of the use of In Z Ga 1-Z As accumulate the N-type GaAs and an electron supplying high electron density A high electron concentration with high mobility can be realized in the channel. Also, since electrons mainly travel in the In Z Ga 1-Z As quantum well, the Al of the AlGaAs barrier layer outside the channel is
Even if the composition ratio is 0.2 or less, it acts as a sufficiently high barrier against electrons, reducing the probability that electrons will overflow from the channel in a high electric field. Therefore, by using the structure of the present invention, a heterojunction field effect transistor having high transconductance and stable characteristics with respect to temperature and light can be realized. Incidentally, the thickness of the In Z Ga 1-Z As layer, 50A~150A is appropriate, as the value of z is 0.25 or less, is suitable as a condition for not enter dislocation in the film.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)および第2図は、本発明の第1,第2の実施例
としての電界効果トランジスタの素子構造を示す断面
図、第1図(b)は同第1の実施例におけるチャンネル層
付近の伝導帯エネルギーバンドダイアグラムである。 1……半絶縁性GaAs基板、2……ノンドープGaAs層、3,
7……ノンドープAl0.3Ga0.7As層、4,6……N型GaAs層、
5……ノンドープInZGa1-ZAs層、8……ソース電極、9
……ドレイン電極、10……ゲート電極。
1 (a) and 2 are sectional views showing the element structure of the field effect transistor as the first and second embodiments of the present invention, and FIG. 1 (b) is the same as the first embodiment. It is a conduction band energy band diagram near a channel layer. 1 ... Semi-insulating GaAs substrate, 2 ... Non-doped GaAs layer, 3,
7 ... Non-doped Al 0.3 Ga 0.7 As layer, 4, 6 ... N-type GaAs layer,
5 ... Non-doped In Z Ga 1-Z As layer, 8 ... Source electrode, 9
...... Drain electrode, 10 …… Gate electrode.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】AlGaAs障壁層にチャンネルが挟まれ、前記
チャンネル層がN型GaAs電子供給層とノンドープのInGa
As量子井戸層で構成されるヘテロ接合構造を用いてなる
電界効果トランジスタ。
1. A channel is sandwiched between AlGaAs barrier layers, said channel layer being an N-type GaAs electron supply layer and non-doped InGa.
A field-effect transistor using a heterojunction structure composed of As quantum well layers.
【請求項2】AlGaAs障壁層のAlAs組成比0より大きくか
つ0.2以下であり、前記AlGaAs障壁層の一部にN型不純
物がドープされたことを特徴とする特許請求の範囲第1
項に記載の電界効果トランジスタ。
2. The AlAs composition ratio of the AlGaAs barrier layer is greater than 0 and 0.2 or less, and a part of the AlGaAs barrier layer is doped with N-type impurities.
A field effect transistor according to item.
JP61311365A 1986-12-25 1986-12-25 Field effect transistor Expired - Fee Related JPH0714057B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61311365A JPH0714057B2 (en) 1986-12-25 1986-12-25 Field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61311365A JPH0714057B2 (en) 1986-12-25 1986-12-25 Field effect transistor

Publications (2)

Publication Number Publication Date
JPS63161678A JPS63161678A (en) 1988-07-05
JPH0714057B2 true JPH0714057B2 (en) 1995-02-15

Family

ID=18016289

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61311365A Expired - Fee Related JPH0714057B2 (en) 1986-12-25 1986-12-25 Field effect transistor

Country Status (1)

Country Link
JP (1) JPH0714057B2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5266506A (en) * 1990-07-31 1993-11-30 At&T Bell Laboratories Method of making substantially linear field-effect transistor
US5223724A (en) * 1990-07-31 1993-06-29 At & T Bell Laboratories Multiple channel high electron mobility transistor
JP2924239B2 (en) * 1991-03-26 1999-07-26 三菱電機株式会社 Field effect transistor
JP3173080B2 (en) * 1991-12-05 2001-06-04 日本電気株式会社 Field effect transistor
US5488237A (en) * 1992-02-14 1996-01-30 Sumitomo Electric Industries, Ltd. Semiconductor device with delta-doped layer in channel region
JPH0714850A (en) * 1993-06-15 1995-01-17 Matsushita Electric Ind Co Ltd Heterojunction field effect transistor

Also Published As

Publication number Publication date
JPS63161678A (en) 1988-07-05

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