JPH0714068B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device. In particular, GaAs
The present invention relates to an improvement in a method for manufacturing a field effect transistor. More specifically, the dielectric strength around the electrode of the GaAs field effect transistor having a structure in which the gate electrode is formed on the recess formed in the surface layer of the active layer of the GaAs field effect transistor is stressed in the active layer, Further, the present invention relates to an improvement in which the carrier concentration in the channel region of the active layer is improved and a GaAs field effect transistor having excellent characteristics can be manufactured without causing side effects such as inaccuracy.

[Conventional technology]

GaAs is easy to be semi-insulating by mixing chrome, etc., but element isolation is not always easy. Therefore, one conductivity type is directly or semi-insulating on the semi-insulating GaAs substrate. In some cases, a thin n-type GaAs layer is formed in a mesa shape, and this mesa layer is used as an active layer.

Since it is not always easy to control the impurity concentration in GaAs, the operating characteristics of the field effect transistor and the like formed on the mesa layer forming the active layer can be accurately adjusted to a desired value by adjusting the thickness of the mesa layer. A method of adjusting the value is known.

An example of the manufacturing process of the GaAs field effect transistor having such a structure will be described below.

See FIG. 7. A buffer layer 2 and an n-type GaAs layer 3 are continuously formed on the insulating GaAs layer 1, and etching is performed to leave the n-type GaAs layer 3 in a mesa shape in the element formation region. Subsequently, the silicon dioxide layer 4 is formed.

See FIG. 8. The silicon dioxide layer 4 is removed from the source / drain regions by the lithography method, and the AuGe / Au layer 5 is formed here by the lift-off method.

See FIG. 9. After forming the resist film 6, an opening 7 is formed in the gate electrode region, the silicon dioxide layer 4 is etched through this opening 7, and then the upper portion of the n-type GaAs layer 3 is etched. To form a recess. In the first half of this process, hydrofluoric acid is used as an etchant, and in the second half, a mixed solution of hydrofluoric acid and hydrogen peroxide is used as an etchant for wet etching.

The reason for forming the recess here is that the n-type Ga in the recess is
This is because it is easy to adjust the layer thickness of the As layer 3 and accurately adjust the operating voltage of the GaAs field effect transistor to be manufactured thereafter to a desired value.

See FIG. 10. An Al film 8 is formed.

See FIG. 11. The resist 6 is dissolved and removed, and the Al film 8 is removed from a region other than the gate electrode region to form a gate electrode.

Then, the silicon nitride film 9 is formed to a thickness of about 1,000 Å by plasma CVD or the like, and passivation is performed.

[Problems to be solved by the invention]

In the passivation step, which is the final step of the method for manufacturing the GaAs field effect transistor having the above-described structure, particles having a large mass collide with the AuGe / Au layer 5 at high speed, and are thus spattered and scattered. However, there is a drawback in that the withstand voltage of this region is lowered and the characteristics are deteriorated.

This drawback is that, for example, before the step of forming the passivation film by using the plasma CVD method, the cover film is formed in the region around the gate electrode by using the normal CVD method or the like in which the above-mentioned reverse sputtering does not occur. There is a possibility that the problem can be solved by forming a film and covering a region around the gate electrode. However, when a double layer of a normal insulating film and a plasma CVD insulating film is formed in the region around the gate electrode in this way, stress based on this double layer, particularly compressive stress, is applied to the periphery of the gate electrode, The above method is practically difficult to use because the electric field distribution in the lower region is distorted.

Further, the above method results in covering the periphery of the gate electrode with a layer containing Si (SiO ₂ layer, PSG layer, etc.), so that this Si diffuses into the active layer as an n-type dopant, As a result, the carrier concentration of is changed, and also from this point, the above method cannot be actually used.

An object of the present invention is to make a passivation film of a GaAs field effect transistor having a structure in which a gate electrode is formed on a recess provided in a surface layer of a GaAs active layer, particles having a large mass such as a plasma CVD method, collide with a base at a high speed. In the process of forming using a deposition method that has an opportunity to do so, it is possible to eliminate the spattering and scattering of the metal by the plasma during the plasma CVD process without any side effect and to prevent the metal around the gate of the GaAs field effect transistor. It is an object of the present invention to provide an improvement that prevents the breakdown voltage from decreasing.

[Means for solving problems]

The means adopted by the present invention to achieve the above object is Ga
As the source / drain electrode (5) is formed on the active layer (3) so as to be separated from each other, and the GaAs active layer (3) including the source / drain electrode (5). ), An insulating film (10) is formed using an atmospheric pressure CVD method, and an opening is formed on the GaAs active layer (3) between the source electrode and the drain electrode (5). A step of forming a mask (6) having (7), and in the opening (7) of the mask (6), one of the insulating film (10) and the GaAs active layer (3) is formed. Part of the GaAs active layer (3) is removed to form a recess (7) in the GaAs active layer (3), and the gate electrode (8) is formed on the bottom surface of the recess (7). The step of removing (6) and the plasma CVD method are used to form the insulating film (10).
And depositing a passivation film (9) on the gate electrode (8) and on the surface of the GaAs active layer in the recess (7) in which the gate electrode (8) is formed. And a method of manufacturing a semiconductor device.

[Action]

The above-mentioned drawbacks are caused by the fact that the particles having a large mass collide with the underlying metal such as the AuGe / Au layer 5 at high speed in the passivation process, so that such particles do not collide with the underlying metal. Alternatively, the underlying metal may not be sputtered even if it collides.

What is important here is that the above-mentioned side effects (the formation of a thick cover amount causes stress in the channel region, and the strain based on the stress distorts the electric field distribution in the channel region or causes undesired dopants. Side effects such as (Si) diffusing into the active layer and changing the carrier concentration in the channel region).

Therefore, in the present invention, except for the gate electrode region,
The underlying metal is covered with an oxide film.

〔Example〕

Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be further described with reference to the drawings.

See FIG. 2. A buffer layer 2 and an n-type GaAs layer 3 are continuously formed on the insulating GaAs layer 1, and etching is performed to leave the n-type GaAs layer 3 in a mesa shape in the element formation region. Subsequently, the silicon dioxide layer 4 is formed.

See FIG. 3. The silicon dioxide layer 4 is removed from the source / drain regions by the lithography method, and the AuGe / Au layer 5 is formed there by the lift-off method.

See FIG. 4. The silicon dioxide film 10 is formed by using the atmospheric pressure CVD method.

See FIG. 5. After forming the resist film 6, an opening 7 is formed in the gate electrode region, the silicon dioxide layers 10 and 4 are etched through the opening 7, and then the upper portion of the n-type GaAs layer 3 is removed. Etch to form recess. In the first half of this step, hydrofluoric acid is used as an etchant, and in the second half, a mixed solution of hydrofluoric acid and hydrogen peroxide is used as an etchant for wet etching.

See FIG. 6. An Al film 8 is formed, and the Al film 8 is removed from a region other than the gate electrode region to form a gate electrode. In this step, the lift-off method is used to dissolve and remove the Al film 8 together with the resist 6.

As a result of this step, except for the periphery of the gate electrode 8, the n-type
The surface of the GaAs layer 3 will be covered by the silicon dioxide layer 10.

Referring to FIG. 1, a plasma CVD method or the like is used to form a silicon nitride film 9 having a thickness of about 1,000 Å and passivation is performed.

Since the source / drain electrode 5 is covered with the silicon dioxide layer 10, the source / drain electrode 5 made of AuGe / Au is not directly exposed to plasma in this step, so that this metal is sputtered and recessed. Defects such as adhesion to the inside or the gate electrode 8 to lower the breakdown voltage have been solved.

Moreover, since the silicon dioxide layer 10 does not exist around the gate electrode, the above-mentioned side effects (the formation of a thick cover layer causes stress in the channel region,
Due to the stress-based strain, the electric field distribution in the channel region may be distorted, and undesired dopant (Si) may diffuse into the active layer to change the carrier concentration in the channel region. That's not it.

〔The invention's effect〕

As described above, in the present invention, the dielectric strength around the electrodes of the GaAs field effect transistor having a structure in which the gate electrode is formed on the recess formed in the surface layer of the active layer of the GaAs field effect transistor Stress, and without the side effect of inaccurate carrier concentration in the channel region of the active layer,
It is possible to provide a method for manufacturing a semiconductor device capable of manufacturing a GaAs field effect transistor having improved characteristics.

[Brief description of drawings]

FIG. 1 is a sectional view of a GaAs field effect transistor manufactured by carrying out the method for manufacturing a semiconductor device according to an embodiment of the present invention. 2 to 6 are cross-sectional views after completion of the main steps of the method of manufacturing a GaAs field effect transistor according to one embodiment of the present invention. 7 to 11 are cross-sectional views after completion of the main steps of the method of manufacturing a GaAs field effect transistor according to the prior art. 1 ... Insulating GaAs layer, 2 ... Buffer layer, 3 ... N-type GaAs layer, 4 ... Silicon dioxide layer, 5 ... AuGe.Au layer (source / drain electrodes), 6 ... Resist film, 7 ...
Opening, 8 ... Al film (gate electrode), 9 ... Silicon nitride film, 10 ... Silicon dioxide film.

Claims (1)

[Claims] 1. A GaAs active layer (3) spaced apart from each other,
Forming a source electrode / drain electrode (5);
As an active layer (3), an insulating film (1
0), and the Ga between the source electrode and the drain electrode (5).
As a step of forming a mask (6) having an opening (7) on the active layer (3), and the insulating film (10) and the GaAs in the opening (7) of the mask (6). Forming a recess (7) in the GaAs active layer (3) by removing a part of the active layer (3); and forming a gate electrode (8) on the bottom surface of the recess (7). The step of removing the mask (6), and the recess in which the insulating film (10), the gate electrode (8), and the gate electrode (8) are formed by using a plasma CVD method. (7) a step of depositing a passivation film (9) on the surface of the GaAs active layer in (7), and a method of manufacturing a semiconductor device.