JPH0714108B2 - Multilayer wiring board and manufacturing method thereof - Google Patents
Multilayer wiring board and manufacturing method thereofInfo
- Publication number
- JPH0714108B2 JPH0714108B2 JP60162858A JP16285885A JPH0714108B2 JP H0714108 B2 JPH0714108 B2 JP H0714108B2 JP 60162858 A JP60162858 A JP 60162858A JP 16285885 A JP16285885 A JP 16285885A JP H0714108 B2 JPH0714108 B2 JP H0714108B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- layer
- insulating
- wiring board
- multilayer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】 [発明の利用分野] 本発明の電子計算機などに使用されるLSI搭載のための
多層回路基板とくに有機物で絶縁層を形成する薄膜多層
回路基板に関するものである。Description: FIELD OF THE INVENTION The present invention relates to a multi-layer circuit board for mounting LSI used in a computer of the present invention, and more particularly to a thin film multi-layer circuit board having an insulating layer formed of an organic material.
[発明の背景] 従来より多層回路基板の高精度,高機能化をはかるため
に有機絶縁層を使用することは、たとえば特開昭57−20
2797号公報に記載されている。上記の公報では有機絶縁
層にポリイミドを使用してその積層法について記載され
ているが、これを使用した多層基板の使用状態に対する
信頼性の配慮については何等記載されていない。すなわ
ち、高精度,高機能が要求される多層回路基板の主な用
途とは大形計算機のLSI搭載用多層回路基板であるが、
この場合には、信頼性の面からLSI搭載部の気密封止が
大前提である。その理由は、絶縁層形成時、絶縁物体
と、有機絶縁層との間に熱膨張の差で発生する応力によ
り上記両者の間に剥離しようとする力が作用する。この
力は基板の端部で最大となり、かつ有機絶縁層の膜厚が
厚ければ厚いほど大きくなる。そのため、膜の厚さには
自ら制限を受けるからである。これに対して上記公報に
記載された構成では、基板の端部に耐湿性の劣る有機物
層を含めているため、上記の力に対抗しうる力で気密を
封止することが困難であり、あえて気密の封止を行なう
とすれば、基板の裏面を気密の封止代にしなければなら
ないため、構成が複雑になる恐れがある。BACKGROUND OF THE INVENTION The use of an organic insulating layer in order to achieve high precision and high functionality of a multilayer circuit board has hitherto been disclosed in, for example, JP-A-57-20.
No. 2797. Although the above-mentioned publication describes the lamination method using polyimide for the organic insulating layer, it does not describe the consideration of the reliability in the usage state of the multilayer substrate using the same. In other words, the main application of multi-layer circuit boards that require high precision and high functionality is the multi-layer circuit board for LSI mounting on large computers.
In this case, it is a major premise to hermetically seal the LSI mounting part from the viewpoint of reliability. The reason for this is that when the insulating layer is formed, a force that tends to separate between the insulating body and the organic insulating layer due to the stress generated by the difference in thermal expansion acts between them. This force is maximum at the edge of the substrate, and becomes larger as the organic insulating layer is thicker. Therefore, the thickness of the film is limited by itself. On the other hand, in the configuration described in the above publication, it is difficult to seal the airtightness with a force capable of counteracting the above force, because the end portion of the substrate includes an organic layer having poor moisture resistance. If the airtight sealing is dared, the back surface of the substrate must be used as an airtight sealing allowance, which may complicate the configuration.
[発明の目的] 本発明は、前記従来技術の問題点を解決し、気密封止の
容易な高精度,高機能が可能な多層配線基板を提供する
ことにあり、他の目的は、確実に製造し得る多層配線基
板を提供することにある。[Object of the Invention] The present invention solves the above-mentioned problems of the prior art and provides a multi-layer wiring board capable of high precision and high performance in which airtight sealing is easy. It is to provide a multilayer wiring board that can be manufactured.
[発明の概要] 本発明の多層配線基板では、各絶縁層のうち、上層の絶
縁層の周囲がそれより下層の絶縁層の周囲を覆って絶縁
基板の周端より距離を隔てて該基板の内側に位置するよ
うに構成したことを特徴とするものである。[Outline of the Invention] In the multilayer wiring board of the present invention, of each insulating layer, the periphery of the upper insulating layer covers the periphery of the lower insulating layer and is spaced apart from the peripheral edge of the insulating substrate. It is characterized in that it is configured to be located inside.
また本発明の多層配線基板の製造方法では、A)絶縁基
板の一方の面に、該基板の周端より一定距離を残して一
層目の絶縁層を形成し、B)その一層目の絶縁層の所定
位置に導体層を形成した後、C)絶縁基板と一層目の絶
縁層,配線層との露出している面上に、該基板の周端よ
り一定距離を残しかつ一層目の絶縁層の周囲を覆って二
層目の絶縁層を形成すると共に、該二層目の絶縁層の所
定位置に導体層を形成し、D)以下、C)を同様にして
所定回数繰返し、各々の上層の絶縁層の周囲がそれより
下層の絶縁層の周囲を覆って、かつ絶縁基板の周端より
距離を隔てて該基板の内側に位置するように形成したこ
とを特徴とするものである。In the method for manufacturing a multilayer wiring board of the present invention, A) a first insulating layer is formed on one surface of the insulating substrate leaving a constant distance from the peripheral edge of the substrate, and B) the first insulating layer. C) after forming a conductor layer at a predetermined position on the exposed surface of the insulating substrate and the first insulating layer and the wiring layer, leaving a constant distance from the peripheral edge of the substrate and the first insulating layer. And a conductor layer is formed at a predetermined position on the second insulating layer so as to cover the periphery of the above, and D) and C) are similarly repeated a predetermined number of times, and each upper layer is formed. The insulating layer is formed so as to cover the surroundings of the lower insulating layer and to be located inside the insulating substrate at a distance from the peripheral edge of the insulating substrate.
[発明の実施例] 以下、本発明の実施例を示す図面について説明する。第
1図は本発明の実施例を示す薄膜多層配線基板の製作工
程図である。同(a)に示す如く、絶縁基板としてたと
えばアルミナセラミック板のあるいは厚膜多層配線板1
上面全体に、たとえば日立化成工業株式会社製のピーア
イキュ(PIQ)(商品名)をスピンナにより均一に塗布
し、これを熱処理して有機絶縁層のポリイミド層20を形
成する。然る後、ホトレジストを用いてエッチングマス
ク3を形成する。この際、スルホール形成個所にマスク
開口部40を形成し、かつ上記厚膜多層配線板1の周端よ
り一定距離50の領域のホトレジストを除去するようにす
る。ついで同図(b)に示す如く、上記エッチングマス
ク3を用いてポリイミド層20をヒドラジンヒドラートお
よびエチレンジアミンの混液あるいは02プラズマなどで
エッチングして上記レジストを除去する。ついで同図
(c)に示す如く、半導体などで用いられる方法により
配線材の成膜,ホトエッチングで配線層6を形成したの
ち、上記ポリイミド層20と同一のポリイミド層21を上記
厚膜多層配線板1の周端より一定距離50の領域,ポリイ
ミド層20および配線層6を覆うように形成する。ついで
同図(d)に示す如く、上記ポリイミド層21をパターニ
ングする。このとき、上記厚膜多層配線板1の周端より
一定距離51の領域のポリイミド層21を除去するとともに
上記配線層6に接続するマスク開口部41を形成する。つ
いで同図(e)に示す如く、上記を必要回数繰返して所
定の多層配線基板を形成する。このとき、厚膜多層配線
板1の周端よりポリイミド層の最下部外周部までの距
離、すなわち最も上層となるポリイミド層の外周部まで
の距離5xは、上記厚膜多層配線板1の周端よりポリイミ
ド層21の最下部内周部までの距離5(x−1)より小さ
く、かつ0にならないように配慮する必要がある。Embodiments of the Invention Hereinafter, drawings showing embodiments of the present invention will be described. FIG. 1 is a manufacturing process diagram of a thin film multilayer wiring board showing an embodiment of the present invention. As shown in FIG. 3A, an insulating substrate such as an alumina ceramic plate or a thick film multilayer wiring board 1 is used.
For example, PIC (trade name) manufactured by Hitachi Chemical Co., Ltd. is uniformly applied to the entire upper surface by a spinner, and this is heat-treated to form a polyimide layer 20 of an organic insulating layer. After that, an etching mask 3 is formed using a photoresist. At this time, a mask opening 40 is formed at the through-hole forming portion, and the photoresist in a region at a constant distance 50 from the peripheral edge of the thick film multilayer wiring board 1 is removed. Then, as shown in FIG. 2B, the polyimide layer 20 is etched by using the etching mask 3 with a mixed solution of hydrazine hydrate and ethylenediamine or 02 plasma to remove the resist. Then, as shown in FIG. 3C, after forming the wiring layer 6 by film formation of a wiring material and photo-etching by a method used for semiconductors or the like, the same polyimide layer 21 as the polyimide layer 20 is formed into the thick film multilayer wiring. The polyimide layer 20 and the wiring layer 6 are formed so as to cover a region at a constant distance 50 from the peripheral edge of the plate 1. Then, the polyimide layer 21 is patterned as shown in FIG. At this time, the polyimide layer 21 in a region of a constant distance 51 from the peripheral edge of the thick film multilayer wiring board 1 is removed, and a mask opening 41 connecting to the wiring layer 6 is formed. Then, as shown in FIG. 8E, the above is repeated a required number of times to form a predetermined multilayer wiring board. At this time, the distance from the peripheral edge of the thick film multilayer wiring board 1 to the lowermost outer peripheral portion of the polyimide layer, that is, the distance 5x to the outer peripheral portion of the uppermost polyimide layer is the peripheral edge of the thick film multilayer wiring board 1. It is necessary to consider so that the distance is smaller than 5 (x-1) to the innermost portion of the lowermost portion of the polyimide layer 21 and does not become zero.
これにより、本発明においては、厚膜多層配線板1上に
積層された複数のポリイミド層のうち、上層のポリイミ
ド層がそれより下層のポリイミド層の周囲を覆って、か
つ厚膜多層配線板1の周端より距離5xを残し内側に位置
する構成の多層配線基板となる。その結果、各々のポリ
イミド層の周端部が厚膜多層配線板1に対し一様に密着
し、膜厚がほぼ一定となるので、ポリイミド層の厚膜多
層配線板1からの剥離力が増大するのを防止できるばか
りでなく、ポリイミド層が剥離するのを防ぐことができ
る。そのため、安定したかつ高機能,高信頼性を得るこ
とができる。したがって、厚膜多層配線板1の周端部分
が気密封止代となるので、構成が複雑になることもな
い。Thus, in the present invention, among the plurality of polyimide layers stacked on the thick film multilayer wiring board 1, the upper polyimide layer covers the periphery of the lower polyimide layer and the thick film multilayer wiring board 1 The multilayer wiring board is configured to be positioned on the inner side with a distance 5x left from the peripheral edge. As a result, the peripheral edge of each polyimide layer uniformly adheres to the thick film multilayer wiring board 1 and the film thickness becomes substantially constant, so that the peeling force of the polyimide layer from the thick film multilayer wiring board 1 increases. Not only can it be prevented, but also the polyimide layer can be prevented from peeling off. Therefore, stable, high-performance, and high reliability can be obtained. Therefore, since the peripheral end portion of the thick film multilayer wiring board 1 serves as an airtight sealing margin, the structure does not become complicated.
そして、下層のポリイミド層20を覆う上層のポリイミド
層21は、その周端部の厚さが、各ポリイミド層の厚膜多
層配線板1の積層方向の厚さより薄くなるように形成し
ているので、ポリイミド層の剥離力が増大するのをいっ
そう防止することができ、いっそう効果的となる。The upper polyimide layer 21 that covers the lower polyimide layer 20 is formed such that the thickness of the peripheral edge portion thereof is smaller than the thickness of each polyimide layer in the stacking direction of the thick film multilayer wiring board 1. Further, it is possible to prevent the peeling force of the polyimide layer from increasing, which is more effective.
また本発明の製造方法においては、上述の如く、厚膜多
層配線板1上にその周端より一定距離50を残して一層目
のポリイミド層21を形成し、ついでその一層目のポリイ
ミド層の所定位置に配線層6を形成し、さらに、厚膜多
層配線板1と一層目のポリイミド層と配線層との露出し
ている面上に、厚膜多層配線板1の周端より一定距離51
を残して二層目のポリイミド層21を形成すると共に配線
層6を形成し、以下同様にして三層目以降のポリイミド
層と配線層とを繰返すことにより、上層のポリイミド層
の周端部がそれより下層のポリイミド層の周囲を覆っ
て、かつ厚膜多層配線板1の周端より距離5xを隔てて内
側に位置するように形成したので、多層配線基板を確実
に製造することができる。Further, in the manufacturing method of the present invention, as described above, the first-layer polyimide layer 21 is formed on the thick-film multilayer wiring board 1 leaving a constant distance 50 from its peripheral edge, and then the predetermined polyimide layer is formed. A wiring layer 6 is formed at a position, and a constant distance 51 from the peripheral edge of the thick film multilayer wiring board 1 on the exposed surface of the thick film multilayer wiring board 1, the first polyimide layer and the wiring layer.
To form the second polyimide layer 21 and the wiring layer 6, and then repeat the third and subsequent polyimide layers and the wiring layer in the same manner, so that the peripheral edge portion of the upper polyimide layer is Since it is formed so as to cover the periphery of the lower polyimide layer and to be located inside at a distance 5x from the peripheral edge of the thick film multilayer wiring board 1, it is possible to reliably manufacture the multilayer wiring board.
[発明の効果] 以上述べたように、本発明によれば、各絶縁層のうち、
上層の絶縁層がそれより下層の絶縁層の周囲を覆って、
かつ絶縁基板の周端より距離を隔てて内側に位置し、各
絶縁層の周端部の膜厚が絶縁基板に対し一様に密着し、
膜厚が一定となるように構成したので、絶縁基板に対し
絶縁層の剥離力が増大するのを防止するばかりでなく、
絶縁層が絶縁基板から剥離するのを防ぐことができる結
果、安定したかつ高機能,高信頼性を得ることができる
と云う効果がある。As described above, according to the present invention, among the insulating layers,
The upper insulating layer covers the surrounding lower insulating layer,
Also, the insulating film is positioned inside the insulating substrate at a distance from the peripheral end, and the film thickness at the peripheral end of each insulating layer is uniformly adhered to the insulating substrate.
Since the film thickness is configured to be constant, not only the peeling force of the insulating layer from the insulating substrate is prevented from increasing, but
As a result of preventing the insulating layer from peeling off from the insulating substrate, there is an effect that stable and high function and high reliability can be obtained.
また本発明方法によれば、絶縁基板の一方の面に、該基
板の周端より一定距離を残して一層目の絶縁層を形成
し、ついてその一層目の絶縁層の所定位置に導体層を形
成した後、絶縁基板と一層目の絶縁層,配線層との露出
している面上に、該基板の周端より一定距離を残しかつ
一層目の絶縁層の周囲を覆って二層目の絶縁層を形成す
ると共に、該二層目の絶縁層の所定位置に導体層を形成
し、以下、これらの露出している面上に同様にして絶縁
層および導体層を所定回数繰返し形成し、各々の上層の
絶縁層がそれより下層の絶縁層の周囲を覆って、かつ絶
縁基板の周端より距離を隔てて内側に位置するように形
成したので、多層配線基板を確実に製造し得ると云う効
果がある。Further, according to the method of the present invention, a first-layer insulating layer is formed on one surface of the insulating substrate leaving a constant distance from the peripheral edge of the substrate, and then a conductor layer is formed at a predetermined position of the first-layer insulating layer. After the formation, the insulating substrate of the first layer, the insulating layer of the first layer, and the wiring layer, on the exposed surface, leaving a certain distance from the peripheral edge of the substrate and covering the periphery of the first insulating layer, the second layer. Along with forming an insulating layer, a conductor layer is formed at a predetermined position of the second insulating layer, and thereafter, an insulating layer and a conductor layer are repeatedly formed a predetermined number of times on these exposed surfaces, Since each upper insulating layer is formed so as to cover the periphery of the lower insulating layer and be located inside at a distance from the peripheral edge of the insulating substrate, it is possible to reliably manufacture the multilayer wiring board. There is an effect to say.
第1図(a)〜(e)は本発明の実施例を示す多層配線
基板の製造工程図である。 1…厚膜多層配線板、21,22…ポリイミド層、3…エッ
チングマスク、40,41…マスク開口部、50,51…絶縁層除
去領域、6…配線層。1 (a) to 1 (e) are manufacturing process diagrams of a multilayer wiring board showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1 ... Thick film multilayer wiring board, 21, 22 ... Polyimide layer, 3 ... Etching mask, 40, 41 ... Mask opening, 50, 51 ... Insulating layer removal area, 6 ... Wiring layer.
Claims (4)
体層とを交互に積重して形成する多層配線基板におい
て、各絶縁層のうち、上層の絶縁層の周端部がそれより
下層の絶縁層の周囲を覆って、かつ絶縁基板の周端より
距離を隔てて該基板の内側に位置するように形成したこ
とを特徴とする多層配線基板。1. In a multilayer wiring board formed by alternately stacking an insulating layer made of an organic material and a conductor layer on an insulating substrate, the peripheral end portion of the upper insulating layer of each insulating layer is A multilayer wiring board formed so as to cover the periphery of a lower insulating layer and be located inside the insulating substrate at a distance from the peripheral edge of the insulating substrate.
の厚さは、絶縁基板上に積層された各絶縁層の積層方向
の厚さより薄くなるように形成したことを特徴とする特
許請求の範囲第1項記載の多層配線基板。2. The thickness of the peripheral edge portion of the upper insulating layer covering the lower insulating layer is smaller than the thickness of each insulating layer stacked on the insulating substrate in the stacking direction. The multilayer wiring board according to claim 1.
体層とを交互に積重して形成する多層配線基板におい
て、 A)絶縁基板の一方の面に、該基板の周端より一定距離
を残して一層目の絶縁層を形成し、 B)ついでその一層目の絶縁層の所定位置に導体層を形
成した後、 C)絶縁基板と一層目の絶縁層,配線層との露出してい
る面上に、該基板の周端より一定距離を残しかつ一層目
の絶縁層の周囲を覆って二層目の絶縁層を形成すると共
に、該二層目の絶縁層の所定位置に導体層を形成し、 D)以下、C)を同様にして所定回数繰返し、各々の上
層の絶縁層の周端部がそれより下層の絶縁層の周囲を覆
って、かつ絶縁基板の周端より距離を隔てて該基板の内
側に位置するように形成したことを特徴とする多層配線
基板の製造方法。3. A multilayer wiring board formed by alternately stacking an insulating layer made of an organic material and a conductor layer on an insulating substrate, wherein A) one surface of the insulating substrate is fixed from a peripheral edge of the substrate. After forming a first insulating layer with a distance left between them, B) and then forming a conductor layer at a predetermined position on the first insulating layer, and C) exposing the insulating substrate and the first insulating layer and wiring layer. A second insulating layer is formed on the surface where the second insulating layer is provided, leaving a certain distance from the peripheral edge of the substrate and covering the periphery of the first insulating layer, and a conductor is provided at a predetermined position of the second insulating layer. Layers are formed, and D) and C) are repeated a predetermined number of times in the same manner, and the peripheral edge of each upper insulating layer covers the periphery of the insulating layer below it and is separated from the peripheral edge of the insulating substrate. A method for manufacturing a multi-layer wiring board, characterized in that it is formed so as to be positioned inside the board with a space therebetween.
縁基板上に積層された各絶縁層の積層方向の厚さより薄
くなるように形成したことを特徴とる特許請求の範囲第
3記載の多層配線基板の製造方法。4. The thickness of the peripheral edge portion of the second or more insulating layers is thinner than the thickness of each insulating layer stacked on the insulating substrate in the stacking direction. A method for manufacturing a multilayer wiring board according to claim 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60162858A JPH0714108B2 (en) | 1985-07-25 | 1985-07-25 | Multilayer wiring board and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60162858A JPH0714108B2 (en) | 1985-07-25 | 1985-07-25 | Multilayer wiring board and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6224694A JPS6224694A (en) | 1987-02-02 |
| JPH0714108B2 true JPH0714108B2 (en) | 1995-02-15 |
Family
ID=15762587
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60162858A Expired - Lifetime JPH0714108B2 (en) | 1985-07-25 | 1985-07-25 | Multilayer wiring board and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0714108B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0774690B2 (en) * | 1989-05-31 | 1995-08-09 | 川崎製鉄株式会社 | Method and apparatus for melting incinerated ash |
| JPH03286597A (en) * | 1990-04-03 | 1991-12-17 | Fujitsu Ltd | Circuit board of multilayer interconnection |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57139996A (en) * | 1981-02-24 | 1982-08-30 | Nippon Electric Co | Hybrid multilayer circuit board |
-
1985
- 1985-07-25 JP JP60162858A patent/JPH0714108B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6224694A (en) | 1987-02-02 |
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