JPH0714420B2 - Electrical stimulator - Google Patents

Description

The present invention relates to an electric stimulator that forms a low-frequency stimulus that is sensitive in a living body by applying an alternating wave having two high frequencies to the living body.

Such an electric stimulator has two oscillators of several thousand (Hz), and the frequency difference between them is as low as several hundred (Hz) or less, and it is necessary to maintain a stable frequency difference accurately. I won't. Since an oscillator having this frequency difference must rely on the rating of the element, it is necessary to consider the fluctuation rate due to heat, let alone hold the frequency difference,
Require complicated configuration. Under such circumstances, it was difficult to change the frequency in various ways, save power consumption, and operate with a small power source (battery of ~ 9V).

In view of the above, it is an object of the present invention to output two alternating waves that have a small power supply and that maintain accurate frequency difference and phase difference with a simple configuration.

Hereinafter, the present invention will be described in detail with reference to examples.

(10) is the first CPU, and the first CPU (10) is the memory (RO
Clock pulse oscillator (0, M, RAM, etc.)
The program is executed in synchronism with the clock pulse of 1) and the drive pulse (DP1) with the pulse width and pulse interval according to the program is output. (11) is the second CPU,
Similar to the first CPU (10), the internal program is executed according to the clock pulse of the clock pulse oscillator (01), and the drive pulse DP2 having the pulse width and the pulse interval according to the program is output. Clock pulse oscillator (01)
May be provided for each of the first and second CPUs.

The output of the first CPU (10) is connected to the base of the transistor (12). The collector side of the transistor (12) is supplied with the power supply potential + Vc via the resistor (14). The emitter side of the transistor (12) is connected to one end of the transformer (16) on the primary side. Output ends (0-1) (0-2) are connected to both ends of the secondary side of the transformer (16) and are connected to a human body through a conductor. The output of the second CPU (11) is connected to the base of the transistor (13). Transistor (1
The power supply voltage + VC is supplied to the collector side of 3) via a resistor (15). The primary side of the transformer (17) is connected to the emitter side of the transistor (13), and the other end of the primary side is grounded. Both ends of the secondary side of the transformer (17) (0
-3) (0-4) forms the output end and is connected to the human body via the conductor.

The portion including the transistor (12) (13), the power supply voltage + Vc, and the resistors (14) (15) is connected to the driver circuit and the transformer (1
6) (17) was used as the output means.

Next, the operation of FIG. 1 will be described.

The first CPU and the second CPU start the operation in synchronization with the clock pulse output from the clock pulse oscillator (01). The first CPU (10) executes the program by the internal memory in response to the clock pulse and outputs the drive pulse DP1 shown in FIG. 2 (c). The second CPU (11) outputs the drive pulse DP2 shown in FIG. 2 (d) according to the synchronization signal. The drive pulse DP1 and the drive pulse DP2 have different frequencies and phases, and the difference is, for example, 1 (Hz) to
It reaches the range of several hundreds (Hz). In this embodiment, drive pulse
The period of DP1 was 250 (μsec) and the duty was 50%, and the drive pulse PP2 was 249.5 (μsec) and the duty was 50%.

The drive pulse DP1 is input to the transistor (12),
When the drive pulse DP1 changes from the low (“L”) level to the high (“H”) level, the transistor (12) turns on and the power supply voltage + Vc passes through the resistor (14) to the transformer (16).
Applied to the primary side of the. The primary side of the transformer (16) is excited, a change in the primary side exciting current, a voltage (PW1) according to the turns ratio, and Fig. 2 (b) are generated on the secondary side of the transformer (16). When the transistor (12) goes from the high (“H”) level to the (“L”) level, the energy stored in the primary side of the transformer (16) moves to the secondary side and the reverse voltage (NW
1) occurs.

Further, next, when the drive pulse DP1 changes from the low (“L”) level to the high (“H”) level, the transistor (12) is turned on as described above, the exciting current flows, and the power supply voltage is supplied to the secondary side. When a voltage (PW2) is generated by multiplying + Vc by the amount of change in the exciting current and the turns ratio, and the transistor (12) is turned off, when the transistor (12) is on, the primary side of the transformer (16) The stored energy is transferred to the secondary side, and a reverse voltage (NW2) is generated.

When the drive pulse is continuously input to the transistor, the alternating wave shown in FIG. 2 (e) is output with respect to FIG. 2 (c).

This alternating wave has a power supply voltage of 5 for example, which is supplied to the primary side.
(V), if the turns ratio is 1: 2, the peak to peak of the alternating wave output to the secondary side can be set to 20 (V).

The drive pulse DP2 is input to the transistor (13),
When the drive pulse DP2 changes from low (“L”) level to high (“H”) level, the transistor (13) turns on and the power supply voltage + Vc passes through the resistor (15) to the transformer (17).
Applied to the primary side of the. The primary side of the transformer (17) is excited, and the secondary side of the transformer (17) generates a voltage (PW1) according to the change amount of the primary side exciting current and the turns ratio, causing the transistor (13) to go high. When the (“H”) level is changed to the low (“L”) level, the exciting current of the transformer (17) is cut off and a voltage (NW1) is generated in the opposite direction.

According to the drive pulse DP2, the alternating wave appearing at the secondary side output terminals (0-3) (0-4) of the transformer (17) is the frequency and phase of the alternating wave outputted to the secondary side of the transformer (16). The waveforms shown in FIG. 2 (f) are different.

Since the transistor used in the embodiment is used for driving with a small current such as a drive pulse, it is possible to enhance the switching response by using a Darlington-connection type transistor.
Further, a diode may be attached so that the emitter and collector directions are forward so that the surge voltage of the transformer generated by turning on and off the transistor is not applied to the transformer.

FIG. 3 shows another embodiment of the present invention.

The first CPU (10) that starts operation by the clock pulse output from the clock pulse generation unit (10) and the clock pulse output from the clock pulse generation unit (01) and outputs the drive pulse DP1 and the second CPU (11) that outputs the drive pulse DP2 Since the structure is the same as that of the embodiment shown in FIG. 1,
The description is omitted.

The first CPU (10) is connected to the base of the transistor (12). On the emitter side of the transistor (12), a transformer (1
One end of the primary side of 6) is connected and the other end of the primary side is a resistor (14)
It is connected to the power supply voltage + Vc via. The collector side of the transistor (12) is grounded. Both ends on the secondary side of the transformer (16) form output ends (0-1) (0-2).

The second CPU (11) is connected to the base of the transistor (11). On the emitter side of the transistor (12), a transformer (1
One end of the primary side of 7) is connected, and the other end of the primary side is connected to the power supply voltage + Vc via the resistor (15). Transistor (1
The collector side of 3) is grounded. 2 of the transformer (17)
Both ends on the next side form output ends (0-3) (0-4).

Next, the operation will be described.

When the drive pulse DP1 output from the first CPU is input to the transistor (12) and changes from high (“H”) level to low (“L”) level, the transistor (12) turns off and the power supply voltage + Vc and the transformer It is cut off from (16) and the exciting current on the primary side flows in a decreasing direction. At this time, a voltage corresponding to the turns ratio appears on the secondary side with respect to the changing amount of the exciting current.

Next, when the drive pulse DP1 changes from the low (“L”) level to the high (“H”) level, the transistor (12) is turned on, the power supply voltage + Vc is applied to the transformer (16) again, and the exciting current increases. It flows in the direction of doing. Therefore, one alternating wave is formed by turning the drive pulse DP1 off and on once,
Output to the output terminals (0-1) (0-2). Moreover, the voltage is boosted by the amount of change and twice the number of turns than the power supply voltage Vc.

Similarly to the drive pulse DP1, the drive pulse DP2 output from the second CPU also turns the transistor (13) on and off, forming one alternating wave by turning the transistor (13) on and off once, and the output terminal (0-3) Output to (0-4).

The waveform and amplitude of the alternating wave output to the secondary side of the transformer change according to the amount of change in the exciting current on the primary side. Therefore, by changing the exciting current by the resistor (14) connected between the primary side of the transformer (16) and the power supply voltage + Vc, alternating waves having various waveforms and amplitudes can be formed. . An inductor may be used instead of the resistor. It is also possible to use a single-winding inductor instead of the transformer.

The present invention, by a signal processing function represented by a microcomputer,
Outputs drive pulse with pulse width and pulse interval set. By changing the pulse width and the pulse interval, it is possible to output an alternating wave having a change as shown in FIG.

FIG. 4A shows the drive pulse DP1, and FIG. 4B shows the drive pulse DP2. An alternating wave shown in FIG. 4 (c) is formed for the drive pulse DP1, and an alternating wave shown in FIG. 4 (d) is formed for the drive pulse DP2. The drive pulse DP1 has a constant pulse width and pulse interval. If this frequency is exemplified as 4000 (Hz), drive pulse DP
2 changes the frequency from 4008 (Hz) to 4100 (Hz), and further 4
It was changed to 008 (Hz). The interference wave generated in the living body due to this change changes to 8 (Hz), 100 (Hz), and 8 (Hz), and the sensitivity also changes according to this change. For details, see Japanese Patent Application Nos. 57-88932, 57-226499, and 58-10779.
No. 9 and No. 59-33377.

As described above, according to the present invention, the two transistors are switched according to the drive pulses output from the two signal processing units of the first CPU and the second CPU, and the exciting current flowing in the primary side of each transformer is changed, and the change amount thereof is changed. And according to the turns ratio,
A step-up alternating wave is formed on the secondary side. The two alternating waves have a difference in either a period different from each other, a phase different from each other, or both different (collectively different phases). The frequency of the alternating waves is Since it directly corresponds to the pulse width and the pulse interval, the cycle and phase of the alternating wave can be easily set variably by a program provided inside the signal processing unit. The frequency of the alternating wave is in the range of several kHz to several tens of kHz.

The signal processing unit uses two microcomputers in synchronization with each other, or one microcomputer outputs two drive pulses, these are semi-custom ICs, and the expression is fixed by logic (gate Arrays, standard cells and other ASICs) are exemplified.

An example of a flow chart when the microcomputer is used is shown in FIG. 5 and will be described.

The content of the flowchart shows the case where the control routine of the pulse width of the drive pulse and the control routine of the pulse interval of the drive pulse are performed. Besides, there are functional routines such as a polarity conversion routine and a routine for increasing or decreasing the pulse interval.

Parameters for controlling the pulse width and interval are stored in advance in the ROM. Here, the parameters were set as follows. M ₁ : pulse width of drive pulse DP1, M ₂ : pulse interval of drive pulse DP1, M ₃ : pulse width of drive pulse DP2, M ₄ : pulse interval of drive pulse DP2. Further, the memory (register) was _{r 1, r 2, r 3} , r 4 , which is built in the microcomputer.

1) ON the start SW, to set the value of M ₃ and M ₁ to r ₃ to r _1. Drive pulse DP1 and drive pulse DP2 are "1",
That is, a high level is output.

2) Determine whether the value of r ₃ is "0", and if it is not "0", r ₃
Subtract the value of by "1", set the value of M _{4 to} r ₄ and proceed to.

3) the value of r ₃ is at "0", the drive pulse DP2 is "0" and low level is outputted. Next, the value of r _4, it is determined whether or not there is "0", if it is not a "0" proceeds drawn only 1 value of r _4. For r ₄ is "0" the drive pulse DP2 is "1" and a high level is output, the value of M ₃ progresses are stored in r _3.

4) After confirming the pulse of the clock pulse φ (output pulse from the clock pulse oscillator (01) shown in FIG. 1),
Determine whether the value of r ₁ is “0”. When the value of r ₁ is “0”,
The drive pulse DP1 becomes "0" and a low level is output. Next, it is determined whether the value of r ₂ is “0”. If the value of r ₂ is not "0" proceeds drawn value of r ₂ is only 1. r ₂
In the case of a value of "0", the drive pulse DP1 is in a state of "1", a high level is output, the value of M ₁ to r ₁ progresses been stored.

5) If the value of r ₁ is not "0", by subtracting the value of r ₁ only 1,
Set the value of M ₂ in r ₂ and proceed to.

As described above, the drive pulses DP1 and DP2 are output with desired pulse widths and pulse intervals according to the parameters M ₁ , M ₂ , M ₃ , and M ₄ .

Further, when the signal processing unit is formed by using the ASIC, it is general to digitally divide one reference oscillation pulse to generate two drive pulses. Further, when the mode is changed, the frequency divider is further divided. It can be easily implemented by adding a selector and a counter, and incorporating a few modes is fully possible with the current one-chip IC technology.

As described above in detail, the present invention has an effect that it can be simply configured by the signal processing unit, the transistor and the transformer, and that the current is consumed only during the intermittent operation of the transistor to form a sufficient alternating wave. is there.

[Brief description of drawings]

1 and 3 are circuit diagrams showing an embodiment of the present invention, and FIG.
FIG. 4 and FIG. 4 are output waveform diagrams of the above embodiment, and FIG. 5 is a flow chart showing a program of the first CPU or the second CPU in the embodiment of the present invention. 01 …… Clock pulse oscillator, 10 …… First CPU, 11 …… First
2CPU, 12,13 …… Transistor, 14,15 …… Resistance, 16,17…
… Transformer, + Vc …… Power supply voltage.

Claims (1)

[Claims] 1. A first signal processor including an algorithm for outputting a drive pulse, a first driver circuit for intermittently driving a transformer or an inductor by a drive pulse output from the first signal processor, and the transformer. Alternatively, a first output means for outputting a boosting alternating wave generated when the inductor is intermittently driven, and an algorithm for outputting a drive pulse whose phase or frequency is at least different from the drive pulse output by the first signal processor are incorporated. A second signal processor, a second driver circuit for intermittently driving a transformer or an inductor by a drive pulse output from the second signal processor, and a boosting alternating wave generated when the transformer or the inductor is intermittently driven. An electrical stimulation device comprising a second output means.