JPH0715955B2 - Nonvolatile semiconductor memory device - Google Patents

Description

The present invention relates to a non-volatile semiconductor memory device, and more particularly to a high speed ultraviolet erasable programmable read only memory device (EPROM). is there.

(Prior Art) A pattern plan view of a conventional EPROM cell array is shown in FIG. 2, and a sectional view taken along line III-III in FIG. 3 is shown in FIG.
In the figure, 1 is a source region (N ⁺ diffusion), 2 is a drain region (N ⁺
(Diffusion), 3 is a word line (second polysilicon or polycide), 4 is a floating gate (first polysilicon layer), 5 is a bit line (first aluminum wiring), 6 is a contact, 7 is a second aluminum layer, Reference numeral 8 is an insulating film, 9 is a field insulating film, and 10 is a semiconductor substrate (P type).

By the way, when implementing a high-speed EPROM, the word line (EPR
It is necessary to suppress the resistance of the control gate of the OM cell, that is, the second polysilicon layer 3) as much as possible. As one of the methods, a method of lowering resistance by a polycide technique using tungsten, titanium silicide, molybdenum, or the like can be considered. However
In the case of EPROM, the step 11 is severe as shown in FIG.
There was a drawback that it was difficult to reduce the resistance in the middle, medium and low levels. As another method, a two-layer aluminum structure can be considered.

[Problems to be Solved by the Invention] In the two-layer aluminum structure, the second aluminum layer is first
Wiring on the contact between the aluminum layer and the diffusion layer is easy to break. Therefore, in order to reduce the resistance of the word line 3 in the conventional cell as shown in FIG. 2, it is necessary to run the same signal line (second aluminum) as the word line 3 as shown by the broken line 7. In the two-layer aluminum, the step difference of the second aluminum layer is large, and the width and interval of the second aluminum layer need to be smaller than that of the first aluminum layer. Therefore, the width of the second aluminum layer 7 becomes thicker than the width of the polysilicon of the cell, and it becomes difficult for ultraviolet rays to reach the floating gate of the cell, that is, the first polysilicon layer 4, and the data erasing time becomes long.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a high-speed nonvolatile semiconductor memory device in which the data erasing time does not become long even if a two-layer aluminum structure is used.

[Structure of the Invention] (Means and Actions for Solving Problems) According to the present invention, a word line to which the same signal is applied is wired in parallel with a source line made of a diffusion layer, sandwiching the source line, An ultraviolet erasable programmable memory cell array is formed in which a first metal wire is wired at right angles to a word line to form a bit line, and a second metal wire serving as the same signal line as the word line signal is the source. The source line and the word line are wired on the wiring, and the word line and the second metal line are connected to each other, and the word line of the same signal is wired across the source line of the diffusion layer. By doing so, the margin of the width of the second metal wiring is increased to achieve the above object.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. First
The figure is a pattern plan view of the same embodiment, in which 21 is a common source region (N ⁺ diffusion), 22 is a drain region (N ⁺ diffusion), 23 is a word line (second polysilicon), and 24 is a floating gate ( The first polysilicon layer), 25 is a bit line (first aluminum wiring), 26 is a contact, and 27 is a second aluminum layer. That is, this structure has a source wiring 21 formed of a diffusion layer.
A word line 23 to which the same signal is applied is wired in parallel with the source wire 21 and is perpendicular to the word line 23.
The second aluminum wiring 27, which is the same signal line as the word line signal, is connected to the source wiring 21 and the word line 23. The EPROMs are arranged in parallel and the word lines 23 and the second aluminum wirings 27 are in contact with each other every few cells. In this case, the cell arrangement is different from that shown in FIG. 2, and two word lines 23 run in parallel with each other across the source wiring 21. Therefore, only one second aluminum wiring 27 for low resistance is required for the two word lines 23, so that ultraviolet rays can be directly applied to the floating gate as shown in FIG.
The part irradiated to 24 is easily realized.

[Effects of the Invention] As described above, according to the present invention, it is possible to reduce the resistance of a word line, which has been difficult to realize in the past, and a high-speed EPRO can be realized.
Although M is realized, since there is no metal wiring (second aluminum wiring) above the floating gate,
Data can be erased in a short time.

[Brief description of drawings]

FIG. 1 is a pattern plan view of an embodiment of the present invention, FIG. 2 is a pattern plan view of a conventional EPROM, and FIG. 3 is III- of FIG.
It is sectional drawing which follows the III line. 21 ... common source region, 22 ... drain region, 23 ... word line (second polysilicon layer), 24 ... floating gate (first polysilicon layer), 25 ... bit line (first)
Aluminum wiring), 27 ... the second aluminum layer.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 27/112 29/788 29/792 7210-4M H01L 27/10 433 (72) Inventor Shinro Otsuka Komukai-Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Inside Toshiba Research Institute Co., Ltd. (56) Reference JP-A-61-111581 (JP, A) JP-A-56-100448 (JP, A) JP-A-54 -59875 (JP, A)

Claims (1)

[Claims] 1. A bit line in which a word line to which the same signal is applied is wired in parallel with a source line made of a diffusion layer and sandwiching the source line, and a first metal line is wired at a right angle to the word line. Forming a UV erasable programmable memory cell array, and a second metal line serving as the same signal line as the word line signal is provided on the source line in parallel with the source line and the word line, A nonvolatile semiconductor memory device characterized in that a word line and a second metal wiring are connected.