JPH0716006B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an input protection circuit.

[Conventional technology]

Semiconductor devices, especially insulated gate field effect integrated circuits (MOS
-IC) uses a very thin silicon oxide film with a thickness of 20 to 30 nm as the gate insulating film, and it is easy to cause dielectric breakdown due to static electricity or noise voltage due to friction, etc. It is well known that it causes trouble in use. Further, in the future, as MOS-ICs become more highly integrated and have higher performance, the gate insulating film is being further thinned, and the problem is becoming serious.

FIG. 2 is an equivalent circuit diagram of an example of a conventional semiconductor protection device.

This equivalent circuit includes resistors R ₁ and R ₂ and a transistor Q ₁ (the gate is at one end of the input terminal P and the resistor R ₁ , the drain is at the other end of the resistor R ₁ and one end of the resistor R ₂ , and the source is at the ground potential). And a transistor Q ₂ (the gate and source are connected to the ground potential, and the drain is connected to the other end of the resistor R ₂ and the input gate of the transistor Q ₃ which is an internal circuit). Has been done.

The input terminal P is normally connected to an aluminum pad for bonding. The transistor Q ₃ are a transistor of the internal circuit to be protected, the gate insulating film is a silicon oxide film having a thickness of 20~30nm is used as described above.
The transistor Q ₂ is a punch-through transistor, which conducts when an abnormal voltage of around 20 V is applied between the source and drain, and has the function of clamping the input voltage. Transistor
As the gate insulating film of Q ₂ , it is usual to use the same one as the transistor Q ₃ . The transistor Q ₁ uses a thick silicon oxide film of about 600 nm with a threshold voltage of about 20 V as a gate insulating film.
It is formed at the same time as a so-called channel stopper region. The resistors R ₁ and R ₂ have a time constant to smooth the input pulse waveform,
It also has the purpose of limiting the current when the transistor Q ₁ or Q ₂ becomes conductive, and is usually formed of an impurity diffusion layer of the opposite conductivity type to the semiconductor substrate or a polycrystalline silicon layer containing impurities such as phosphorus. There are many.

FIG. 3 is a plan view of the equivalent circuit of FIG. 2 formed on a semiconductor substrate.

In the semiconductor substrate, the impurity diffusion layers 4A to 4C and 5A to 5C, which are the active regions, and the polycrystalline silicon layer 1 containing phosphorus are formed by an ordinary method.
1, contact openings 7A to 7C, a bonding pad 8 and an aluminum wiring layer 9, and a pad through hole pattern 12 for bonding are provided. Also, the resistance element
R ₁ and R ₂ are formed of impurity diffusion layers. The bonding pad 8 is made of aluminum and can be connected to a lead electrode (not shown) of the package by a passivation film (not shown) covering the entire surface of the semiconductor chip. It corresponds to the terminal P. The bonding pad 8 (input terminal P) is connected to the impurity diffusion layer 4A (corresponding to the resistor R ₁ in FIG. 3) through the contact opening 7A, and the impurity diffusion layer 103A (resistance
R ₁ ) to the drain region of transistor Q ₁ .

In addition, the impurity diffusion layer forming the source of the transistor Q ₁
5A is connected to the aluminum wiring layer 9 at ground potential through the contact opening 7B, and further reaches the drain region (not shown) of the transistor Q ₂ through the regions of the impurity diffusion layers 4B and 4C forming the resistor R ₂ . Further, a polycrystalline silicon layer 11 which is kept at the ground potential is the gate electrode of the transistor Q ₂ (not shown) is formed, whereas the region of the impurity diffusion layer 5B forming the source of the transistor Q ₂ (not shown) It is connected to the aluminum wiring layer 9 at ground potential through the contact opening 7C.

[Problems to be Solved by the Invention]

The above-described conventional input protection circuit has a drawback that it largely depends on the layout and often becomes a constraint on the layout. For example, in FIG. 3, when an abnormal voltage is applied to the bonding pad 8, before this abnormal voltage is transmitted to the protective elements such as the transistors Q ₁ and Q ₂ since this portion has no protection function. The junction of the impurity diffusion layer 4A near the contact opening 7A is broken down.
At this time, if there is a region of the impurity diffusion layer 5C having another reference potential near the contact opening 7A, an abnormal current concentrates on a very small portion (not shown) of the junction of the impurity diffusion layer 5C and Due to the contact resistance, the temperature becomes instantaneously high, and the aluminum wiring on the contact opening 7D and the silicon substrate forming the impurity diffusion layer directly below are alloyed with each other and aluminum is melted into silicon, so-called spike occurs. This causes destruction of the joint, melting of the upper aluminum, and short circuit.

In the case of a forward surge voltage for the junction of the impurity diffusion layer 4A, the junction of the impurity diffusion layer 5C is destroyed. In this case, the problem becomes more remarkable in the case of an impurity diffusion layer having a large contact resistance with only one contact opening 7D.

As described above, in the conventional input protection device, attention must be paid to the positional relationship between the input protection device attached to another input pad and the impurity diffusion layer such as the internal circuit, which is a layout restriction.

[Means for Solving the Problems]

The present invention is a semiconductor device in which an input terminal and an internal circuit are provided on a semiconductor substrate, and an input protection circuit including a resistor is provided between the input terminal and the internal circuit. The impurity diffusion layer to which the power supply potential or the ground potential is applied is formed deeper than the impurity diffusion layer provided in the protection circuit and the internal circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1 (a) and 1 (b) are a plan view and a sectional view taken along line YY of an embodiment of the present invention.

The well 2 is formed in the semiconductor substrate 1, and the field oxide film 3 is formed by the LOCOS method. Next, the impurity diffusion layers 4A to 4A
Form C, 5A-5C. Impurity diffusion layers 4A~4C is a resistor R _1, R ₂ which is connected to the input terminal. The impurity diffusion layers 5A to 5C have the same conductivity type as the well 2 and are held at the ground potential. After covering with the interlayer insulating film 6, opening the contact openings 7A to 7D, forming the aluminum bonding pad 8 and the aluminum wiring layer 9, and then covering with the wiring film 10. What is important here is that a well 2 of the same conductivity type as that of the impurity diffusion layer, for example, the impurity diffusion layer 5C, to which a power supply potential or a ground potential is applied near the input protection circuit is provided, and another impurity diffusion layer of the internal circuit is provided. To be deeper than. For example, the impurity diffusion layer 5A
If the depth of ~ 5C is 0.3μm, the depth of well 2 is 5μ
to m.

In the semiconductor device thus formed, an abnormal voltage is applied to the bonding pad 8 and the contact opening
Abnormal current concentrates at the junction of the impurity diffusion layer 5C near 7A,
Even if the junction 5C of the contact opening 7D heats up and a spike is generated, since the contact opening 7D is formed in the well layer 2 of the impurity diffusion layer deeper than the impurity diffusion layer 5C, the spike is a semiconductor. It is possible to prevent a short circuit between the impurity diffusion layer 5C having the power supply potential or the ground potential and the semiconductor substrate 1 without reaching the substrate 1.

〔The invention's effect〕

As described above, according to the present invention, the depth of the impurity diffusion layer connected to the power supply or the ground potential located in the vicinity of the input protection circuit installed in the input terminal is set to the depth of the impurity diffusion layer installed in the internal circuit. By forming deeper than
It is possible to prevent the junction breakdown due to the generation of an abnormal current in the impurity diffusion layer connected to the power supply or the ground potential near the input protection circuit due to the abnormal voltage applied to the input terminal.

[Brief description of drawings]

1 (a) and 1 (b) are a plan view and a sectional view taken along the line XX of one embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of an example of a conventional semiconductor input protection device, and FIG. It is a top view of what formed the equivalent circuit of the figure on the semiconductor substrate. 1 ... Semiconductor substrate, 2 ... Well, 3 ... Field oxide film,
4A to 4C, 5A to 5C ... Impurity diffusion layer, 6 ... Interlayer insulating film, 7A-7
D ... Contact opening, 8 ... Bonding pad, 9
... Aluminum wiring layer, 10 ... Insulating film, 11 ... Polycrystalline silicon layer, 12 ... Pad through hole, P ... Input terminal.

Claims (1)

[Claims] 1. A semiconductor device having an input terminal and an internal circuit provided on a semiconductor substrate, and an input protection circuit including a resistor provided between the input terminal and the internal circuit. The semiconductor device is characterized in that the depth of the impurity diffusion layer to which the power source potential or the ground potential is applied is formed deeper than the depth of the impurity diffusion layer provided in the protection circuit and the internal circuit.