JPH0716148B2 - Phase control device - Google Patents

Description

The present invention relates to a phase control device, and more particularly to a phase control device applicable to a waveform distortion removing device such as a waveform equalizer or a ghost canceller, a waveform distortion detecting device, and the like. Regarding

(Prior Art) Conventionally, in a method of removing a waveform distortion such as a ghost generated by a multipath of a television broadcast wave, a narrow pulse superposed in a predetermined horizontal scanning period (for example,
T pulse or 2T pulse) is used as a reference pulse, and waveform distortion such as ghost is detected with reference to the peak position and peak value of this reference pulse.

Then, this reference pulse is sliced by a comparator or the like at an appropriate amplitude level to obtain a pulse with a width as narrow as possible. Waveform distortion detection was performed.

(Problems to be solved by the invention) However, the peak value of the reference pulse does not always have a constant amplitude, and varies considerably depending on the phase distortion and proximity ghost of the circuit system, and signal setting conditions. Since the pulse width obtained by slicing with a constant amplitude level fluctuates considerably, the estimation of the peak position had to be uncertain.

In recent years, digital signal processing has come to be performed. In this case, estimating the peak position from the signal sequence obtained by discretely sampling is performed in the minimum time unit. May be predetermined,
The estimation of peak position had to be uncertain.

Thus, if the estimation of the peak position is uncertain, the waveform distortion such as ghost is measured with this as the reference position, and when the waveform distortion is to be removed by the ghost canceller or the like,
There is a problem in that the operation accuracy is poor and the waveform distortion cannot be removed sufficiently.

The present invention has been made by paying attention to the above points, and obtains the maximum value of the sample values of the sample points and the two sample values adjacent thereto, and from these, the true peak of the input signal by quadratic function approximation. The amount of deviation between the maximum value and the sample position is calculated, and the weighting coefficient of the transversal filter is controlled to correct this amount of deviation, and the output signal with the true peak value at the sample point position is matched. Therefore, it is an object of the present invention to provide a phase control device capable of improving the operation accuracy in a ghost canceller or the like.

(Means for Solving the Problems) In order to solve the above problems, the present invention samples an input signal and maximizes the sample value y ₁ among the sample values of sample points during a predetermined period.
And a maximum value detection circuit for detecting sample values y ₀ and y ₂ before and after the sample value and sample values y ₀ , y ₁ and y ₂ obtained from the maximum value detection circuit.
By a shift amount calculating circuit for calculating the shift amount between the sampling point position of y _{1 and} the position of the true peak value of the input signal by approximating the input signal by a quadratic function, and the output signal of the shift amount calculating circuit A phase control device comprising: a transversal filter for controlling a phase of an input signal to obtain an output signal in which a true peak value is matched with a sampling point position. .

(Example) FIG. 6 is a waveform diagram for explaining a method of detecting a waveform distortion such as a ghost.

As a method of detecting a waveform distortion such as a ghost in an NTSC television image signal, a reference signal as shown in FIG. 6 (A) is used, and an amplitude a ₀ of the reference signal during a predetermined period T _M ,
The amplitude a ₁ of the ghost and the delay time τ from the reference signal to the ghost are measured.

As the reference signal, a pulse having a narrow width (for example, a half value width) that is inserted in advance such as the waveform shown in FIG. 6D is used.
130-140 ns), or differentiating the leading edge portion of the vertical synchronizing signal shown in FIG.
The edge of the bar pulse shown in FIG. 6C may be differentiated and used as the reference signal.

FIG. 7 is a waveform diagram showing a sampled reference pulse.
FIG. 7 (B) shows the case where the sample point coincides with the peak position of the reference pulse, and FIGS. 7 (A) and 7 (C) show the peak position of the reference pulse at the center position between the sample points. This is the case.

7 (A) is advanced and FIG. 7 (C) is delayed with respect to FIG. 7 (B).

FIG. 1 is a block diagram showing an embodiment of the phase control device of the present invention.

In FIG. 1, the input signal from the input terminal 1 is supplied to the maximum value detection circuit 2.

The maximum value detection circuit 2 is composed of delay units 3, 4, memories 5, 6, 7 and a comparator 8.

The maximum value detection operation of the maximum value detection circuit 2 will be described below.

The reference signal having the waveform shown in FIG. 6 (A) is input from the input terminal 1 and supplied to the delay device 3. The output signal of the delay device 3 is supplied to the delay device 4.

It is the pulse shown in FIG. 6 (E) that defines the predetermined period T _M for detection in FIG. 6 (A), and defines the start time and end time of the predetermined period T _M for detection. The pulses are shown in FIGS. 6 (F) and (G), respectively.

The delay devices 3 and 4 are configured by, for example, a general-purpose latch circuit (for example, a TTL digital IC such as 74LS273) that operates at a clock frequency of 4fsc (fsc is a color subcarrier frequency), and a predetermined period T for detection is used. It is cleared by the pulse shown in FIG. 6 (F) that defines the start point of _M , and each output becomes 0.
70ns (1 / 4fsc) per clock after being set to
A delayed output is obtained.

Therefore, the delay units 3 and 4 sample the input signal at the sampling period Ts (1/4 fsc in the above case).

The input signal and the output signals of the delay units 3 and 4 are supplied to the memories 5, 6 and 7, respectively. The memories 5, 6, 7 are composed of a latch circuit like the delay units 3, 4, and when the outputs delayed by the sampling period Ts are obtained and the control signal from the comparator 8 is received. , This output value is held.

Similarly to the delay units 3 and 4, the memories 5, 6 and 7 are cleared by the pulse shown in FIG. 7 (F) so that the output becomes 0 at the start of the predetermined detection period T _M.

The comparator 8 compares the input signal to the memory 6 with the output signal of the memory 6 which is already stored and output, and when the input signal is larger than the output signal, the memories 5, 6, 7
The clock pulse is continuously supplied to and the input signals are sequentially stored and updated.

Then, when the input signal of the memory 6 becomes smaller than the output signal, the supply of the clock pulse to the memories 5, 6, 7 is stopped and the stored value at this time is held.

The outputs of the memories 5, 6 and 7 at this point are respectively
As shown in the figure, y ₀ , y ₁ , and y ₂ .

As a result, the output y ₁ of the memory 6 obtains the maximum value of the sample values of the sample points during the predetermined period T _M.

FIG. 2 is a diagram showing the relationship between each sample value and the true peak value.

In Fig. _2, the sample values at each sample point x ₀ , x ₁ , x ₂ are
_{y 0, y 1, y 2} , amount of deviation from the x ₁ to the position of the true peak value y _M is represented as x _M.

In FIG. 2A, the true peak position is on the right side of x ₁ , that is,
This is the case of the delay phase.

In FIG. 2 (B), the true peak position is on the left side of x ₁ , that is,
This is the case of the lead phase.

FIG. 2C shows the case where the true peak position coincides with x ₁ .

The outputs y ₀ , y ₁ , y ₂ of the memories 5, 6, 7 are supplied to the shift amount calculation circuit 9.

The operation of the shift amount calculation circuit 9 will be described below.

When the input signal (that is, the reference signal) is approximated by a quadratic function,
It is expressed as follows.

y = ax ² + bx + c (1) Substituting the sample values y ₀ , y ₁ , and y ₂ at each sample point x ₀ , x ₁ , and x ₂ into y ₀ = ax ₀ ² + bx ₀ + c (2) y ₁ = ax ₁ ² + bx ₁ + c (3) y ₂ = ax ₂ ² + bx ₂ + c (4) where x ₀ , x ₁ and x ₂ are three consecutive sample points, so for convenience x _{With 1} as the reference point 0, x ₀ = −1, x ₁ = 0, x ₂ = 1
In other words, equations (2) to (4) are as follows.

y ₀ = a−b + c (5) y ₁ = c (6) y ₂ = a + b + c (7) From equations (5) to (7), a and b are as follows.

a = (y ₀ + y ₂ −2y ₁ ) / 2 (8) b = (y ₂ −y ₀ ) / 2 (9) As is well known, the formula (1) is modified as follows. Therefore, the maximum value of y = a (x + b / 2a) ² + C−b ² / 4a y is when x = −b / 2a, so the deviation from x ₁ to the position of the true peak value y _M The quantity x _M is x _M = −b / 2a (10).

In FIG. 1, the arithmetic unit 10 adds the output y _{0 of the} memory 5 and the output y _{2 of the} memory 7, and outputs it by halving it.

The output (y ₀ + y ₂ ) / 2 of this arithmetic unit 10 and the output y _{1 of the} memory 6
Are respectively supplied to the arithmetic unit 11 and subjected to subtraction processing to obtain an output a. The value of the output a is shown in the equation (8).

Similarly, the arithmetic unit 12 subtracts the output y _{0 of the} memory 5 from the output y _{2 of the} memory 7 and outputs it by halving it to obtain the output b. The value of the output b is shown in the equation (9).

The outputs a and b are supplied to the arithmetic unit 13, respectively, and the (1
The output x _M shown in equation (0) is obtained.

Therefore, from the shift amount calculation circuit 9, the true peak value from x ₁
The amount of displacement x _M to the position of y _M is obtained.

It is clear from FIG. 2 that −1 / 2 ≦ x _M ≦ 1/2.

The output x _M of the arithmetic unit 13 is supplied to the memory 14. The memory 14 is supplied with a pulse defining the end point of the predetermined period T _M for detecting the waveform shown in FIG. 6 (G) to the control terminal 15, and x _M at this point is stored and output. To be done.

Since the predetermined period T _M including the reference signal is repeatedly present in every 1 field (1/60 seconds) or 1 frame (1/30 seconds), the value of x _M is updated each time. The Rukoto.

The output of the memory 14, x _M, is a weighting coefficient memory 16
Is being supplied to.

The weighting coefficient memory 16 is composed of a ROM or a RAM, and supplies an appropriate weighting coefficient to the transversal filter 17 according to the value of x _M.

The input signal to the transversal filter 17 is supplied from the input terminal 1 through the delay device 18. Delay device 18
_Has a delay time of at least the predetermined period T _M or more.

The output signal of the transversal filter 17 is output
Taken out from 19.

FIG. 3 is a diagram showing a configuration example of a transversal filter.

In FIG. 3, the tapped delay circuit 20 has a sampling period of
Unit delay circuits for each Ts are connected in series.

The weighting circuit 21 is provided with a weighting coefficient K from the weighting coefficient memory 16 at the output of each tap.

The weighted outputs are supplied to the adder 22 to obtain the added outputs.

Transfer function G (ω) of this transversal filter
Is expressed by the following equation.

FIG. 4 is a diagram showing the characteristics of the transversal filter.

FIG. 4A shows the amplitude characteristic, where the horizontal axis represents the frequency f and the vertical axis represents the amplitude characteristic A. It has flat characteristics in the video signal band of 0 to 4 MHz, and attenuates with an appropriate roll-off characteristic in the frequency band higher than that.

FIG. 4 (B) shows impulse response characteristics. The horizontal axis represents the time t, and the vertical axis represents the impulse response characteristic g (t).

The weighting of the transversal filter is set such that the impulse response is slightly shifted, and the phase can be controlled by selecting it appropriately.

FIG. 5 is a diagram showing an arrangement of peak positions of impulse response. This represents the arrangement of the peak positions of the impulse response in the case of N = 8 in the above equation G (ω) by a vertical line.

In FIG. 5, the ● mark indicates the position of the sampling point, and 17 points of phase control can be performed within the phase control range −1 / 2Ts to 1 / 2Ts, and the minimum precision is the phase control unit time ts. It is shown that.

For example, when the value of x _M , which is the output of the memory 14, is the position of 4 ts (that is, x _M = 0.25) in FIG. 5, the peak position of the impulse response set in the transversal filter is It is controlled so that it becomes −4 ts, and as a result, the peak position is located on the sample point.

Therefore, by controlling the weighting coefficient of this transversal filter, an output signal whose true peak value matches the sample point position can be obtained from the output terminal 19.

As described above, to obtain an output signal to match the true peak value to the sample point position, using the reference signal as shown in FIG. 6 (A), the amplitude of the reference signal in the predetermined time period T _M
a ₀ , the amplitude a ₁ of the ghost and the delay time τ from the reference signal to the ghost can be measured accurately, and the weighting coefficient value of the transversal filter used for the ghost canceller can be obtained to easily remove the ghost. it can.

(Effect of the Invention) The phase control device of the present invention is configured as described above, and obtains the maximum value of the sample values of the sample points and two sample values adjacent thereto, and approximates the quadratic function from them. Calculate the shift amount between the true peak value of the input signal and the sample position of the maximum value, and control the weighting coefficient of the transversal filter to correct this shift amount, and set the true peak value at the sample point position. Since the output signals in which the above are matched are obtained, the operation accuracy in the ghost canceller or the like can be improved, and there is an extremely excellent effect in practical use.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a phase control device of the present invention, and FIG. 2 is a diagram showing the relationship between each sample value and a true peak value.
FIG. 3 is a diagram showing a configuration example of a transversal filter, FIG. 4 is a diagram showing characteristics of the transversal filter, FIG. 5 is a diagram showing arrangement of peak positions of impulse responses, and FIG. 6 is a ghost etc. FIG. 7 is a waveform diagram for explaining the waveform distortion detection method of FIG. 7, and FIG. 7 is a waveform diagram showing a sampled reference pulse. 1 ... Input terminal, 2 ... Maximum value detection circuit, 3, 4, 18 ... Delay device,
5,6,7,14 ... memory, 8 ... comparator, 9 ... deviation amount calculation circuit,
10 to 13 ... arithmetic unit, 15 ... control terminal, 16 ... weighting coefficient memory, 17 ... transversal filter, 19 ... output terminal,
20 ... tapped delay circuit, 21 ... weighting circuit, 22 ... adder, a, b ... output, A ... amplitude characteristics, g (t) ... impulse response, K ... weighting factor, T _M ... predetermined period, Ts ... Sampling period, ts ... Phase control unit time, x ₀ , x ₁ , x ₂ … Sample points,
x _M ... deviation amount, y ₀ , y ₁ , y ₂ ... sample value, y _M ... true peak value.

Claims (1)

[Claims] 1. The input signal is sampled, and the maximum sampled value y ₁ and sample values before and after the sampled value of sampled points during a predetermined period are sampled.
The maximum value detection circuit for detecting y ₀ , y ₂ and the sampled values y ₀ , y ₁ , y ₂ obtained from the maximum value detection circuit are used to determine the sampling point position of y ₁ and the true peak value of the input signal. A shift amount calculation circuit that calculates a shift amount from a position by approximating an input signal by a quadratic function, and a phase of the input signal is controlled by an output signal of the shift amount calculation circuit to obtain a true peak value at a sampling point position And a transversal filter for obtaining an output signal in which the two are matched with each other.