JPH0716151B2 - Wave shaping circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform shaping circuit for converting a continuously changing input waveform into a square waveform.

2. Description of the Related Art As a conventional waveform shaping circuit, a Schmitt circuit as shown in FIG. 2 is well known. In Figure 2, 31,3
Reference numeral 2 is a transistor, and its collector is connected to the current voltage Vcc via resistors 33 and 34. Each transistor 3
The 1,32 emitters are commonly connected and grounded via a resistor 35. Transistor on the collector of transistor 31
32 bases are connected. The base of the transistor 31 is an input terminal 36 to which a signal is input, and the collector of the transistor 32 is an output terminal 37 to which a signal after waveform shaping is output.

The operation of the waveform shaping circuit shown in FIG. 2 will be described below.

When the input signal is zero, the transistor 31 is cut off,
The transistor 32 is conductive. If the resistance values of the resistors 33, 34, and 35 are R ₁ , R ₂ , and R _E , respectively, the emitter voltage V _E1
Since the emitter and collector voltages of the transistor 32 are zero and saturated, the power supply voltage Vcc is a value obtained by dividing the ratio of R ₂ and R _E.

Therefore, the input is added to the transistor 31 and the input level V ₁ is V _E1 + V _BE (V _BE is the base-emitter voltage drop)
When this happens, the transistor 31 rapidly becomes conductive due to the feedback effect of the common emitter resistor 35, the transistor 32 is cut off, and the "H" level signal is output from the output terminal 37.

Next, when the input signal level applied to the base of the transistor 31 is reduced, the input level V ₂ at which the transistor 31 is in the conductive state and the transistor 32 is in the cut-off state is obtained. When inverted, the emitter voltage V ₂ is
Is saturated and the voltage between the emitter and the collector is zero, the power supply voltage Vcc is divided by the ratio of R ₁ and R _E.

Therefore, when the input level applied to the base of transistor 31 decreases to V _E2 + V _BE , the common emitter resistance
Due to the feedback action of 35, the transistor 31 is rapidly turned off, the transistor 32 is turned on, and the "L" level signal is output from the output terminal 37.

From the above, the input signal level when a signal is applied to input terminal 36 and an "H" level signal is output from output terminal 37
V ₁ and the input signal level V ₂ when the “L” level signal is output from the output terminal 37 when the signal level applied to the input terminal 36 is reduced are expressed by equations (3) and (4), respectively. It is represented by.

Therefore, the voltage difference ΔV (hysteresis) between the input level V _{1 at} which the “H” level signal is output from the output terminal 37 and the input level V _{2 at} which the “L” level signal is output from the output terminal 37. From (3) and (4) Hysteresis ΔV is the resistance value of resistors 23 and 24 R ₁
And the value of R ₂ (R ₁ > R ₂ ) can be chosen freely.

(For example, Practical Electronic Circuit Handbook <1> CQ Publisher) Problems to be Solved by the Invention In such a conventional circuit, the hysteresis width depends on the magnitude of the power supply voltage, and the input terminal has a single input. Therefore, it is not suitable for handling a differential signal such as the output of a Hall element.

The present invention has been made in view of the above points, and an object thereof is to provide a waveform shaping circuit that converts a differential input signal into a single-ended output signal with a simple configuration.

Means for Solving the Problems In order to solve the above problems, the present invention includes a differential amplifier having a differential type input terminal, a first constant current circuit for supplying a constant current to the differential amplifier, and Second and third constant current circuits having different current magnitudes from the first constant current circuit, and a composite obtained by combining the difference between the collector output of one transistor of the differential amplifier and the output of the second constant current circuit. A flip-flop circuit to which a signal and a combined signal obtained by combining the difference between the collector output of the other transistor of the differential amplifier and the output of the third constant current circuit are input, and the output terminal of the flip-flop circuit. To obtain the output pulse.

Action The present invention has the above-mentioned configuration and includes the first constant current circuit and the second constant current circuit.
By freely selecting the ratio of each output current with the third constant current circuit, the signal applied to the differential input terminals of the differential amplifier is waveform shaped with an arbitrary hysteresis width regardless of the fluctuation of the power supply voltage. However, a stable pulse output can be obtained from the output terminal of the flip-flop circuit.

Embodiment 1 FIG. 1 is a circuit configuration diagram showing an embodiment of a waveform shaping circuit of the present invention. Hereinafter, description will be given with reference to the drawings. In FIG. 1, reference numeral 1 is a differential amplifier, which is composed of transistors 11 and 12 whose emitters are commonly connected, and the bases of the transistors 11 and 12 are connected to input terminals 8 and 9, respectively. 2 is first
In the constant current circuit, the emitter of the transistor 20 is connected to the power supply Vcc via the resistor 19, and the collector of the transistor 20 is connected to the common emitter of the transistors 11 and 12. 3 is a second constant current circuit, which is composed of a resistor 21 and a transistor 22 whose emitter is connected to the power supply Vcc through the resistor 21, and 4 is a third constant current circuit, which is a resistor 23 and an emitter It is composed of a transistor 24 connected to a power source Vcc via. The bases of the transistors 20, 22, and 24 are commonly connected to each other, and are connected to the base of the transistor 26 to which the collector and the base are connected.
The emitter of the transistor 26 is connected to the power supply voltage Vc via the resistor 25.
connected to c. That is, transistors 20, 22, 24, 26
And the resistors 19, 21, 23 and 25 form a current mirror circuit. Reference numeral 10 is a command current source of the current mirror circuit, the output of which is connected to the collector of the transistor 26. Reference numeral 5 is a first combining circuit, which is a current mirror circuit composed of a transistor 13 having a collector and a base connected to each other, and a transistor 14 having a base commonly connected to each other, and a transistor at the base.
It is composed of a transistor 17 in which the collector of 14 and the collector of transistor 22 are connected together. 6 is a second synthesis circuit, which is a current mirror circuit composed of a transistor 15 having a collector and a base connected to each other, and a transistor 16 having a base commonly connected to each other, and a transistor at the base.
It consists of a transistor 18 in which the collector of 16 and the collector of transistor 24 are connected together. A flip-flop circuit 7 is composed of NAND circuits 27 and 28 having two input terminals, and outputs of the NAND circuits 27 and 28 are connected to one input terminal of another NAND circuit. NAND circuit 27, 28
The collectors of the transistors 17 and 18 are connected to the other input terminals of the. An output terminal 29 of the waveform shaping circuit is connected to the output of the NAND circuit 27.

FIG. 3 is a signal waveform diagram for explaining the operation of the waveform shaping circuit of the present invention. In FIG. 3, (a) shows a differential input signal applied between the differential input terminals 8 and 9. (B) shows the collector current i ₁ of the transistor 11 and the collector current I ₂ of the transistor 22, and (c) shows the collector current i ₂ of the transistor 12 and the collector current I ₃ of the transistor 24. Is. Differential input terminal 8,9
When the input signal applied to is 0, the collector current I ₁ of transistor 20 is
Half flows through 11 and transistor 12. Next, as the magnitude of the input signal applied to the differential input terminals 8 and 9 increases (the potential of the input terminal 9 rises as compared to the input terminal 8), the collector current i ₁ of the transistor 11 gradually increases, The collector current i _{2 of} 12 gradually decreases. When the magnitude of the input signal applied to the input terminals 8 and 9 exceeds a certain value, the collector current I ₁ of the transistor 20 all flows to the transistor 11 and no current flows to the transistor 12. On the contrary, as the magnitude of the input signal applied to the differential input terminals 8 and 9 decreases (the potential of the input terminal 9 decreases compared to the input terminal 8), the collector current i ₁ of the transistor 11 gradually decreases, The collector current i ₂ of the transistor 11 gradually increases. When the magnitude of the input signal applied to the input terminals 8 and 9 becomes smaller than a certain value, the collector current I ₁ of the transistor 20 all flows to the transistor 12 and the current does not flow to the transistor 11. (D) shows transistor 17
It shows the collector voltage of. The bases of the transistors 17 are connected to the collectors of the transistors 22 and 14, respectively. In the collector of the transistor 14, a current obtained by converting the collector current i ₁ of the transistor 11 into a sink current by the current mirror circuit composed of the transistors 13 and 14 (whose magnitude is the same as i ₁ ) flows. 17 bases overall
I ₂ -i ₁ current flows. Therefore, I ₂ −i ₁ > 0
When I ₂ > i ₁ , the transistor 17 becomes conductive and the collector voltage of the transistor 17 becomes “L” level. Conversely, I ₂
When ≦ i ₁ , the transistor 17 is cut off and the collector voltage of the transistor 18 becomes “H” level. (E)
Shows the collector voltage of the transistor 18.
The base of the transistor 18 is connected to the collectors of the transistor 24 and the transistor 16, respectively.
The collector current of the transistor 12 is converted into the sink current of the collector current i ₂ of the transistor 12 by the current mirror circuit composed of the transistors 15 and 16 (the magnitude is the same as i ₂ ). The current I ₃ −i ₂ flows through the base of. Therefore, I ₃ −i ₂ >
When 0, that is, I ₃ > i ₂ , the transistor 18 becomes conductive, and the collector voltage of the transistor 18 becomes “L” level. On the contrary, when I ₃ ≦ i ₂ , the transistor 18 is cut off and the collector voltage of the transistor 18 becomes “H” level. (F) shows the output waveform of the output terminal 29 to which the output of the flip-flop circuit 7 is connected. The collector outputs of transistors 17 and 18 ((d) and (e) in FIG. 3) are connected to the input terminals of NAND gates 27 and 28, respectively, which form the flip-flop circuit 7. When the collector of the transistor 17 changes from "H" level to "L" level, the collector of the transistor 18 is at "H" level and the output of the NAND gate to which the collector of the transistor 17 is connected becomes "L" level. An “L” level signal is output from the terminal 29. Next, when the collector of the transistor 18 changes from the “H” level to the “L” level, the collector of the transistor 17 is at the “H” level and the transistor 18
The output of the NAND gate to which the collector of is connected becomes "H" level, the output of the NAND gate 27 is inverted from "H" level to "L" level, and the "L" level signal is output from the output terminal 29. .

The above operation will be described in more detail using mathematical expressions. Let I ₁ be the constant current supplied to the common emitter of the transistors 11 and 12 constituting the differential amplifier 1, i _{1 be} the collector current of the transistor 11, and α be the current amplification factor from the emitter to the collector of the transistor 11. , The following relational expression holds.

Where e: differential input voltage If V _T ≈ 26 mv (6) is transformed at room temperature, Becomes

When i ₁ = I ₂ , the output of the output terminal 29 is inverted from “L” level to “H” level.
If we set e ₁ , from equation (7) Is represented.

Similarly, when i ₂ = I ₃ , the output of the output terminal 29 is inverted from the “H” level to the “L” level, so if the differential input voltage at that time is e ₂ , Is represented.

Based on the above operation, if the relationship between the differential input voltage and the output voltage is illustrated, the operation characteristic of FIG. 4 is obtained. The hysteresis ΔV is calculated by e ₁ −e ₂ .

(8) As is clear from equation (9), in the embodiment shown in FIG. 1, the hysteresis ΔV is the collector current I ₁ of transistor 20, the collector current of the collector current I ₂ and the transistor 24 of the transistor 22 I Each ratio with ₃ I ₁ /
It can be freely set by selecting the values of I ₂ and I ₁ / I ₃ . That is, since the transistors 20, 22, 24, 26 and the resistors 19, 21, 23, 25 form a current mirror circuit, in the embodiment shown in FIG.
The hysteresis ΔV can be set freely by arbitrarily selecting the resistance ratio between the resistance and the resistance and the resistance ratio between the resistance 19 and the resistance 21.

As described above, according to the present invention, a differential input signal can be converted into a single-ended output signal with a simple circuit configuration. Further, the hysteresis can be arbitrarily set by freely selecting the ratio of the output currents of the first constant current circuit and the second and third constant current circuits. Moreover, since the hysteresis width is determined by the ratio of each output current of the constant current circuit, it is practically extremely useful without being affected by the fluctuation of the power supply voltage.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a waveform shaping circuit according to an embodiment of the present invention, FIG. 2 is a circuit configuration diagram of a conventional waveform shaping circuit, and FIGS. 3 and 4 are main parts of the waveform shaping circuit of the present invention. It is a signal waveform diagram and a characteristic diagram explaining operation. 1 ... Differential amplifier, 2,3,4 ... Constant current source, 5,6 ... Synthesis circuit, 7 ... Flip-flop circuit, 8,9 ... Input terminal, 2
9 …… Output terminal.

 ─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-51-53442 (JP, A) JP-A-59-79628 (JP, A) JP-A-59-147528 (JP, A) JP-A 52- 46748 (JP, A)

Claims (2)

[Claims] 1. A differential amplifier having a differential type input terminal, a first constant current circuit for supplying a constant current to the differential amplifier, and a current magnitude different from that of the first constant current circuit. The second and third constant current circuits, the first combining circuit to which the collector output of one transistor of the differential amplifier and the output of the second constant current circuit are input, and the other of the differential amplifier The flip-flop circuit includes a second combination circuit to which the collector output of the transistor and the output of the third constant current circuit are input, and a flip-flop circuit to which the outputs of the first and second combination circuits are respectively input. A waveform shaping circuit that obtains an output pulse from the output terminal of the loop circuit. 2. A first combining circuit, a first current mirror circuit having an input connected in series to the collector of one transistor of a differential amplifier, an output of the first current mirror circuit, and a second constant circuit. It is composed of a first transistor to which the difference from the output of the current circuit is combined and the combined signal is added to the base, and the second combined circuit has the input connected in series to the collector of the other transistor of the differential amplifier. A second current mirror circuit, and a second transistor to which the difference between the output of the second current mirror circuit and the output of the third constant current circuit is combined and the combined signal is added to the base.
The waveform shaping circuit according to claim 1, wherein the collector outputs of the first and second transistors are connected to a flip-flop circuit.