JPH0716180B2 - Vehicle communication device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a vehicular communication device that improves reliability of data transmission.

(Prior Art) As a conventional multiplex communication device, for example, there is one as shown in FIG. 6 (see USP4370561).

In FIG. 6, 10 is a vehicle power supply, 20 is a circuit protector, 30 is a power supply line, 40 is a multiplexing and synchronizing device, 50 is a communication line, 60 is a transmitting device, 61 to 63 are switches, 70 is a receiving device, 71 , 73 are relays, and 72, 74 are loads.

The synchronizer 40 outputs a synchronization signal as shown in FIG. 7 (a) to the communication line 50. Reference numeral 100 shown in FIG. 7 (a) is a master synchronization section, and the transmitter / receivers 60, 70 detect the transmitter / receiver channel by counting the negative pulse 101 following this (FIG. 7 (b). )). Figure 7 (a)
200 is a data transmission section following the negative pulse 101, and during this period, the output of the synchronizer 40 is in a floating state (see FIGS. 7A and 7C). When the transmission channel sequentially designated by the negative pulse 101 becomes a predetermined channel, the transmission device 60 responds to an input of a switch (for example, a switch 61) corresponding to the channel to output the transmission section.
Data is output to the communication line 50 at "H" level or "L" level during the period of 200.

On the other hand, the receiving device 70 also detects a predetermined channel similarly to the transmitting device 60, and latches the voltage level on the communication line 50 by the timing pulse 400 shown in FIG. 7 (d) during the sending period 200. Depending on the latch output, relay (eg relay 7
1) turns on and drives the load 72. After the sending section 200, the synchronizer 40 outputs the signal of the "H" level section 300 shown in FIG. 7 (a). In this way, it is possible to configure a plurality of communication channels on the communication line 50 and simultaneously perform data communication on the same line.

(Problems to be Solved by the Invention) However, in such a conventional multiplex communication device, since the output of the synchronization device is a 3-state output, the synchronization device is provided to each of the transmission device and the reception device. It is necessary to have a means for accurately determining the floating section of the output of the device, and an attached circuit for that purpose and a high-precision and expensive oscillator are required.Therefore, there is a problem that the circuit configuration becomes complicated and the cost increases. It was Also, during the output floating section of the synchronizer, that is, during the data transmission section,
When the data output of the transmitter has a slight deviation,
If the output of the synchronizer collides with the output of the transmitter, or the signal on the communication line shows a floating state of the output of the synchronizer, the signal becomes an undefined level, and a channel reading error occurs, resulting in reliable data. There was also a problem that communication was not possible and reliability was poor.

Furthermore, since the output of the transmitter is a CMOS output, only one switch can access on the same channel and data collision is not allowed. Therefore, if the control switches for the same device are located at two separate locations (for example, a radio operation switch in a vehicle), it is not possible to take the wired OR of the signals from these two locations, and There is also a problem that transmission efficiency is poor because it is necessary to prepare a channel for the switch, perform data transmission, and perform OR operation after receiving each signal on the receiving side.

(Means for Solving Problems) The present invention has been made in view of the above-mentioned conventional problems, in which each output of the synchronization device and the transmission device is an open drain output, and the synchronization device is a master synchronization device. Only the section signal is output, and the transmission device monitors the output state of the transmission data according to the level on the communication line to detect the communication channel, so that the circuit configuration is simple and the cost is low, and the reliability and transmission of data transmission are possible. An object of the present invention is to provide a highly efficient vehicle communication device.

To achieve this object, the present invention provides a single communication line for performing data communication, a synchronization device for transmitting a master synchronization signal indicating the start of communication to the communication line via an open drain transistor, and communication data. Is transmitted to the communication line through an open drain transistor until the level is determined for each bit, and communication data transmitted from the transmission device is connected to the communication line. A receiving device that drives the load by receiving each bit until a predetermined number of bits is reached.

(Operation) In the present invention having such a configuration, each transmission device is activated by the master synchronization signal of the synchronization device, and the data is transmitted by 1
The level is monitored every time a bit is transmitted, and after confirming that all transmitting devices have finished outputting one bit, the next bit is output. In this case, even if there is a time lag in data output, correction is performed for each 1-bit output, and erroneous data transmission does not occur. Further, unlike the conventional case, a circuit for accurately detecting the floating section and a highly accurate oscillator are not required, so that the circuit configuration becomes simple and the cost can be reduced. Furthermore, since wired OR can be realized efficiently, transmission efficiency can be improved.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

1 to 6 are views showing an embodiment of the present invention.

First, the configuration will be described. In FIG. 1, reference numeral 500 is a device power supply, 510 is a circuit protector, 700 is a power supply line, and 710 is a communication line.

570 is a synchronizer, and this synchronizer 570 is an oscillator 571.
And a frequency divider 572, a master synchronization signal generator 573, and an open drain transistor 574, and power is supplied from the device power supply 500 via a power supply circuit 520.

Reference numeral 580 denotes a transmitter, and the transmitter 580 is a starter circuit 58.
1, an oscillator 582, a frequency divider 583, a counter 584, a data signal generator 585, a parallel / serial converter (hereinafter referred to as P / S converter) 586, and an open drain output transistor 587. Power is supplied from the device power supply 500 via the power supply circuit 550, and a switch signal from the switch group 588 is input. Although only one transmitter 580 is shown in FIG. 1, one or more similar transmitters 580 are connected to the power supply line 700 and the communication line 710. Also, 550 shows pull-up resistance.

As shown in FIG. 2, the starting circuit 581 of the transmitter 580 includes a data end detecting circuit 5810 and an RS flip-flop 58.
11, 5814, AND circuits 5813 and 5817, a rising synchronous one-shot vibrator 5812, a cycle counter 5815, and an inverter 5816.

Here, returning to FIG. 1 again, 590 is a receiving device,
This receiver 590 is equipped with a rising one-shot vibrator 5
91, a counter 592, a falling synchronous one-shot vibrator 593, a data end circuit 594, an AND circuit 595,
598, a serial / parallel converter (hereinafter referred to as S / P converter) 596, and a latch circuit 597,
The output drives the loads 610 and 611 via the relays 600 and 601. 540 is a power supply circuit, and 560 is a pull-up resistor.

Next, the operation will be described.

First, the operation of the synchronizer 570 of FIG. 1 will be described. The synchronizer 570 outputs the output of the oscillator 571 and the output of the frequency divider 572 that divides the output of the oscillator 571 to the master synchronization signal generator 5
By synthesizing by 73, a master synchronizing pulse signal having a period T as shown in FIG. 3 (A) is generated. At this time,
The output of the synchronizer 570 is an open drain transistor 574.
Since it is transmitted to the communication line 710 via the, the output level is high impedance HZ or Low level.

Next, the operation of the starting circuit 581 of the transmitting device 580 will be described. The data end detection circuit 5810 monitors the level of the communication line 710, and when the high level time τH of the communication line 710 exceeds a predetermined time τD (τH ≧ τD) (FIG. 4 (A)), “H” level. Outputs a signal (Fig. 4 (B)) and RS flip-flop
Set the 5811 (Fig. 4 (C)). When the level of the communication line 710 becomes “L” level, the data end detection circuit
The 5810 output goes low. The output of the data end detection circuit 5810 becomes a latch signal for latching the P / S converter 586 and a reset signal for resetting the counter 584. The rising synchronization one-shot 5812 generates a pulse in synchronization with the rising of the signal (master synchronizing signal) on the communication line 710 (FIG. 4 (D)), and the RS flip-flop 58
When the output signal of the AND circuit 5813 input to the output of 11 and the output of the one-shot 5812 is at "H" level (in FIG. 4,
At time t1), the reset-priority RS flip-flop 5814 is set (FIG. 4 (E)), and the RS flip-flop 5811 is set.
Is reset. The output of the RS flip-flop 5814 becomes the “H” level after τH ≧ τD, that is, when the first rising signal (master synchronization signal) is detected after the suspension of data transmission. It means the start of data transmission. The output pulse of the one-shot 5812 is a cycle counter 5815 that measures the cycle of 1-bit data.
It becomes a reset signal for resetting.

The output of the cycle counter 5815 is input to one of the AND circuits 5817 via the inverter 5816, and the other is input as the input.
Since the output of the RS flip-flop 5814 is given,
Output of AND circuit 5817 (START / STOP for oscillator 582
Signal) becomes "H" level at time t1, as shown in FIG. At this time, the oscillator 582 starts oscillation and transmits data.

When the frequency counter 5815 counts the output pulse of the oscillator 582 and detects the data 1 bit time tB (FIG. 4 (A)), that is, when the output of the data 1 bit ends, the output is set to the “H” level. To do.

At this time, the output of the AND circuit 5817 becomes "L" level,
The oscillator 582 is suspended. Then, when the level of the communication line 710 rises, the one-shot multivibrator 5812 outputs a pulse signal, so the period counter 5815 is reset again, and the output of the AND circuit 5817 becomes the “H” level,
The oscillator 582 starts oscillating again and transmits the next bit data.

In the same manner, the counter 58 is sent out bit by bit, and when the output of the predetermined number of bits is completed, the counter 58 at the time tn in FIG.
The output of 4 resets the RS flip-flop 5814 and returns to the initial state.

Next, the operation of the transmission device 580 will be described. In FIG. 3, Tx-1 is the first transmitting device and Tx-2 is the second transmitting device.

As described above, the starting circuit 581 causes the high level time τH of the communication line 710 to exceed the predetermined time τD (τH ≧ τ).
D), the input signal from the switch group 588 is taken into the P / S converter 586 and latched, and at the same time, the counter 584 is reset. Further, the starting circuit 581 monitors the level of the signal line 710 and rises the master synchronization signal (FIG. 4, time t0 to t1) output from the synchronizer 570 (FIG. 4, time t).
1) Start the oscillator 587 and start sending data.

The transmitted data has a waveform as shown in FIGS. 5A and 5B corresponding to the input data latched in the P / S converter 586 and communicates via the open drain transistor 587. Output on line 710.

The P / S converter 586 operates as a shift register after the input data is latched, and shifts the latched data bit by bit to the right in FIG. 1 at a timing described later.

The data signal generator 585 synthesizes the output of the oscillator 582 and the output of the frequency divider 583 on the basis of the value of the data shifted by the P / S converter 586, and the above-mentioned FIG. 5 (a), (b). Generates a signal in the inverted form of the waveform signal shown in FIG.

The signal generated by the data signal generator 585 is transmitted onto the communication line 710 by the output transistor 587 and becomes the waveform signal shown in FIGS. 5 (a) and 5 (b).

The starting circuit 581 measures the 1-bit length tB of the data shown in FIGS. 5A and 5B from the output of the oscillator 582,
When the output of one bit of data is completed, the oscillator 582 is suspended.

Next, as shown in FIGS. 3B and 3C, at time t1 to t2, the transmitting device Tx-1 has data "1" and transmitting device Tx-2.
When the data "0" is output, the wired OR of both outputs is taken on the communication line 710, and the data "0" appears as shown in FIG. 3 (D).

The P / S converter 586 of each transmitter (Tx-1), (Tx-2) is
The falling edge of the output signal of the data signal generator 585 (ie,
The latch data is shifted by the rising edge of the signal shown in FIGS. 5A and 5B, and the next output value is output to the data signal generator.
Give to 585.

The start-up circuit 581 continues to monitor the level of the communication line 710, and when detecting that the level has become “H” level, the oscillator 571 is started again, and the data signal generator 585 outputs the data signal of the next bit. Occur.

In this way, each transmission device (Tx-1), (Tx-2) stops the temporary transmission output every time it sends out 1 bit of data, and monitors the level of the communication line where the wired OR of each output is taken. Then, after confirming that all the transmitting devices have finished outputting 1 bit, the next bit is output. Therefore, there are variations in the frequencies of the oscillators of the transmitters (Tx-1) and (Tx-2). For example, as shown in FIGS. Even if a shift occurs, the shift is corrected for each 1-bit output, and even if the number of transmission bits increases, the timing shift does not cause erroneous transmission of transmission, and each transmitter (Tx-
The wired OR signal of each output of 1) and (Tx-2) can be generated.

The counter 584 counts the number of pulses output from the data signal generator 585, and when detecting that the output of a predetermined number of bits is completed, stops the starting circuit 581 and ends the data transmission.

After that, the transmitters (Tx-1) and (Tx-2) are the synchronizers 570.
In response to the master synchronization signal from the output of, the above operation is repeated.

Next, the operation of receiving apparatus 590 will be described. The receiver 590 is
It is connected to the communication line 710 via a pull-up resistor 560. The output of the rising synchronous one-shot vibrator 591 and the first output of the counter 592 are both AND circuits.
Entered in 98. Here, the counter 592 counts the rising edges of the pulses on the communication line 710, and outputs the first “H” level signal until a predetermined number of pulses described later are input. Therefore, the output of the AND circuit 598 is a pulse (reception clock) having a width τR, as shown in FIG.
And given to the S / P converter 596. S / P converter 596
Operates as a shift register, for example, and circuit 59
The shift operation is performed at the falling edge of the output of 8 and the level of the communication line 710 is read. At this time, if the signal of the communication line 710 is a pulse of data “0” (width tB0 <τR), the S / P converter 596
Is read as "L" level, and if the pulse of data "1" (width tB1> τR) is read as "H" level. Here, if the data to be transmitted and received is (n-1) bits, the counter 592 receives the (n-1) th bit at time tn-1 in FIG. 3 and outputs the first output as "L". "Set to level and stop receiving clock supply to S / P converter 596. The second output of the counter 592 is the time t
When the count value becomes n at n, it becomes "H" level, and this output is input to one side of the AND circuit 595.

On the other hand, the data end detection circuit 594 monitors the level of the communication line 710, and outputs the “H” level when the “H” level time τH becomes τH ≧ τD with respect to the predetermined time τD, and this output Is input to the other of the AND circuit 595. At this time,
The output of the AND circuit 595 becomes "H" level as shown in FIG. 3 (F) and is given to the output latch circuit 597 as a latch signal, and the output of the S / P converter 596 is the output latch circuit.
Latched in 597. In this way, the load drive relay 600,6
01 operates by the output of the output latch circuit 597, and the load 61
Drive 0,611. At this time, if the number of rising edges of the signal on the communication line 710 is not equal to the number of bits n, the counter
The output of 592 becomes the "L" level, the latch signal is not generated, and it is determined that communication transmission error has occurred, and the communication data at that time is discarded. Data end detection circuit 594
Then, the output of is reset by the master synchronizing signal appearing on the communication line 710 and becomes the “L” level. The falling synchronization one-shot vibrator 593 generates a pulse signal when the output of the data end detection circuit 594 falls and resets the counter 592. After that, the receiving device 590 repeats the same receiving operation.

As described above, in this embodiment, the synchronizing device 570 only generates the master synchronizing signal, and the circuit for accurately discriminating the floating section and the high-precision and expensive oscillator as in the conventional art are not required. The circuit configuration can be simplified and the cost can be reduced. In addition, since the data does not reach an indefinite level and the time shift of the data can be corrected, the channel can be correctly detected, and reliable and reliable data transmission can be performed. In addition, the wired OR of the outputs of multiple transmitters
Since the operation of taking can be efficiently realized, the transmission efficiency can be improved.

(Effects of the Invention) As described above, according to the present invention, the outputs of the synchronizer and the transmitter are open drain outputs, and the synchronizer directs only the master synchronization section. Since the output state of the transmission data is monitored by the level of the communication line to detect the communication channel, the oscillator provided in the synchronizer and the transmitter may be of low accuracy and low cost, and the circuit that detects the floating section may be used. Since it is not required, the device can be simplified and the cost can be reduced.

In addition, it is possible to correct the time lag of communication data and prevent the occurrence of an undefined level of data.
Reliable and reliable data transmission can be performed.
Further, the operation of taking the wired OR of the outputs of the plurality of transmitters can be realized efficiently and simply, and the transmission efficiency can be improved.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of its starting circuit, FIG. 3 is a timing chart for explaining the overall operation, and FIG. 4 is an operation of the starting circuit. 5 (a) and 5 (b) are diagrams showing data output waveforms, FIG. 6 is a circuit block diagram showing a conventional example, and FIG. 7 is its timing chart. 570 ... Synchronizer, 574,587 ... Open drain transistor, 580 ... Transmitter, 590 ... Receiver, 710 ... Communication line.

Claims (1)

[Claims] 1. A communication line for performing data communication, a synchronization device for sending a master synchronization signal indicating the start of communication to the communication line through an open drain transistor, and communication data level for each bit. And a transmission device that sends the data to the communication line through an open drain transistor until the number of bits reaches a predetermined number, and communication data that is connected to the communication line and is transmitted from the transmission device has a predetermined number of bits for each bit. And a receiving device for driving the load, the receiving device until receiving the signal.