JPH0716266B2 - Centralized wiring equipment for automobiles - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated wiring system for an automobile, and more particularly, a central processing unit calculates control data for controlling a plurality of loads connected to a plurality of terminal processing units, and the terminal processing units are operated. The present invention relates to an integrated wiring system for an automobile, in which the load is controlled by communicating with the integrated wiring via the integrated wiring.

[0002]

2. Description of the Related Art Conventionally, as shown in JP-A-55-105490, data for controlling a load by a central processing unit is calculated each time based on various signals sent from a terminal processing unit. Then, the calculation result is sent as control data to the load via a predetermined terminal processing device to control the load.

[0003]

SUMMARY OF THE INVENTION In the above conventional configuration,
The processing time of the central processing unit becomes long, and a control delay occurs when controlling many loads in the automobile.

In view of this point, an object of the present invention is to shorten the arithmetic processing time of the central processing unit so that a delay in controlling the load does not occur.

[0005]

[Means for Solving the Problems] The above object is to store control data for load control in a table, and a central processing unit obtains the load control data by a table search according to a signal received from a terminal. It is achieved by configuring as follows.

[0006]

According to the present invention thus constructed, for example,
Switch ON when the central processing unit receives from the terminal processing unit
Which load and which load is to be operated are calculated by searching the contents stored in the table, so that the calculation time is considerably shortened and the control response becomes good.

[0007]

EXAMPLES Hereinafter, an integrated wiring device according to the present invention will be described.
This will be described in detail with reference to the illustrated embodiment.

FIG. 1 is a physical wiring diagram showing an embodiment of an integrated wiring system according to the present invention mounted on an actual vehicle. Central control unit 1 (hereinafter referred to as CCU1) and terminal control unit (hereinafter referred to as L
11 to 17 are connected by an optical fiber 2, and the CCU 1 inputs the states of switches and the like connected to the LCUs 11 to 17 and creates control data for the LCUs 11 to 17. Send and control the load. The room lamp 95 is connected to the LCU 15, and the door switches 91 and 92 are connected to the LCUs 15 and 13, respectively. The key switch 93 is connected to the LCU 13, the rear differential Otsuga switch 94 is connected to the LCU 14, and the rear differential Otsuga 96 is connected to the LCU 17. CCU1 is LCU1
When the door switch 92 is ON from 3 or the door switch 91 is ON from LCU 15, LC is received.
Data for turning on the room lamp 95 is transmitted to U15. In the case of the rear differential otsuga, the accessory switches (hereinafter referred to as ACC) of the key switch 93 and the ignition switch (hereinafter referred to as IGN) are turned on from the LCUs 13 and 14, and the rear differential otsuga switch 94 is turned on.
Only when it is received, the data for operating the rear differential otsuga is transmitted to the LCU 17. In the current automobile, the rear differential otsuga can be operated if the key switch IGN is ON, but if the integrated wiring system is used, the ACC, IGN and the rear differential otsuga switch AN can be used.
Since D can be easily obtained, useless power consumption at the time of engine start can be prevented, and the starter or the like can be swiftly turned. Note that FIG. 2 shows a part of the wiring by the conventional wire harness for reference.

FIG. 3 is a block diagram showing an embodiment of the structure of the CCU and LCU. Since the CCU requires a high degree of judgment processing ability, it has a microcomputer 5. A signal transmission control circuit (hereinafter referred to as CIM) 6 converts parallel control data generated by a microcomputer into serial control data and transmits the serial control data. Further, it has a function of performing serial / parallel conversion on received data and outputting an interrupt request to the microcomputer 5 when data having no error is received. Which L is CCU
Multiplexer 8 for selecting whether to transmit with CU,
It is composed of photoelectric converters 21 to 23 for converting light / electricity and a memory device 9 for storing received data and transmitted data.

On the other hand, the LCU is a photoelectric converter 24, CIM.
7, an input / output interface 4, an A / D converter 3, etc., and is connected to the analog sensors 121 to 122 and the digital input / output 111 to 112.

FIG. 4 is a block diagram showing the CIM circuit configuration, which is an important component in the integrated wiring system. The CIM can be roughly classified into a control unit and an interface unit. The control unit uses a synchronizing circuit 61 for synchronizing the clock with the data received on the line 68, the shift operation control of the shift register using this clock, the interrupt relation control (when used in the CCU), and the data transmission error control. It comprises a control circuit 62 for carrying out the above, and an address comparator 63 for comparing the address given from the line 67 with the address indicating the destination included in the received data.
The interface unit includes a shift register 64 that performs serial / parallel conversion and a serial input / output A / D converter 3
The input / output buffer 66 is connected to the input / output interface 4 by changing the input / output direction by the address input of the A / D converter control circuit 65 and the line 67. When the data is received from the line 68, the shift register 64 converts the data into parallel data. A transmission error is checked during reception, and when reception is completed, the address input from the line 67 is compared with the address in the received data. If both are normal, the received data is transferred to the input / output buffer 66. Then, the output part of the external digital input / output 113 to 115 is controlled. On the other hand, during data transmission, the data in the A / D converter control circuit 65 and the data in the input / output buffer 66 are transferred to the shift register 64.
Is transmitted to the CCU from the line 69 by the shift clock generated by the control circuit 62. Although FIG. 4 shows the CIM used in the LCU for handling analog data, the CIM is the line 67.
Depending on the address given from, it can be used as a CIM that handles only digital input / output in the LCU and as a CIM that interfaces with a microcomputer in the CCU.

FIG. 5 shows the CIM when used in the LCU.
3 is a state transition diagram of FIG. When reset, it goes into an idle state and waits for data reception. When the start bit at the beginning of the data is received, the reception state is entered, and the presence or absence of a transmission error and the address are checked while receiving the data. If there is an error, it returns to idle and waits for the next data. If there is no error, the process shifts to zero transmission, and "0", which is the number of bits required to detect a transmission error, is transmitted. The transmission data is transmitted in the next transmission state, the idle state is returned, and one transmission is completed.

FIG. 6 shows the CIM when used in the CCU.
3 is a state transition diagram of FIG. First, it is reset and is in an idle state. Here, when the microcomputer writes data to the shift register 64 in the CIM, transmission is started. It transits from idle to zero transmission and transmission, transmits data, returns to idle, and waits for reception of reply data to the transmitted data. When the reply data is received, it shifts to the receiving state. If there is a transmission error, it returns to idle. In the CIM in the CCU, the received data is a reply to the transmitted data, so no address check is performed. When the error-free data is received, the interrupt request flag for the microcomputer is set, the idle state is returned to, and one transmission is completed. The interrupt request can be masked by software.

FIG. 7 is a flow chart of a control method in an integrated wiring system having such a CCU and LCU and having a star network structure as shown in FIG. In the main routine, first, the memory and the timer are initialized and the transmission is activated, that is, the data is transmitted to the first CIM. After the transmission is started, the transmission table that stores the transmission data is repeatedly updated. Processing of received data with respect to transmitted data is performed by an IRQ routine. Control is transferred to the IRQ routine by the interrupt request flag output when the CIM receives data. The IRQ routine fetches the received data, stores it in the receiving table, sends the data to the next CIM,
Return from the Q routine to the main routine. If the data is transmitted normally, the integrated wiring system will function only with the main routine and the IRQ routine. However, if there is an error in the transmitted or received data for some reason, the transmission will stop and the transmission will stop. It will not be restarted. A timer interrupt routine is provided to prevent this. This takes advantage of the fact that the CIM in the LCU has a fixed time from receiving to transmitting data, so a timer longer than that time is set, and the time from the CCU transmitting is set. If it matches the set time, the timer interrupt routine is executed.
When the data cannot be continuously received twice from the above, a process of operating a buzzer or a lamp as an alarm and a process of transmitting the data to the next CIM and continuing the transmission are performed.

FIG. 8 shows an embodiment of a table CCTBL which stores the connection relation between the input and the output used in the process of updating the transmission table in the main routine of FIG. 3 bytes are allocated to indicate one connection relationship. The first byte contains the order in which the CIM to which the input device is connected is transmitted. In the second byte, C is the order at which the output device is transmitted.
It contains the order of whether it is connected to IM. In addition, information indicating whether the input is an AND-related input or an OR-related input is entered in bits 7 and 6 of the second byte. The 3rd byte has the upper 4 bits, which is the number of the input device connected to the input / output terminal of the CIM, and the lower 4 bits, which is the number of the output device connected to the input / output terminal of the CIM. ing. For example,

[0016]

[Outer 1]

The switch connected to the input / output terminal 9 of the CIM transmitted first is the C transmitted fifth.
It shows that the device connected to the input / output terminal 3 of the IM is operated. Also,

[0018]

[Outside 2]

Indicates that the output device connected to the input / output terminal 3 of the CIM to be transmitted third does not operate unless the AND condition of a plurality of inputs is satisfied, and is transmitted first. The input connected to the input / output terminal 6 of the CIM is one of them.

FIG. 9 is a flowchart of a routine for updating the transmission table using the table having the configuration shown in FIG. The simplest way to update the transmission table is to check the input status in order, and if it is "1", set the corresponding output to "1", and if it is "0", set it to "0". Is. However, when there are many input-output connection relationships, a problem occurs in terms of response time. Therefore, in the routine of FIG. 9, when the integrated wiring system targets the general wiring system, the input is often kept in the previous state, and it rarely changes. If there is a change, the state of the corresponding output is inverted. First, the reception table containing the latest data is compared with the transmission table containing the previous input state to check if there is any change in the input. If there is no change, the pointer of the reception table is advanced by 1 and the process is terminated. When there is a change, in order to check the presence or absence of the next change, the changed input bit of the transmission table is inverted so as to match the reception table. Next, the connection relation for the changed input is searched from CCTBL, and OR
Check the bit and AND bit, and if they are "1",
Perform each processing. If it is “0”, CCTB is now
Based on the connection data found from L, the output bit of the transmission data is inverted. Since the connection relation of the output to the changed input is not limited to one, the connection relation is searched again from the CCTBL and the same processing is performed. CCTBL
When there is no connection data for the changed input, the pointer in the reception table is advanced by 1 and the processing is terminated.

FIG. 10 shows a method of processing the OR relation input. For this processing, ORTBL is used which is a table that collects only the connection relationships in which the OR bit is "1" in CCTBL. The structure of ORTBL is shown in FIG.
In the configuration of CCTBL, the OR bit and the AND bit are the same as "0". Focusing on the output corresponding to the changed input, the connection data related to the output is searched from ORTBL, the input state indicated by the connection data is checked, and if it is "1", the bit corresponding to the output device of the transmission table is "1". And finish. If it is "0", the next connection data is searched from ORTBL and the same processing is performed. When the connection data for the output cannot be found from the ORTBL, the bit corresponding to the output device in the transmission table is set to "0" and the process ends.

FIG. 11 is a flowchart of a routine for processing an AND-related input. This is the OR of FIG.
"1" and "0" in the processing routine for inputting the relationship
It is almost the same as the one that replaced, but paying attention to the output destination of the connection data (in CCTBL) corresponding to the changed input,
An input having an AND relationship is searched for from NDTBL, and it is checked whether the value is "0". 1
If any one is "0", "0" is written in the transmission table, and "1" is written in the transmission table only when all inputs are "1".

[0023]

According to the integrated wiring system of the present invention, since the load control data is obtained by the search using the table, the calculation is very fast, and the control data can be saved in the table when the difference in the control data is caused by the change of the model. There is an effect that it can be easily dealt with by simply changing.

[Brief description of drawings]

FIG. 1 is a substantive diagram when an integrated wiring system of the present invention is installed in an actual vehicle.

FIG. 2 is an explanatory diagram showing a configuration example of wiring by a conventional wire harness.

FIG. 3 is a block diagram showing a configuration example of an integrated wiring system.

FIG. 4 is a circuit configuration diagram of a CIM.

FIG. 5 is a state transition diagram of CIM.

FIG. 6 is a state transition diagram of CIM.

FIG. 7 is a flowchart for explaining the operation.

FIG. 8 is an explanatory diagram showing the structure of a CCTBL table.

FIG. 9 is a flowchart for explaining the operation.

FIG. 10 is a flowchart for explaining the operation.

FIG. 11 is a flowchart for explaining the operation.

[Explanation of symbols]

1 ... CCU, 2 ... optical fiber, 3 ... A / D converter, 4 ...
Input / output interface, 5 ... Microcomputer,
6, 7 ... CIM, 8 ... Multiplexer, 9 ... Memory device, 21-24 ... Photoelectric conversion device, 61 ... Synchronous circuit, 62
... control circuit, 63 ... address comparator, 64 ... shift register, 65 ... A / D converter control circuit, 66 ... input / output buffer.

Claims (3)

[Claims] 1. A signal processing apparatus is configured to be capable of bidirectionally transmitting and receiving a signal between a plurality of terminal processing devices and at least one central processing device via integrated wiring, and the central processing device is connected to the terminal processing device. In a configuration in which control data for controlling the load is calculated and the same load is controlled by communication with the terminal processing device, the central processing unit stores a table storing the data for controlling the load. An integrated wiring device for an automobile, comprising: the control data is obtained from this table by a table search. 2. The integrated wiring device for an automobile according to claim 1, wherein the table stores data indicating a control state of a load as control data. 3. The integrated wiring device for an automobile according to claim 2, wherein the table stores output destination data indicating which load is controlled for an input as control data.