JPH071854B2 - Non-linear companding circuit - Google Patents
Non-linear companding circuitInfo
- Publication number
- JPH071854B2 JPH071854B2 JP8089086A JP8089086A JPH071854B2 JP H071854 B2 JPH071854 B2 JP H071854B2 JP 8089086 A JP8089086 A JP 8089086A JP 8089086 A JP8089086 A JP 8089086A JP H071854 B2 JPH071854 B2 JP H071854B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- limit
- input
- output
- ratio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Picture Signal Circuits (AREA)
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は非線形圧伸回路、即ち入力レベルに応じて出力
レベルの圧縮率又は伸長率が非線形に変化する回路に関
する。The present invention relates to a non-linear companding circuit, that is, a circuit in which a compression rate or an expansion rate of an output level changes non-linearly according to an input level.
同一の振巾リミット特性を持つ複数のリミット回路にレ
ベルの異なる入力信号を与えて、リミット点(折点)が
異なる複数の信号を形成し、これらを所定の極性及び比
率で加算して、非線形入出力特性を得たものである。Input signals with different levels to multiple limit circuits that have the same amplitude limit characteristics to form multiple signals with different limit points (break points), and add them at a specified polarity and ratio to obtain a nonlinear I / O characteristics are obtained.
この種の非線形圧伸回路は従来ではダイオードを用いた
折線近似回路や対数増幅回路で構成していた。これらの
回路ではダイオード又はトランジスタのPN接合による非
線形特性を利用しているので、本質的に温度特性が悪
く、またPN接合の容量によって高域特性が悪い。またカ
ーブの形状が固定であり、任意の関数(次数)を選らべ
ず、微小レベル、双方向信号を扱うことができない欠点
もある。This type of non-linear companding circuit has conventionally been composed of a broken line approximation circuit using a diode and a logarithmic amplification circuit. Since these circuits use the non-linear characteristics of the PN junction of the diode or transistor, the temperature characteristics are essentially poor, and the high frequency characteristics are poor due to the capacitance of the PN junction. There is also a drawback that the shape of the curve is fixed, an arbitrary function (order) cannot be selected, and minute levels and bidirectional signals cannot be handled.
本発明はこれらの問題を解消することを目的とする。The present invention aims to solve these problems.
本発明の非線形圧伸回路は、入力レベルを複数に分圧す
る分圧回路3と、各分圧出力に対してほぼ同一の振巾リ
ミット特性でリミットをかける複数個のリミット回路
(実施例の差動アンプ4a〜4c)と、各リミット回路の出
力を所定の極性及び比率で加算する加算回路とを具備し
ている。The non-linear companding circuit according to the present invention includes a voltage dividing circuit 3 for dividing an input level into a plurality of parts and a plurality of limit circuits for limiting each divided output with substantially the same amplitude limit characteristic (the difference between the embodiments. Dynamic amplifiers 4a to 4c) and an adder circuit for adding the outputs of the limit circuits with a predetermined polarity and ratio.
分圧比、加算比率によって任意の伸長又は圧縮特性が得
られる。ダイオードを用いないので、温度特性、周波数
特性が良く、広帯域の非線形処理回路に適す。小入力レ
ベルで動作し、双方向入力(AC)でも動作する。Arbitrary expansion or compression characteristics can be obtained by the division ratio and the addition ratio. Since it does not use a diode, it has good temperature and frequency characteristics and is suitable for a wide-band nonlinear processing circuit. It operates at a small input level and also works with bidirectional input (AC).
第1図は本発明による非線形圧伸回路の伸長回路の実施
例を示す。入力信号源1の出力(例えば帯域10MHzのビ
デオ信号)は平衡出力を発生するアンプ2に供給され、
互に逆極性のアンプ出力は更に分圧回路3にてレベル調
整された複数(この例では3つ)の信号に分圧される。
3つの分圧出力は夫々差動アンプ4a〜4cに与えられ、差
動アンプに固有のリミット特性で振巾リミットを受け
る。差動アンプ4a〜4cは±4KT/q(K:ボルツマン定数、
T:絶対温度、q:電子の電荷)の差動入力以上では飽和す
る。FIG. 1 shows an embodiment of a decompression circuit of a non-linear companding circuit according to the present invention. The output of the input signal source 1 (for example, a video signal having a bandwidth of 10 MHz) is supplied to an amplifier 2 that produces a balanced output,
The amplifier outputs having opposite polarities are further divided into a plurality of (three in this example) signals whose levels have been adjusted by the voltage dividing circuit 3.
The three voltage-divided outputs are given to the differential amplifiers 4a to 4c, respectively, and are subjected to the swing limit by the limit characteristic peculiar to the differential amplifier. The differential amplifiers 4a to 4c have ± 4 KT / q (K: Boltzmann constant,
It saturates above the differential input of (T: absolute temperature, q: electron charge).
第2図a〜cは差動アンプ4a〜4cの入出力特性で、aは
差動アンプ4aの入力が分圧回路3では分圧されていない
ので、差動アンプ4aの本来のリミット特性を示す。b及
びcは、差動アンプ4b、4cの入力が夫々分圧回路3の抵
抗R1〜R3によって分圧されているので、aの特性よりも
リミットが生ずる入力レベルが上昇する。即ち、リミッ
トが生じる入力電圧はvc>vb>vaとなる。2A to 2C show the input / output characteristics of the differential amplifiers 4a to 4c. In FIG. 2A, since the input of the differential amplifier 4a is not divided by the voltage dividing circuit 3, the original limit characteristics of the differential amplifier 4a are shown. Show. In b and c, the inputs of the differential amplifiers 4b and 4c are divided by the resistors R1 to R3 of the voltage dividing circuit 3, so that the input level at which the limit occurs is higher than the characteristic of a. That is, the input voltage limit occurs a v c> v b> v a .
差動アンプ4a〜4cの出力a〜cを抵抗R4〜R6で重み付け
して、帰還抵抗R7を持つ差動アンプ5で加算すると、第
3図のような伸長特性(小レベルほどゲイン大)を有す
る出力が得られる。加算比率は、分圧比の逆数であって
よい。なお入力がAC信号であれば、第3図のように対称
形の双方向出力特性となる。When the outputs a to c of the differential amplifiers 4a to 4c are weighted by the resistors R4 to R6 and added by the differential amplifier 5 having the feedback resistor R7, the extension characteristic (the smaller the level is, the larger the gain) is as shown in FIG. Output is obtained. The addition ratio may be the reciprocal of the voltage division ratio. If the input is an AC signal, symmetrical bidirectional output characteristics are obtained as shown in FIG.
第4図は圧縮回路の実施例で、第1図とほぼ同様に、ア
ンプ2、分圧回路3、リミット用差動アンプ4a、4b、加
算用抵抗R3〜R5及び差動アンプ5から成っている。この
例では、アンプ2から得られる逆極性の入力信号aに、
差動アンプ4a、4bで振巾リミットを受けた正極性の信号
b、cを所定の比率で加えて、a−b−cの減算により
第5図のような圧縮特性(小レベルほとゲイン小)を得
ている。FIG. 4 shows an embodiment of a compression circuit, which comprises an amplifier 2, a voltage dividing circuit 3, limiting differential amplifiers 4a and 4b, adding resistors R3 to R5, and a differential amplifier 5 in the same manner as in FIG. There is. In this example, for the input signal a of the opposite polarity obtained from the amplifier 2,
The positive polarity signals b and c, which have been subjected to the swing limit by the differential amplifiers 4a and 4b, are added at a predetermined ratio, and by subtracting ab-c, the compression characteristic (small level and gain) as shown in FIG. Got a small).
第6図は伸長回路の具体例を示す。第7図の入出力特性
グラフに示すような折線近似特性を得る場合、各折点
A、B、Cの電圧を40mV(1)、160mV(4)、320mV
(8)とする。即ち、入力40mVで差動アンプ4aが飽和
し、160mVで差動アンプ4bが、更に320mVで差動アンプ4c
が夫々飽和するように分圧比を定める。分圧回路3の抵
抗R3を30Ωにすると、 各差動アンプ4a、4b、4cの出力a〜cを0.125(1/8)、
0.125(1/4)、1.0(1)の比率で加えれば、第7図の
太線で示す伸長特性が得られる。即ち、一番感度の低い
差動アンプ4cの出力cを基準(リニア特性)にして他の
出力b、aに倍率を掛けて加算する。FIG. 6 shows a concrete example of the expansion circuit. When the broken line approximation characteristics shown in the input / output characteristic graph of FIG. 7 are obtained, the voltages at the respective break points A, B and C are 40 mV (1), 160 mV (4) and 320 mV.
(8). That is, the differential amplifier 4a saturates at 40 mV input, the differential amplifier 4b at 160 mV, and the differential amplifier 4c at 320 mV.
The partial pressure ratio is determined so that each of them is saturated. If the resistance R3 of the voltage dividing circuit 3 is set to 30Ω, Output a to c of each differential amplifier 4a, 4b, 4c is 0.125 (1/8),
If the ratios of 0.125 (1/4) and 1.0 (1) are added, the elongation characteristics shown by the bold line in FIG. 7 can be obtained. That is, the output c of the differential amplifier 4c having the lowest sensitivity is used as a reference (linear characteristic), and the other outputs b and a are multiplied and added.
加算比率は第6図に示すようにR−2Rの抵抗ラダー回路
6によって設定されている。各差動アンプ4a〜4cが飽和
した状態では、ほぼ等しい電流がラダー回路6から各差
動アンプ4a〜4cの出力に向って流入する。まず入力が40
mVで差動アンプ4aが飽和し、このアンプ4aの電流は1/8
の比率でラダー回路6の出力Dに電圧信号として表れ
る。同様に160mV入力で差動アンプ4bが飽和すると1/4の
比率の電圧が出力点Dに加算され、最後に320mV入力で
差動アンプ4cが飽和すると1の比率の電圧が出力点Dに
加算される。The addition ratio is set by the resistance ladder circuit 6 of R-2R as shown in FIG. When the differential amplifiers 4a to 4c are saturated, substantially equal currents flow from the ladder circuit 6 toward the outputs of the differential amplifiers 4a to 4c. First input is 40
The differential amplifier 4a saturates at mV and the current of this amplifier 4a is 1/8.
The voltage signal appears at the output D of the ladder circuit 6 at a ratio of. Similarly, when the differential amplifier 4b is saturated with 160 mV input, the voltage of 1/4 ratio is added to the output point D, and when the differential amplifier 4c is saturated with 320 mV input, the voltage of 1 ratio is added to the output point D. To be done.
ラダー回路の出力はエミッタホロワ・アンプ7を介して
取出される。The output of the ladder circuit is taken out via the emitter follower amplifier 7.
第8図は圧縮回路の具体例で、第6図の伸長回路の逆特
性を持つ。第4図の抵抗R3に対応するのが、分圧回路3
の同一点を入力とし、出力を共通接続した一対の差動ア
ンプ4c、4dである。これらの差動アンプ4c、4dの出力
に、差動アンプ4a、4bの逆相出力、をラダー回路6
で加算(結果的には減算)する。FIG. 8 shows a concrete example of the compression circuit, which has the reverse characteristics of the decompression circuit of FIG. The voltage dividing circuit 3 corresponds to the resistor R3 in FIG.
Is a pair of differential amplifiers 4c and 4d in which the same point is input and the outputs are commonly connected. The ladder circuit 6 is provided with the outputs of the differential amplifiers 4c and 4d and the negative phase outputs of the differential amplifiers 4a and 4b.
To add (resultingly subtract).
第7図の逆特性を得るために、分圧回路3によって160m
V、120mV及び40mVの各入力電圧で折点が生じるように分
圧比を定める。分圧抵抗R1、R2、R3を計算すると、R1=
62Ω、R2=120Ω、R3=62Ωとなる。In order to obtain the reverse characteristics of FIG.
Set the voltage division ratio so that a break occurs at each input voltage of V, 120 mV, and 40 mV. Calculating the voltage dividing resistors R1, R2, and R3, R1 =
62Ω, R2 = 120Ω, R3 = 62Ω.
ラダー回路6の出力Dから見て差動アンプ4aの出力の
重みは1/4で、差動アンプ4bの出力bの重みは1/2であ
る。2個の差動アンプ4c、4dの出力は、電流加算により
比率が2であるので、 の比率で各信号c、−b、−aの加算が行われる。When viewed from the output D of the ladder circuit 6, the weight of the output of the differential amplifier 4a is 1/4 and the weight of the output b of the differential amplifier 4b is 1/2. Since the ratio of the outputs of the two differential amplifiers 4c and 4d is 2 due to the current addition, The signals c, -b, and -a are added at the ratio of.
〔発明の効果〕 本発明は上述の如く、同一特性のリミット回路にレベル
の異なる入力信号を与えて、入力に対しリミット点が異
なる複数の信号を得て、これらの所定の極性及び比率で
加算して非線形出力を得るようにしたので、分圧比、加
算比を変えることにより任意の伸長又は圧縮カーブを得
ることができる。またダイオードを用いずに折線近似を
行えるので、温度特性、周波数特性が極めて良好であ
り、広帯域微小信号を処理することができる。また双方
向(入力極性が正負)の対称特性が容易に得られる。[Effects of the Invention] As described above, the present invention provides input signals having different levels to limit circuits having the same characteristics, obtains a plurality of signals having different limit points with respect to the inputs, and adds the signals at predetermined polarities and ratios. Since a non-linear output is obtained by changing the voltage division ratio and the addition ratio, an arbitrary expansion or compression curve can be obtained. Further, since the broken line approximation can be performed without using a diode, the temperature characteristic and the frequency characteristic are extremely good, and a wide band minute signal can be processed. Further, bidirectional (input polarity is positive / negative) symmetric characteristics can be easily obtained.
第1図は本発明の一実施例を示す伸長回路の回路図、第
2図は差動アンプの入力レベルとリミット点の関係を示
すリミット特性図、第3図は伸長特性図、第4図は圧縮
回路の回路図、第5図は圧縮特性図、第6図は伸長回路
の具体例を示す回路図、第7図は折点設定のための伸長
特性図、第8図は圧縮回路の具体例を示すグラフであ
る。 なお、図面に用いた符号において、 1……信号源 2……アンプ 3……分圧回路 4a〜4c……差動アンプ 6……ラダー回路FIG. 1 is a circuit diagram of an expansion circuit showing an embodiment of the present invention, FIG. 2 is a limit characteristic diagram showing a relationship between an input level of a differential amplifier and a limit point, FIG. 3 is an extension characteristic diagram and FIG. Is a circuit diagram of the compression circuit, FIG. 5 is a compression characteristic diagram, FIG. 6 is a circuit diagram showing a concrete example of the decompression circuit, FIG. 7 is a decompression characteristic diagram for setting a break point, and FIG. It is a graph which shows a specific example. In the reference numerals used in the drawings, 1 ... Signal source 2 ... Amplifier 3 ... Voltage dividing circuit 4a to 4c ... Differential amplifier 6 ... Ladder circuit
Claims (1)
各分圧出力に対してほぼ同一の振巾リミット特性でリミ
ットをかける複数個のリミット回路と、各リミット回路
の出力を所定の極性及び比率で加算する加算回路とを具
備する非線形圧伸回路。1. A voltage divider circuit for dividing an input level into a plurality of voltages,
A non-linear companding circuit comprising: a plurality of limit circuits that limit each divided output with substantially the same amplitude limit characteristic; and an adder circuit that adds the outputs of each limit circuit with a predetermined polarity and ratio.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8089086A JPH071854B2 (en) | 1986-04-08 | 1986-04-08 | Non-linear companding circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8089086A JPH071854B2 (en) | 1986-04-08 | 1986-04-08 | Non-linear companding circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62236202A JPS62236202A (en) | 1987-10-16 |
| JPH071854B2 true JPH071854B2 (en) | 1995-01-11 |
Family
ID=13730947
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8089086A Expired - Fee Related JPH071854B2 (en) | 1986-04-08 | 1986-04-08 | Non-linear companding circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH071854B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0437263A (en) * | 1990-05-31 | 1992-02-07 | Matsushita Electric Ind Co Ltd | Gradation correction device |
| JPH05268498A (en) * | 1992-03-24 | 1993-10-15 | Keitaro Sekine | Picture signal amplifier |
-
1986
- 1986-04-08 JP JP8089086A patent/JPH071854B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62236202A (en) | 1987-10-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0505751B1 (en) | Logarithmic amplification circuit | |
| US3921091A (en) | Amplifier circuit | |
| JP2000504900A (en) | Temperature compensated logarithmic detector | |
| JPH0452645B2 (en) | ||
| JPH0738554B2 (en) | Logarithmic amplifier | |
| JPS5820482B2 (en) | amplifier | |
| US3868574A (en) | Arrangement for the transmission of information signals by pulse code modulation | |
| JPH071854B2 (en) | Non-linear companding circuit | |
| US3300631A (en) | Analog multiplier | |
| JPH0547868B2 (en) | ||
| US4385364A (en) | Electronic gain control circuit | |
| US4093876A (en) | Baseline restorer circuit | |
| JP2690599B2 (en) | Variable gain amplifier | |
| JP2719251B2 (en) | Noise attenuation circuit with main signal path and auxiliary signal path with high-pass filter characteristics | |
| US6198333B1 (en) | Analog multiplier with thermally compensated gain | |
| EP0178936B1 (en) | Variable emphasis circuit | |
| JPH05160657A (en) | Signal converter | |
| JP2573279B2 (en) | Current conversion circuit | |
| JP3367875B2 (en) | Logarithmic conversion circuit and transconductor using the same | |
| JPH031845B2 (en) | ||
| JPH037161B2 (en) | ||
| JPH0637449Y2 (en) | Reference voltage generator | |
| JPS59127412A (en) | Logarithmic compressing and amplifying circuit | |
| JPS5840846B2 (en) | AGC amplifier circuit | |
| JPS61253915A (en) | Electronic volume circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |