JPH0719125B2 - Encryption circuit and decryption circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an encryption circuit and a decryption circuit for an encryption synchronization signal of digital data.

(Prior Art and Its Problems) Cryptography is used for concealing digital data, but when using cryptography, it is necessary to establish cryptographic synchronization between transmission and reception.

Depending on the quality of the line, this cipher synchronization may be out of sync during reception, and if it is misaligned, the cipher cannot be decrypted and data cannot be reproduced.

FIG. 4 is a block diagram of a conventional encrypted data transmission system, and FIG. 5 is a block diagram of a reception system. In these figures, 1 is an exclusive OR (), 20 is a random number generator (PN
(1)), 21 is a switch (SW), 22 is a cipher start position signal generator (SYN), and 23 is a cipher start position signal detector (DET).

In the transmission system shown in FIG. 4, the encryption start position signal is output from SYN22 via SW21 by a control signal prior to communication,
After that, the input data and the output of the random number generator 20 are added with a random number by 1 (encrypted), and the encrypted output is transmitted.

On the other hand, in the receiving system of FIG. 5, the encrypted output of FIG. 4 is input, the encryption start position signal is detected by the detector 23, the random number is generated by the random number generator 20, and the encrypted input is input. By adding a random number of 1 to the data, the encrypted input data is decrypted and output data is obtained.

As described above, conventionally, only the cryptographic synchronization is established prior to the communication. Therefore, if the synchronization is deviated during the communication due to a disturbance or the like, the subsequent data cannot be translated and the information is lost. These pieces of loss information are retransmitted by re-encrypting the same data with a different random number by a notification from the receiving side to the transmitting side. The disadvantage of this method is that since the same data is encrypted using different random numbers, it gives information about the encryption method and the method of generating the random numbers to a third party, which reduces the strength of the encryption. is there.

(Object of the Invention) An object of the present invention is to solve the above-mentioned problems, and to decrypt a re-pullable encrypted sync signal that can be immediately re-synced even if a synchronization shift occurs due to a disturbance or the like during communication. It is to provide an encryption circuit and an encryption circuit.

(Structure and Operation of the Invention) The decryption circuit and the encryption circuit for the re-pullable cipher sync signal according to the present invention use the centralized sync signal and the interlaced sync signal together with the input data, and these sync signals are used for encryption. Each of them is used as a start position signal and a synchronization monitor, and if the clock synchronization that is synchronized between transmission and reception is used to check the synchronization monitor after communication is started and the cryptographic synchronization is deviated due to disturbance, etc. The main feature is that the synchronization pull-in is performed.

The present invention will be described in detail below with reference to the drawings.

1 and 2 are block diagrams showing a configuration example of the present invention. FIG. 1 shows a transmission system encryption circuit, and FIG. 2 shows a reception system decryption circuit.

In the encryption circuit of FIG. 1, 1 is an exclusive OR (),
2 and 4 are random number generators (PN (p)) and (PN (q)) of different types used for encryption, and 3 is a switch (SW) that switches the outputs of the two random number generators. ). Reference numeral 5 is a clock circuit (TIM) which is composed of an oscillator and a counter and serves as a clock. Reference numeral 6 is an encryption start position signal generator (SYN), which is transmitted prior to communication and is used for centralized synchronization. Reference numeral 7 denotes a switch (SW) for transmitting the output of the start position signal generator 6 and subsequently transmitting the encrypted data output of exclusive OR 1.

In the decoding circuit of FIG. 2, 13 is a bit pattern matching circuit (DET (s)), and 5 is a clock circuit (TIM) for time adjustment having a period equal to TIM5 of FIG. Two
Reference numerals 4 and 4 are the same as 2 and 4 shown in FIG. Reference numeral 1 is an exclusive OR (), and 15 is a bit pattern matching circuit (DET (M)). 14 is a phase control circuit (CNT).

(Explanation of Action) FIG. 3 is a time chart showing signals of respective parts of the configuration example of the present invention shown in FIG. 1 and FIG.

In FIG. 3, (1) is the input data of FIG.
[A _i , a _{i + 1} , a _{i + 2} ...] is data, and b is a fixed pattern inserted periodically or at a fixed time for interlaced synchronization, and normally uses a PN sequence.

[P _i , p _{i + 1} , p _{i + 2} ...] In (2) represents a random number sequence generated in PN (p) 2. Also, [q _i , q _{i + 1} , q _{i + 2} ...] of (3) is
It is a random number sequence generated by PN (q) 4, and different random numbers are used for (2) and (3). These random number outputs are periodically or regularly switched by SW3 controlled by TIM5 to obtain an output (4).

The encryption start position signal (SYN) used for centralized synchronization
Is output from the cipher start position signal generator 6 controlled by TIM5 through SW7 prior to communication.

The input data (1) is exclusive-ORed with (4), and at the same time, the cipher start position signal SYN is added to the head and sent as the encoded output (5). In the time chart, represents exclusive OR.

Reception processing in the circuit configuration of FIG. 2 is performed as follows. First, when (5) 'is input, the leading SYN is detected by DET (s), TIM5 is activated as a result, and TIM5 of FIG. 1 is timed. Next, this output also activates the random number generators PN (p) and PN (q), [p _i ,
p _{i + 1} , p _{i + 2} ...] And [q _i , q _{i + 1} , q _{i + 2} ...].
The output (6) of PN (p), that is, [p _i , p _{i + 1} , p _{i + 2} ...] is cryptographically added to the input (5) ', and the output is [a _i , a _{i + 1} ...]. Obtain the data (8).

Also in this case, the input (5) 'of the received sequence is always cryptographically added with the output (7) of PN (q), that is, [q _i , q _{i + 1} , q _{i + 2} ], and the result is DET (M ) 15, the b pattern (9) is detected by pattern matching. If the insertion position of this b pattern (9) is at the time specified by TIM5, PN
The generation of (p) is continued as it is and the phase control circuit 14 does not perform the phase control.

Next, the operation in the case where the encrypted output (5) from the transmission system is deviated due to disturbance such as at time 13 of the input (5) 'is shown below. Input (5) 'and output of PN (q) (7) [q _i , q _{i + 1} ,
q _{i + 2} ...] Is generated under the control of TIM5 and is always exclusive-ORed with the input (5) 'to constantly monitor whether or not the result is b as a synchronous monitor.

Now, [bq _{i + 1} ] of the input (5) 'is performed at the positions of the times 13 and 14, and when the result b is detected, the pattern of [q _{i + 1} ] is started from the time 15 in a one-to-one manner. Corresponding (6) [p
_{i + 2} ] is generated from PN (p) 2, the phase control circuit 1
Use 4 to control the phase. As a result, p _{i + 1} (time 8 ~ ₁ ) of (6)
(Between 3) and the result of cryptographic addition of input (5) '(8) [a'
_{i + 1} ] is obtained, but the result is that the phase relationship between [p _{i + 1} ] in (2) and [p _{i + 1} ] in (6) is different,
[A ' _{i + 1} ] becomes incorrect data (shown by hatching). If [p _{i + 2} , p _{i + 3} ...] Is generated in this state and cryptographically added to the input (5) ′, erroneous data is continuously restored. Therefore, in the configuration according to the present invention, time 1
3, b is detected, and as a result, the output (9) controls the phase control circuit 14 to control the phase of the generation sequence of PN (p) and generate [p _{i + 2} ] synchronized with the input (5) '. Therefore, the subsequent data immediately returns to normal.

(Effect) According to the present invention, if synchronization is lost due to disturbance or the like during reception of an encrypted signal, resynchronization can be immediately performed, and normal data can be continuously received. Further, since the fixed pattern is encrypted by using the clock circuit for the transmission system and the reception system, it becomes difficult for the third party to recognize the synchronization pattern, and the random number generator having different properties is used for the data and the fixed pattern. Therefore, the effect that the decryption by the third party is difficult, etc. is remarkable.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an encryption circuit according to the present invention, FIG. 2 is a block diagram showing an embodiment of a decryption circuit according to the present invention, and FIG. 3 is a circuit diagram of the circuit shown in FIGS. FIG. 4 is a block diagram of a conventional encryption circuit, and FIG. 5 is a block diagram of a conventional decryption circuit. 1… exclusive OR, 2,4,20… random number generator (PN
()), 3,7,21 ... Switch (SW), 5 ... Watch circuit (TI
M), 6,22 ... Encryption start position signal generator (SYN), 13,15,23
… Detector (DET).

Claims (2)

[Claims] 1. A clock circuit for generating and outputting a synchronization clock and a clock circuit for generating and outputting a synchronization clock for concealing and transmitting input data in which interlaced synchronization signals having a fixed pattern are inserted into digital data at predetermined intervals. A first random number generator for generating a random number for encrypting the digital data; and a random number different in kind from the first random number generator for encrypting the interlaced sync signal according to the synchronization clock. Switching between a second random number generator, an output of the first random number generator and an output of the second random number generator so as to encrypt the digital data and the interlaced sync signal according to the synchronization clock, respectively. And a first switch that outputs the input data and an exclusive OR with the input data as one input and the output of the switch as the other input. An exclusive OR circuit for outputting encrypted data, an encryption start position signal generator for generating an encryption start position signal according to the synchronization clock, and an encryption start position signal generator for starting encryption before communication. A second switch for transmitting a position signal and subsequently transmitting the encrypted data from the exclusive OR circuit. 2. Encrypted data in which digital data and an interlaced synchronization signal of a fixed pattern inserted into the digital data at a predetermined interval are encrypted with different random numbers in accordance with a synchronization clock after the encryption start position signal. And a first bit pattern matching circuit that detects the encryption start position signal, and is activated when the encryption start position signal is detected by the first bit pattern matching circuit. A clock circuit that outputs equal clocks; a first random number generator that is activated by the output of the clock circuit and that generates and outputs a random number for decoding the encrypted digital data according to the clock of the output; The received encrypted data is used as one input, and the output of the first random number generator is used as the other input to perform exclusive OR operation and decrypt the data. A first exclusive-OR circuit for obtaining force data, and a second exclusive-OR circuit that is activated by the output of the clock circuit and generates and outputs a random number for decoding the encrypted interlaced synchronization signal in accordance with the clock of the output. A random number generator and a second exclusive logic which receives the encrypted encrypted data as one input and an output of the second random number generator as the other input to obtain an exclusive OR to obtain a decrypted output. A second circuit for collating and monitoring the bit pattern of the output of the summing circuit and the second exclusive OR circuit, and outputting a signal indicating a match when the bit pattern matches the predetermined fixed pattern of the interlaced sync signal. The first random number generator when the time at which a signal indicating that a fixed pattern is matched is input from the bit pattern matching circuit and the second bit pattern matching circuit is off the predetermined interval Decoding circuit, characterized in that a phase control circuit for providing a phase control signal for controlling the phase to generate a random number following the interlaced synchronizing signal of the fixed pattern with respect.