JPH0719213B2 - Online test method for disperser - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an online test system for devices that are distributed and connected to a bidirectional common bus.

(Prior Art) Conventionally, a plurality of control devices are connected to a bidirectional common bus,
In a system in which data is transmitted and received between control devices, when testing the data transmission / reception function to the bidirectional common bus of one or more control devices among a plurality of control devices, the bidirectional common bus is preliminarily set in the control device. A test circuit for loopback was prepared in front of, and at the time of the test, the control device was disconnected from the online system, and the loopback test was performed offline to test the data transmission / reception function to the bidirectional common bus.

(Problems to be Solved by the Invention) However, the above-mentioned conventional techniques have the drawbacks that the control device to be tested must be disconnected from the online system and that signals cannot be routed to the bidirectional common bus.

Further, in a device in which the bidirectional common bus is duplicated, it is common that a plurality of control devices connected to the bidirectional common bus are also duplicated. The transmission / reception function of data to / from the bidirectional bus of the control device was tested by taking off some of the control devices connected to the system and one of the buses of the system. In this case as well, there is a drawback that one side of the control device and the bidirectional common bus to be tested must be offline.

The present invention aims to overcome the above drawbacks of the prior art.

(Means for Solving Problems) A feature of the present invention for achieving the above object is that a plurality of control devices are connected to a bidirectional common bus, and data is transmitted between the control devices via the bidirectional common bus. In a distributed device online test method for transmitting and receiving, in the bidirectional common bus, a test device for testing the function of the control device, and a common basic clock is distributed to each control device and the test device via a clock bus, In addition, each control device has a monitoring device for monitoring the entire control device, and each control device is synchronized with the test device at a predetermined different time slot within a fixed cycle, and for testing via the bidirectional common bus. It has a test circuit unit that receives, stores, and transmits data.The test device creates test data and sends it to each control device, and the test circuit unit in each control device receives, stores, and sends the test data that has been sent. , The output data of the control device mounted / unmounted table and the test data in the test device are comprehensively tested to determine the specific time slots prepared for each control device and allocated to each control device. This is an online test method for distributed devices that tests transmission / reception functions between each control device and the bidirectional common bus at fixed intervals.

(Operation) A specific time slot is used between the test device and the control device, and the transmission / reception function of the control device is tested simultaneously with the operation of other time slots. Therefore, the online test can be performed without disconnecting the control device.

(Embodiment) FIG. 1 shows an embodiment of the present invention. Reference numeral 1 is a bidirectional common bus, and 2, 3, 4 are control devices connected to the bidirectional common bus, and a maximum of N (N is an integer) control devices are connected. Reference numeral 5 is a test device, 6 is a monitoring device for monitoring the entire control device and distributing the basic clock, and 7 is a bus for the basic clock distributed from the monitoring device. Test data is transmitted and received between the control device (2, 3, 4) and the test device 5 via the bidirectional common bus 1.

FIG. 2 shows a test circuit portion of the control device, 10 is a control device, 11 is a basic clock bus, 12 is a primary counter, and 13 is 2
Next counter, 14 is bidirectional common bus, 15 is device number,
16 is a secondary counter output, 17 is a matching circuit, 18 is an input instruction signal, 19 is a general data input instruction signal, 20 is an input gate, 21
Is an internal test gate, 22 is an internal test register, 23 is an output instruction signal, 24 is an output data gate, 25 is a general data output gate, 26 is an output gate, 27 is a general data output instruction signal, and 28 is an input instruction signal. A logical sum signal of 18 and the output instruction signal 23, and 29 is general data.

The controller 10 receives the basic clock from the basic clock bus 11 and creates a primary counter 12 and a secondary counter 13. The primary counter 12 is the primary barrier for data and the secondary counter 13
Is a counter having a value equal to the maximum number of control devices connected to the bidirectional common bus 14, and 1 of the secondary counter 13
The time slot is a basic time slot in which data is transmitted and received once on the bidirectional common bus 14. In the present embodiment, the primary counter 12 is set to 480 and the secondary counter 13 is set to 64. The primary counter 12 is made to count up every time the secondary counter 13 counts 64, and to return to 0 after 479.

The controller 10 is used for general data transmission / reception when the primary counter 12 counts 0 to 477, and counts 478,479.
Is used for testing. Further, the control devices 10 are given device numbers 15 which do not overlap among the control devices 10, and the device number 15 is assigned any one of the values counted by the secondary counter 13.

The secondary counter output 16 of the control device 10 is compared with the device number 15 by the coincidence circuit 17, and when they have the same value, the output of the coincidence circuit 17 is output. This output is the counter value 478 of the primary counter 12,
When it is ANDed with 479 and when the count is ANDed with 478, the data from the bidirectional common bus 14 is controlled by the controller.
The input instruction signal 18 to be input to 10 is issued. The input instruction signal 18 is logically ORed with the data input instruction signal 19 in general, the gate of the input gate 20 of the bidirectional common bus 14 is opened, and the data is input to the internal test register 22 through the internal test gate 21. Input to the terminal. The data is set in the internal test register 22 by the basic clock.

When the logical product of the output of the coincidence circuit 17 and the count value 479 of the primary counter 12 is obtained, the output instruction signal 23 for outputting the data of the internal test register 22 to the bidirectional common bus 14 is issued.
The output instruction signal 23 opens the output data gate 24 of the internal test register 22, and the output data is the general data output gate 25.
The data output of the above is logically ORed and becomes the data input of the output gate 26 of the bidirectional common bus 14. The gate of the output gate 26 is opened by the logical sum of the output instruction signal 23 and the general data output instruction signal 27, and data is output to the bidirectional common bus 14.

In the general data output gate 25, when the logical sum signal 28 of the input instruction signal 18 and the output instruction signal 23 is taken, the output of the output gate 25 is suppressed, and the general data 29 is not output to the bidirectional data bus 14. .

FIG. 3 mainly shows an internal circuit of the test apparatus. 40 is a test apparatus, 41 is a monitoring apparatus, 42 is a basic clock, 43 is a primary counter, 44 is a secondary counter, 45 is a transmission gate, and 46 is a bidirectional. Common bus, 47 is test data, 48 is comparison data, 49 is receive gate, 50 is mounted / unmounted table, 51 is mounted / unmounted output data, 52 is test gate, 53 is matching circuit, 54 is error information. is there. Here, the bidirectional common bus 14 in FIG. 2 is the same bidirectional common bus as 46 in FIG. The test apparatus 40 receives the basic clock 42 from the monitoring apparatus 41, receives the primary counter 43,
Create a secondary counter 44.

The basic clock 42, the primary counter 43, and the secondary counter 44 operate in synchronization with the basic clock of the control device 10, the primary counter 12, and the secondary counter 13, respectively. Therefore, 1 of the control device 10
When the counter value of the next counter 12 is 0 and the counter value of the secondary counter 13 is 0, the counter value of the primary counter 43 of the test apparatus 40 is 0, and the counter value of the secondary counter 44 is 0. When the counter value 478 of the primary counter 43 of the test apparatus 40 is the value 478, the transmission gate 45 is validated and the test data 47 is output to the bidirectional common bus 46. The test data 47 includes the secondary counter outputs ⁰ to 63 of the secondary counter 44 (6 bits of 20 to ²⁵ ), the ground signal (2 bits of 2 ⁶ and 2 ⁷ ) and the parity bit (1 bit of 2 ⁸ ). ) Of 9 bits. Further, 8 bits excluding the parity bit from the test data 47 are separately input to the reception matching circuit 53 as the comparison data 48.

When the counter value of the primary counter 43 is 479, the receiving gate 49 of the bidirectional common bus 46 is opened, data is input from the bidirectional common bus 46, and the counter output value of the secondary counter 44 is sequentially sent to the monitoring device 41. send. The monitoring device 41 has a mounted / unmounted table 50 of the control device 10, and is mounted / unmounted during mounting.
Enable output data 51 of unimplemented table and receive gate
The reception data input through 49 is input to the matching circuit 53 through the test data 52. The coincidence circuit 53 compares the data input through the test gate 52 with the comparison data 48, and when they do not coincide, transmits error information 54 to the monitoring device 41. The monitoring device 41 can know from which control device 10 the data is defective by the error information 54 and the value of the secondary counter 44.

(Effects of the Invention) As described above, the present invention provides a test device dedicated to a test on a bidirectional common bus, and synchronizes the test device with each of a plurality of control devices connected to the bidirectional common bus. The addition of the test circuit unit for transmitting and receiving data to and from the bidirectional common bus has an advantage that each control device can be tested in an online state. Therefore, the control device that intermittently transmits / receives data to / from the bidirectional common bus or the control device that cannot confirm the normality of data transmission / reception by the standby standby is the bidirectional on the standby standby side of the duplexed bidirectional common bus. It is possible to quickly and online detect an abnormality in the data transmission / reception portion of the control device having the common bus and interface.

[Brief description of drawings]

1 is a schematic block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing a test circuit portion of a control device connected to a bidirectional common bus, and FIG. 3 is an internal schematic diagram of the test device. 1; bidirectional common bus, 2, 3, 4; control device, 5; test device, 6; monitoring device, 7; basic clock bus.

Front page continued (72) Inventor Hideyuki Matsubara 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Yoichi Kasai 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. In-house (72) Inventor Toshiharu Ueda 1-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) In-house Tomiji Koike 2-3-2 Nishishinjuku, Shinjuku-ku, Tokyo International Telegraph and Telephone Corporation (72) Inventor Hiroshi Suzuki, 2-3-2 Nishishinjuku, Shinjuku-ku, Tokyo International Telegraph and Telephone Corporation (56) Reference JP-A-56-19248 (JP, A) JP-A-58-154950 (JP , A) JP 59-229958 (JP, A)

Claims (1)

[Claims] 1. An online test system for a distributed device, wherein a plurality of control devices are connected to a bidirectional common bus, and data is transmitted and received between the control devices via the bidirectional common bus. A test device for testing the function of the control device, and a monitoring device for distributing a common basic clock to each control device and the test device via a clock bus and for monitoring the entire control device. Each of the control devices has a test circuit unit that receives, stores, and transmits test data via the bidirectional common bus in synchronization with the test device at different predetermined time slots within a certain period. The test device creates test data and transmits the test data to each control device, and the test data received by the test circuit unit in each control device, transmitted after being accumulated, and the mounted / unmounted test data of the control device. By comprehensively testing the output data of the cable and the test data in the test device, by utilizing the specific time slots prepared for each control device and assigned to each control device, An online test method for distributed devices, which tests the transmission / reception function with the bidirectional common bus at fixed intervals.