JPH071921B2 - Odd / even field discriminating device - Google Patents

Description

The present invention relates to an odd / even field discriminating apparatus for television signals.

[Outline of Invention]

The present invention, triggered by each pulse of the composite sync signal,
From a circuit that generates a pulse train with an intermediate pulse width between 2 and 1H, in each vicinity of the front and rear edges of the vertical sync signal, obtain a pulse base of a predetermined interval with a different length from other parts, and obtain this pulse. By detecting the length and interval of the base, it is possible to quickly determine whether the field is odd or even without error.

[Conventional technology]

The current television standard system performs 2: 1 interlaced scanning, and the relationship between the horizontal synchronizing frequency f _H and the vertical synchronizing frequency f _V is f _H =
(N + 1/2) since the a f _V, the phase relationship between the horizontal and vertical synchronizing signals are different between the odd and even fields. Therefore, in the current direction, as shown in FIG. 3, three horizontal scanning periods (3
In H), an equalization pulse with a half cycle of the horizontal sync signal is inserted so that the vertical sync timing does not change between odd and even fields during vertical sync separation by the integrating circuit.

By the way, when editing a video tape, etc., a television signal is often processed in frame units, and it is necessary to determine whether the field is odd or even.
An odd / even field discriminating device as shown in FIG. 4 was used.

In FIG. 4, the composite sync signal from the input terminal IN is supplied to the vertical sync separation circuit (11), and its metastable time τ ₁ is H / 2 <τ via the first inverter (12). ₁
It is supplied to a first monostable multivibrator (hereinafter abbreviated as MMV) (13) such that <1H. This MMV
The output of (13) is supplied to the second MMV (14) whose metastable time τ ₂ is such that 1H <τ ₂ <3H / 2, and through the second inverter (15), It is supplied to the counter (16) as a clock. The output of the second MMV (14) is commonly supplied to the start terminal of the counter (16) and the set terminal of the flip-flop (18) via the third inverter (17). The output of the counter (16) is commonly supplied to its stop terminal and the reset terminal of the flip-flop (18). The output of the flip-flop (18) and the output of the vertical synchronization separation circuit (11) are supplied to the AND gate (19), and the output of the AND gate (19) is led to the output terminal OUT.

Next, the operation of the odd / even field discriminating apparatus in FIG. 4 will be described with reference to FIG.

When transitioning from the even field to the odd field, the equalizing pulse, the vertical synchronizing pulse, and the equalizing pulse and the following composite synchronizing signal are supplied to the input terminal IN from the 525th line having a length of 1H as shown in FIG. 5A. Vertical sync separation circuit (1
In 1), the vertical synchronizing signal as shown in FIG. 5B is extracted from this composite synchronizing signal.

The first MMV (13) to which the composite synchronizing signal is supplied via the inverter (12) has a metastable time (pulse width) τ ₁ set to, for example, 3H / 4, as shown in FIG. 5C. In the first
Triggered on the falling edge of the 525 line horizontal sync pulse,
The output will be in a "Hi" metastable state (hereinafter called the trigger state), and after 3H / 4 hours, the output will be "Lo".
Return to the stable state of.

The MMV (13) which has been triggered by the falling edge of the first equalizing pulse of the composite sync signal returns to the stable state after the arrival of the second equalizing pulse, as shown in FIG. Similarly, the trigger state of MMV (13) by the third equalizing pulse is inverted after the arrival of the fourth equalizing pulse. The pulse-based time length of this section is H / 4. 5
The MMV (1
3) shows that when the stable state is restored after the arrival of the sixth equalization pulse, the stable state is maintained until the falling edge of the first vertical sync pulse of the composite sync signal, and the pulse base is approximately 3H.
/ 4 hours.

On the other hand, the second MMV (13) output is supplied as described above.
MMV (14) has a metastable time (pulse width) τ ₂ of 5
It is set to H / 4 and is triggered every 1H at the same timing as the falling edges of the horizontal sync pulse before the 525th line and the first and third equalization pulses, so it is shown in Fig. 5D. Thus, the metastable state is maintained.

When 5H / 4 has passed from the arrival of the fifth equalizing pulse, it is within the first vertical synchronizing pulse period of the composite synchronizing signal, and the MMV (13) becomes stable as shown in FIG. 5C. Therefore, as shown in D of the same figure, the MMV (14) also inverts from the dogger state to the stable state. The falling edge of the output of the MMV (14) is inverted by the inverter (17) and supplied to the counter (16) as a start pulse and to the flip-flop (18) as a set pulse. As a result, the counter (16) starts the counting operation, and the flip-flop (18) is set as shown in FIG. 5F.

As shown in FIG. 5C, the MMV (13) becomes a trigger state when the first vertical sync pulse of the composite sync signal falls, and stabilizes within the third vertical sync pulse period after 3H / 4 hours have elapsed. Return to the state. Similarly, the trigger state of MMV (13) due to the trailing edge of the third vertical synchronizing pulse is inverted within the fifth vertical synchronizing pulse period. MMV (13) which became the trigger state by the falling edge of the fifth vertical sync pulse
Returns to the stable state after the arrival of the sixth vertical synchronizing pulse and the seventh equalizing pulse immediately thereafter.

MMV triggered by vertical sync pulse, as described above
The falling edge of the output of (13) is supplied to the counter (16) as a clock through the inverter (15). As described above, this counter (16) starts operating by the output of the second MMV (14) in the first vertical synchronizing pulse period, and as shown in FIG.
The individual clocks are counted and an output pulse is generated. The output pulse of the counter (16) stops the counting operation of the counter (16) itself and also resets the flip-flop (18) as shown in FIG. 5F. The output of the counter (16) becomes "Lo" at the 4th clock.

As a result, the output of the flip-flop (18) becomes "Hi" during a period substantially overlapping with the six vertical synchronizing pulses, and the AND gate (19) opens, and the vertical synchronizing separation circuit (11) shown in FIG. ) Is output to the output terminal OUT as an odd field discrimination output.

Note that, as shown in FIG. 5C, the output of the first MMV (13) becomes 3H / 4 hours “Lo” in the tenth line, which is the same as in the first vertical synchronizing pulse period described above. Two
The output of the MMV (14) becomes "Lo", the output of the flip-flop (18) becomes "Hi", and the AND gate (1
9) opens. However, as shown in FIG. 7A, there is no vertical sync pulse to be separated by the vertical sync separation circuit (11) within a period of about 3H from this point. Therefore, during this period, the discrimination output is not derived at the output terminal OUT.

When transitioning from the odd field to the even field, the last 263rd line of the odd field is as short as H / 2 time as shown in FIG. 3B, and therefore the timing at which the first MMV (13) is triggered. However, there is a delay of H / 2 from the case of transition from the even field to the odd field. And MMV (1
3) is sequentially triggered by the 2nd, 4th and 6th equalization pulses, the stable period of the MMV (13) in the 1st vertical sync pulse period is shortened to approximately H / 4, and the 2nd
The MMV (14) cannot be in a stable state and is maintained in a metastable state. Therefore, the counter (16) is in the stopped state, the flip-flop (18) is maintained in the reset state which continues from the odd field, and the field discrimination output is not derived to the output terminal OUT.

[Problems to be solved by the invention]

In the conventional odd / even field discrimination device shown in FIG. 4,
When the second MMV (14) becomes stable and the vertical sync pulse exists immediately after that, it is possible to determine whether the field is odd or even. Therefore, when noise is mixed in the composite sync signal, There was a risk of malfunction.

For example, if the horizontal sync pulse is lost due to video tape dropout or the like, the MMV (14) becomes stable.
Immediately after that, if the level of the input terminal IN becomes “Hi” for several H periods intermittently due to dropout or the like, the field discrimination output is output regardless of odd / even even in the middle part of the field. Will end up.

In order to prevent such an erroneous discrimination, for example, a discrimination output is obtained at a predetermined time point over three frames, and a correct discrimination signal is first obtained, but in this case, there is a problem that the response is slow. .

In view of such a point, an object of the present invention is to provide an odd / even field discriminating device which has a fast response and which does not malfunction due to mixing of noise or the like.

[Means for solving problems]

The present invention is a circuit which is triggered by the falling edge of a pulse in a composite sync signal including a vertical sync signal to generate a pulse train having a predetermined pulse width longer than 1/2 horizontal period and shorter than 1 horizontal period (13). And a circuit (14) for detecting that the pulse train has a pulse base with a different time length in the vicinity of each of the leading edge and the trailing edge of the vertical sync signal, and a pulse base with a different time length for a predetermined time An odd / even field discriminating device having a circuit (16E) for detecting that there is a space.

[Action]

With such a configuration, malfunction due to mixing of noise and the like can be prevented, and quick discrimination in the same field becomes possible.

〔Example〕

An embodiment of the odd / even field discriminating apparatus according to the present invention will be described below with reference to FIGS. 1 and 2.

The configuration of one embodiment of the present invention is shown in FIG. In FIG. 1, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and redundant description will be omitted.

In FIG. 1, the output of the vertical sync separation circuit (11) is supplied to the reset terminal of the counter (16E). Counter (1
The output of 6E) and the output of the third inverter (17) are supplied to the AND gate (19). In this embodiment, NTSC
In the case of the method, a counter (16E) counts five clock pulses and generates an output. The remaining structure is the same as that of the conventional example shown in FIG.

The operation of this embodiment is as follows.

In the case of shifting from the even field to the odd field, 1 to 525th line of the composite sync signal shown in FIG.
Until the falling of the th vertical sync pulse, the first and second MM
The Vs (13) and (14) operate in exactly the same manner as in the prior art example shown in FIG. 4, and the counter (16E) starts the counting operation.

During the third vertical sync pulse period, the counter (16E)
As shown in FIG. 2E, the output of the first MMV (13) inverted by the inverter (15), that is, one clock is counted.

During the fourth vertical sync pulse period, the counter (16E) is reset by the output of the vertical sync separation circuit (11) as shown in FIG. 2B. After the fifth vertical synchronizing pulse period, as shown in FIG. 5E, the counter (16E) keeps counting the clocks after reset, and the counter (16E) keeps counting 5 clocks during the 10th line period.
The second clock is counted and a pulse as shown in FIG. 2F is output. The output pulse of this counter (16E) opens the AND gate (19). The output of this counter (16E) becomes "Lo" at the 6th clock.

On the other hand, in the 10th line period, as shown in FIGS. 2C and 2D, the first MMV (1
The output of 3) becomes “Lo” for 3H / 4 hours, and the second MMV (14)
Output becomes "Lo". The output of the MMV (14) is inverted by the inverter (17) and supplied to the AND gate (19), and is output to the output terminal OUT as an odd field discrimination output.

In addition, when transitioning from the odd field to the even field, as in the conventional example shown in FIG.
Since (14) is maintained in a metastable state, no field discrimination output is generated.

According to the present embodiment, two output pulses of the MMV (14) that become stable at exactly constant intervals during the first vertical sync pulse period and the tenth line period of the odd field and the vertical sync separation circuit ( A field discrimination output is obtained by using the output pulse of 11) together, and it is possible to prevent malfunctions due to mixing of noise, etc., and it is possible to discriminate between odd and even within the vertical blanking period of the same field. .

〔The invention's effect〕

As described in detail above, according to the present invention, a circuit for generating a pulse train having an intermediate pulse width between H / 2 and 1H by being triggered by each pulse of the composite synchronizing signal is used to detect the front and rear of the vertical synchronizing signal. In each neighborhood of the edge, a pulse base with a predetermined interval having a different length from other parts is obtained, and the length and interval of this pulse base are detected, so that it is possible to quickly determine without malfunction. -An even field discriminating device can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of an odd / even field discriminating apparatus according to the present invention, FIG. 2 is a time chart for explaining the operation of an embodiment of the present invention, and FIG. FIG. 4 is a block diagram showing a configuration example of a conventional odd / even field discriminating device, and FIG. 5 is a time chart for explaining the operation of the conventional example of FIG. (11) is a vertical sync signal separation circuit, (13) and (14) are monostable multivibrators, and (16E) is a counter.

Claims (1)

[Claims] 1. A circuit which is triggered by the falling edge of a pulse in a composite synchronizing signal including a vertical synchronizing signal to generate a pulse train having a predetermined pulse width longer than 1/2 horizontal period and shorter than 1 horizontal period, A circuit for detecting that the pulse train has a pulse base having a different time length from the other portions in the vicinity of each of the leading edge and the trailing edge of the vertical synchronizing signal; An odd / even field discriminating device comprising: a circuit for detecting the presence.