JPH0719844B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0719844B2 JPH0719844B2 JP63235509A JP23550988A JPH0719844B2 JP H0719844 B2 JPH0719844 B2 JP H0719844B2 JP 63235509 A JP63235509 A JP 63235509A JP 23550988 A JP23550988 A JP 23550988A JP H0719844 B2 JPH0719844 B2 JP H0719844B2
- Authority
- JP
- Japan
- Prior art keywords
- bonding pad
- region
- resistance element
- semiconductor device
- bipolar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000005192 partition Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 230000007547 defect Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 230000002950 deficient Effects 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Landscapes
- Element Separation (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置，特にパターン形成工程時のPR不
良によるICの誤動作を防止するためのバイポーラICの構
造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a bipolar IC for preventing malfunction of the IC due to PR failure during a pattern forming process.
従来、バイポーラICにおいて、ボンディングパッド及び
それに接続された配線は、第２図で示すように、それら
の領域の直下には絶縁領域12を有する場合があり、配線
の場合は、必ず、その直下に絶縁領域を有している。こ
れはバイポーラICの場合、各素子のまわりは、素子間を
電気的に絶縁するため必ず、絶縁領域で囲まれているた
め、ボンディングパッドと素子を接続する配線は素子の
まわりを取り囲んでいる絶縁領域上を通らざるを得ない
ためである。2. Description of the Related Art Conventionally, in a bipolar IC, a bonding pad and a wiring connected to the bonding pad may have an insulating region 12 immediately below these regions, as shown in FIG. It has an insulating region. This is because in the case of a bipolar IC, each element is always surrounded by an insulating region in order to electrically insulate the elements from each other. Therefore, the wiring connecting the bonding pad and the element surrounds the element. This is because they have to pass over the area.
上述した従来のバイポーラICの構造は例えばパターンを
形成する工程であるPR工程において、ウエーハ上のゴミ
や、マスクパターンの欠陥が原因でボンディングパッド
やそれに接続された配線の直下にある絶縁領域に欠陥領
域14が発生した場合、前記ボンディングパッド及び、そ
れに接続された配線は前記欠陥領域14を通して絶縁領域
（バイポーラICの場合は、GND電位になる）と初期的に
ショートあるいは、初期的にショートしない場合でも、
後工程で、静電気等がボンディングパッドに印加された
場合は、前記欠陥領域14上の薄い絶縁膜が破壊されショ
ートとなり、不良となってしまう。前者の場合は、ウエ
ーハ段階での電気的特性試験で不良として除去できる
為、それ程、問題とならないが、後者の場合は、スクリ
ーニングが非常に難しく、品質上、重要な問題となる。The structure of the conventional bipolar IC described above, for example, in the PR process, which is a process of forming a pattern, has a defect in the insulating region immediately below the bonding pad or the wiring connected to it due to the dust on the wafer or the defect in the mask pattern. When the region 14 occurs, the bonding pad and the wiring connected thereto are initially short-circuited with the insulating region (in the case of a bipolar IC, it becomes the GND potential) through the defect region 14 or do not initially short-circuit. But
When static electricity or the like is applied to the bonding pad in a later step, the thin insulating film on the defective area 14 is destroyed and short-circuited, resulting in a defect. In the case of the former, it can be removed as a defect in the electrical characteristic test at the wafer stage, so that it does not pose a problem so much, but in the case of the latter, screening is very difficult and becomes an important problem in terms of quality.
［課題を解決するための手段］ 本発明の半導体装置は、半導体基板にバイポーラICが形
成された半導体装置において、ボンディングパッドと、
抵抗素子と、前記ボンディングパッドと前記抵抗素子と
を接続する配線とを同一のエピタキシャル領域内に共に
形成し、このエピタキシャル領域をその周りの他のエピ
タキシャル領域から電気的に絶縁すべく固定電位が与え
られた絶縁区画領域で取り囲み、かつ前記同一のエピタ
キシャル領域には外部から電位を与えないようにしたこ
とを特徴とする。[Means for Solving the Problems] A semiconductor device of the present invention is a semiconductor device in which a bipolar IC is formed on a semiconductor substrate.
A resistance element and a wiring connecting the bonding pad and the resistance element are formed together in the same epitaxial region, and a fixed potential is applied to electrically insulate this epitaxial region from other surrounding epitaxial regions. It is characterized in that the same epitaxial region is surrounded by the insulated partition region and no electric potential is applied to the same epitaxial region from the outside.
［実施例］ 次に、本発明について図面を参照して説明する。EXAMPLES Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の平面図である。ボンディン
グパッド３及びボンディングパッド３と抵抗素子６とを
接続する配線４の直下には前記抵抗素子６をまわりか
ら、電気的に絶縁するための絶縁領域５は存在していな
い。また、前記抵抗素子６のある島７には、外部から、
電位は与えられていない。FIG. 1 is a plan view of an embodiment of the present invention. Immediately below the bonding pad 3 and the wiring 4 connecting the bonding pad 3 and the resistance element 6, there is no insulating region 5 for electrically insulating the resistance element 6 from the surroundings. In addition, from the outside, the island 7 having the resistance element 6 is
No electric potential is applied.
以上説明したように、本発明は、ボンディングパッド及
びボンディングパッドと抵抗素子とを接続する配線の直
下に、絶縁領域を置かないことにより、パターン形成工
程時のPR工程におけるゴミやマスクパターンの欠陥に起
因する欠陥領域が、前記ボンディングパッドや配線の直
下に発生し静電破壊によりボンディングパッドと、抵抗
素子のある島とがショートした場合でもICの誤動作を防
止できる効果がある。As described above, the present invention does not place an insulating region immediately below the bonding pad and the wiring connecting the bonding pad and the resistance element, thereby eliminating dust and mask pattern defects in the PR process during the pattern forming process. Even if the defective area caused by the short circuit occurs between the bonding pad and the wiring and the short circuit occurs between the bonding pad and the island having the resistance element, the IC malfunction can be prevented.
第１図は、本発明の一実施例を示す平面図、第２図は、
従来の構造を示す平面図である。 1,8……スクライブ領域、2,9……不活性領域（エピタキ
シャル領域）、3,10……ボンディングパッド、4,11……
配線、5,12……絶縁領域、6,13……抵抗素子、７……抵
抗素子の島（エピタキシャル領域）、14……欠陥領域。FIG. 1 is a plan view showing an embodiment of the present invention, and FIG.
It is a top view which shows the conventional structure. 1,8 …… Scribe area, 2,9 …… Inactive area (epitaxial area), 3,10 …… Bonding pad, 4,11 ……
Wiring, 5,12 ... Insulation area, 6,13 ... Resistance element, 7 ... Resistance element island (epitaxial area), 14 ... Defect area.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/822 27/04 27/06 9169−4Ｍ Ｈ０１Ｌ 21/76 Ｊ 8826−4Ｍ 21/88 Ｚ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Office reference number FI technical display location H01L 21/822 27/04 27/06 9169-4M H01L 21/76 J 8826-4M 21/88 Z
Claims (1)
導体装置において、ボンディングパッドと、抵抗素子
と、前記ボンディングパッドと前記抵抗素子とを接続す
る配線とを同一のエピタキシャル領域内に共に形成し、
このエピタキシャル領域をその周りの他のエピタキシャ
ル領域から電気的に絶縁すべく固定電位が与えられた絶
縁区画領域で取り囲み、かつ前記同一のエピタキシャル
領域には外部から電位を与えないようにしたことを特徴
とする半導体装置。1. A semiconductor device having a bipolar IC formed on a semiconductor substrate, wherein a bonding pad, a resistance element, and a wiring connecting the bonding pad and the resistance element are formed together in the same epitaxial region,
This epitaxial region is surrounded by an insulating partition region to which a fixed potential is applied so as to electrically insulate it from other surrounding epitaxial regions, and the same epitaxial region is not applied with an external potential. Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63235509A JPH0719844B2 (en) | 1988-09-19 | 1988-09-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63235509A JPH0719844B2 (en) | 1988-09-19 | 1988-09-19 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0282568A JPH0282568A (en) | 1990-03-23 |
| JPH0719844B2 true JPH0719844B2 (en) | 1995-03-06 |
Family
ID=16987051
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63235509A Expired - Lifetime JPH0719844B2 (en) | 1988-09-19 | 1988-09-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0719844B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58178574A (en) * | 1982-04-13 | 1983-10-19 | Nec Corp | Input protecting device |
-
1988
- 1988-09-19 JP JP63235509A patent/JPH0719844B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0282568A (en) | 1990-03-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6531709B1 (en) | Semiconductor wafer and fabrication method of a semiconductor chip | |
| JPH0773106B2 (en) | Method for manufacturing semiconductor device | |
| USH1267H (en) | Integrated circuit and lead frame assembly | |
| JPS6080264A (en) | Semiconductor device | |
| US5175397A (en) | Integrated circuit chip package | |
| JPH09120974A (en) | Semiconductor device | |
| JPH07122604A (en) | Semiconductor integrated circuit device | |
| JPH0719844B2 (en) | Semiconductor device | |
| JP2982182B2 (en) | Resin-sealed semiconductor device | |
| JP2500643B2 (en) | Semiconductor device | |
| JPH09199672A (en) | Semiconductor integrated circuit device and method of inspection | |
| JP2778235B2 (en) | Semiconductor device | |
| JPH0476927A (en) | Semiconductor integrated circuit | |
| JP2855884B2 (en) | Semiconductor device | |
| JP2972473B2 (en) | Semiconductor device | |
| JPH025416A (en) | Semiconductor integrated circuit device | |
| JPH0338052A (en) | Semiconductor integrated circuit device and manufacture thereof | |
| JP2003188262A (en) | Semiconductor element | |
| JPH06163629A (en) | Bonding pad structure for semiconductor integrated circuit | |
| JPH0513658A (en) | Lead frame for semiconductor device | |
| JPH09199565A (en) | Process monitor circuit | |
| JPH04120771A (en) | Delay cell for master slice system ic device | |
| JPH04113641A (en) | Semiconductor integrated circuit device | |
| JPH0338757B2 (en) | ||
| JPS612343A (en) | Semiconductor device |