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JPH0719912B2 - Thin film semiconductor manufacturing equipment - Google Patents
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JPH0719912B2 - Thin film semiconductor manufacturing equipment - Google Patents

Thin film semiconductor manufacturing equipment

Info

Publication number
JPH0719912B2
JPH0719912B2 JP63223395A JP22339588A JPH0719912B2 JP H0719912 B2 JPH0719912 B2 JP H0719912B2 JP 63223395 A JP63223395 A JP 63223395A JP 22339588 A JP22339588 A JP 22339588A JP H0719912 B2 JPH0719912 B2 JP H0719912B2
Authority
JP
Japan
Prior art keywords
substrate
reaction chamber
gas
film
film semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP63223395A
Other languages
Japanese (ja)
Other versions
JPH0272677A (en
Inventor
健司 中谷
宏 岡庭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teijin Ltd
Original Assignee
Teijin Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teijin Ltd filed Critical Teijin Ltd
Priority to JP63223395A priority Critical patent/JPH0719912B2/en
Publication of JPH0272677A publication Critical patent/JPH0272677A/en
Publication of JPH0719912B2 publication Critical patent/JPH0719912B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/548Amorphous silicon PV cells

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  • Photovoltaic Devices (AREA)

Description

【発明の詳細な説明】 〈技術分野〉 本発明は化学的気相分解によるプラズマ雰囲気中で搬送
される基板上に、単層または複数層の薄膜半導体層を成
膜してなる薄膜半導体の製造装置に関し、特に非晶質シ
リコン太陽電池の製造に好適な薄膜半導体の製造装置に
関する。
TECHNICAL FIELD The present invention relates to the production of a thin film semiconductor in which a single layer or a plurality of thin film semiconductor layers are formed on a substrate transported in a plasma atmosphere by chemical vapor decomposition. The present invention relates to an apparatus, and particularly to an apparatus for manufacturing a thin film semiconductor suitable for manufacturing an amorphous silicon solar cell.

〈従来技術〉 化学的気相分解(以降CVDと記す)によるプラズマ雰囲
気中で基板上に単層または複数層の薄膜半導体層を成膜
して半導体装置を製造する方法は、例えばシラン(Si
H4)ガスを放電分解して非晶質シリコン太陽電池を製造
する方法として、広く実施されている公知の技術であ
る。かかる製造方法において、効率よく薄膜半導体層を
成膜する、即ち大量生産に適した製造方法の一つとし
て、基板を連続的に搬送させながらCVDプラズマ放電雰
囲気中を通過させる方法が公知である。
<Prior Art> A method of manufacturing a semiconductor device by forming a single-layer or multiple-layer thin-film semiconductor layers on a substrate in a plasma atmosphere by chemical vapor decomposition (hereinafter referred to as CVD) is described in, for example, silane (Si
This is a well-known technique that is widely practiced as a method for producing an amorphous silicon solar cell by discharge decomposition of H 4 ) gas. In such a manufacturing method, as one of the manufacturing methods suitable for efficiently forming a thin film semiconductor layer, that is, suitable for mass production, there is known a method of passing a substrate through a CVD plasma discharge atmosphere while continuously transferring the substrate.

この方法は大別して次の2種類に分けられる。1つは、
基板の仕込み室と取り出し室の間にプラズマ放電を行な
うための完全に分離・独立した単室,必要に応じて複数
室からなる反応室を設置し、枚葉の基板を移動台車等に
乗せて各室を順次移送させながら成膜を行なうロードロ
ック方式である。他の1つは、特開昭58−216475号公
報,特開昭59−34668号公報等の如く基板自体を長尺の
巻き物にして、巻出し室と巻取り室の間に、基板通路で
連絡した、単室,必要に応じて複数室からなる反応室を
設置し、連続的に搬送される薄膜状基板に成膜を行なう
ロール・ツー・ロール方式である。
This method is roughly classified into the following two types. One is
A completely separate and independent single chamber for plasma discharge and a reaction chamber consisting of multiple chambers are installed between the substrate loading chamber and the substrate loading chamber, and a single substrate is placed on a moving carriage. It is a load-lock system in which film formation is performed while sequentially moving each chamber. The other one is that the substrate itself is formed into a long roll as in JP-A-58-216475 and JP-A-59-34668, and a substrate passage is provided between the unwinding chamber and the winding chamber. This is a roll-to-roll system in which a reaction chamber consisting of a single chamber and, if necessary, a plurality of chambers, which are communicated with each other, is installed, and a film is formed on a continuously conveyed thin film substrate.

かかる製造方式で、更に生産効率を高めるために高速成
膜を行なう場合、従来技術においては、充分な原料ガス
を供給しながら放電電力を増加させてプラズマ雰囲気中
の活性種濃度を高める方法がとられてきた。しかしこの
ような方法では放電電力の増加とともにプラズマ雰囲気
中の荷電粒子の運動エネルギーも増大するため、成膜面
が荷電粒子の衝突で損傷する、云わゆるプラズマ損傷が
顕著になって半導体薄膜の特性が損われ、半導体装置と
しての特性に悪影響を及ぼす欠点があった。基板上に半
導体層が形成されており、更にこの上に別の種類の半導
体層を形成する場合、具体的には非晶質シリコン太陽電
池の製造におけるp層又はn層を基板上に形成後その上
にi層を形成する場合には、この影響が顕著であった。
In the case of performing high-speed film formation in order to further increase the production efficiency in such a manufacturing method, the conventional technique is to increase the discharge power while supplying sufficient raw material gas to increase the concentration of active species in the plasma atmosphere. Has been. However, in such a method, the kinetic energy of the charged particles in the plasma atmosphere increases as the discharge power increases, so that the film formation surface is damaged by the collision of the charged particles. However, there is a drawback that the characteristics of the semiconductor device are adversely affected. When a semiconductor layer is formed on a substrate and another type of semiconductor layer is further formed on the semiconductor layer, specifically, after forming a p layer or an n layer in the production of an amorphous silicon solar cell on the substrate. This effect was significant when the i layer was formed on top of it.

さらに高性能の薄膜半導体層、特に非晶質シリコン太陽
電池を製造しようとした場合堆積される膜の厚み方向に
組成やドーピング不純物量を変化させて成膜する事が好
ましい。膜の厚さ方向で組成やドーピング不純物量を変
化させて成膜する為には単一の反応室を用いて各層の成
膜ごとに反応ガスを切り替えるか、複数の専用反応室を
連結して反応室ごとに反応ガスを変えて成膜し、順次基
板を移送させる方法が行なわれている。これは単一の反
応室内ではプラズマ雰囲気中のガス組成は空間的にほぼ
均一であり、反応室内に組成の異なったガス雰囲気を適
当に分布させることができないためである。
In order to manufacture a high performance thin film semiconductor layer, particularly an amorphous silicon solar cell, it is preferable to change the composition and the amount of doping impurities in the thickness direction of the deposited film. To change the composition and the amount of doping impurities in the film thickness direction to form a film, use a single reaction chamber to switch the reaction gas for each layer formation, or connect multiple dedicated reaction chambers. A method is used in which the reaction gas is changed for each reaction chamber to form a film and the substrates are sequentially transferred. This is because the gas composition in the plasma atmosphere is spatially substantially uniform in a single reaction chamber, and gas atmospheres having different compositions cannot be appropriately distributed in the reaction chamber.

しかし、何らかの方法で単一反応室内のガス組成に所望
の空間的分布をもたせることが可能ならば、単一の反応
室内で定常的に放電するプラズマ雰囲気中のガス組成の
異なる領域を基板を移送するだけで組成やドーピング量
の異なった複数層を一気に形成することが可能となり、
製造工程及び装置の簡略化が実現される。
However, if it is possible to give a desired spatial distribution to the gas composition in a single reaction chamber by some method, the substrate is transferred through a region of different gas composition in a plasma atmosphere that constantly discharges in the single reaction chamber. It is possible to form multiple layers with different compositions and doping amounts all at once,
A simplification of the manufacturing process and equipment is realized.

また、CVDによるプラズマ雰囲気中で基板上に薄膜半導
体層を形成する手法の一つであるロール・ツー・ロール
方式においても、単一反応室内の反応ガスの組成に所望
の空間分布をもたせることができないために、従来、次
のような欠点が存在した。即ち、ロール・ツー・ロール
方式では定常放電プラズマ中で可撓性の帯状基板を連続
搬送して成膜するために、各反応室には同一組成の反応
ガスを連続的に供給する必要があって一走行で組成やド
ーピングの異なる複数層を形成するためにはその数だけ
の専用反応室が不可欠であった。
Also, in the roll-to-roll method, which is one of the methods for forming a thin film semiconductor layer on a substrate in a plasma atmosphere by CVD, it is possible to give a desired spatial distribution to the composition of the reaction gas in a single reaction chamber. Because of this, the following drawbacks existed in the past. That is, in the roll-to-roll system, it is necessary to continuously supply the reaction gas having the same composition to each reaction chamber in order to continuously convey the flexible strip-shaped substrate in the steady discharge plasma to form a film. In order to form multiple layers with different compositions and dopings in a single run, the number of dedicated reaction chambers was indispensable.

更に、複数の反応室をもつロール・ツー・ロール方式に
おいては、各反応室は完全に分離・独立している訳では
なく、基板の通路で連結されている。このため、隣接し
た反応室間で該基板通路を経由して各反応室の反応ガス
の相互混合をさけることができない。この相互混合が作
成しようとする薄膜半導体装置の特性を劣化させる場合
には反応室間の基板通路に一方向性のガスの流れを形成
したり、特開昭58−216475号公報,特開昭59−34668号
公報等に開示の如く、反応室間に専用の緩衝室を設けて
抽気又は差動排気して必要な程度迄ガス分離を行なって
いた。しかし、かかる従来方法ではひとたびこれらガス
分離機構を越えて侵入した隣接反応室の反応ガスは反応
室全域に拡散して反応室内で均一となり、隣接層との界
面の膜厚方向の組成分布や不純物分布のプロファイルの
制御性、例えばゆるやかな傾斜接合にするか、シャープ
な階段接合にするかと云った制御性に乏しかった。
Furthermore, in the roll-to-roll system having a plurality of reaction chambers, the reaction chambers are not completely separated and independent, but are connected by the passage of the substrate. For this reason, it is not possible to avoid mutual mixing of the reaction gases in the reaction chambers between the adjacent reaction chambers via the substrate passage. If this mutual mixing deteriorates the characteristics of the thin film semiconductor device to be produced, a unidirectional gas flow may be formed in the substrate passage between the reaction chambers, or JP-A-58-216475 and JP-A-58-216475. As disclosed in Japanese Patent Laid-Open No. 59-34668, a dedicated buffer chamber is provided between the reaction chambers to bleed or differentially exhaust gas to perform gas separation to the required extent. However, in such a conventional method, once the reaction gas in the adjacent reaction chamber that has penetrated beyond the gas separation mechanism diffuses throughout the reaction chamber and becomes uniform in the reaction chamber, the composition distribution in the thickness direction at the interface with the adjacent layer and impurities The controllability of the profile of the distribution, for example, the controllability such as a gentle graded junction or a sharp stepwise junction, was poor.

〈目的〉 本発明は上記従来技術の欠点を解消し、高品質の薄膜半
導体装置を高速で形成する為になされたもので、ひとつ
の反応室内においてプラズマ衝撃を低下させ良好な界面
を形成する手段と反応室内の反応ガスの空気分布を制御
し堆積される膜の厚み方向に組成や不純物分布を制御す
る手段を有した薄膜半導体の製造装置を提供する事を目
的とする。
<Purpose> The present invention has been made to solve the above-mentioned drawbacks of the prior art and to form a high-quality thin film semiconductor device at high speed. Means for forming a favorable interface by reducing plasma impact in one reaction chamber Another object of the present invention is to provide a thin-film semiconductor manufacturing apparatus having means for controlling the air distribution of the reaction gas in the reaction chamber and controlling the composition and impurity distribution in the thickness direction of the deposited film.

〈発明の構成〉 上述の目的は以下の本発明により達成される。すなわ
ち、本発明は基板を移送しつつ化学的気相分解によるプ
ラズマ雰囲気中で該基板上に所定の半導体層を形成する
薄膜半導体の製造装置において、対向した放電電極の基
板入側の所定範囲の中間に放電電極と平行にプラズマ衝
撃を低下させる多孔板からなる格子電極を少なくとも基
板全巾以上に亘って設けると共に、反応ガスを遮断する
仕切板を基板搬送方向に所定間隔で放電電極面に垂直方
向に配設して、少なくともプラズマ雰囲気を基板通路等
の限られた隙間を除いて基板搬送方向にガス拡散のない
複数の区域に区画し、膜厚方向に所定の組成分布を有す
る薄膜を形成するようになした反応室を有することを特
徴とする薄膜半導体の製造装置である。
<Structure of Invention> The above-mentioned object is achieved by the present invention described below. That is, the present invention is a thin-film semiconductor manufacturing apparatus for forming a predetermined semiconductor layer on a substrate in a plasma atmosphere by chemical vapor decomposition while transferring the substrate, in a predetermined range on the substrate entry side of opposed discharge electrodes. A grid electrode consisting of a perforated plate that reduces the plasma impact is provided in the middle in parallel with the discharge electrode over at least the entire width of the substrate, and partition plates that block the reaction gas are perpendicular to the discharge electrode surface at predetermined intervals in the substrate transfer direction. Direction, and at least the plasma atmosphere is divided into a plurality of areas with no gas diffusion in the substrate transport direction except for a limited gap such as a substrate passage to form a thin film having a predetermined composition distribution in the film thickness direction. The thin film semiconductor manufacturing apparatus is characterized by having a reaction chamber configured as described above.

上述の本発明は以下のようにしてなされたものである。
すなわち、本発明者らは前述の特開昭59−34668号公報
開示のものと同様な連続プラズマCVD装置で高品質、す
なわち太陽エネルギーの変換効率の高い非晶質シリコン
太陽電池の連続大量生産について検討してきたが、生産
性向上のため堆積速度を上げるために放電電力を大きく
するとその変換効率が下がる現象が観察された。そし
て、その原因の1つはi層の形成初期の下層からの不純
物混入に基づくもので、膜形成初期の下層のプラズマ衝
撃に基づくものであることを見出した。そして、この対
策について種々検討の結果放電電極間の基板入側のみに
格子電極を設けることにより格子電極存在部及びその近
傍のみで効果的にプラズマエネルギーが低下し前記プラ
ズマ損傷が防止でき、且つ、格子電極部以外では格子電
極の影響を受けることなく高速膜形成ができることを見
いだした。
The present invention described above is made as follows.
That is, the present inventors have succeeded in continuous mass production of amorphous silicon solar cells of high quality, that is, high conversion efficiency of solar energy, in a continuous plasma CVD apparatus similar to that disclosed in JP-A-59-34668. As a result of studying, it was observed that when the discharge power was increased to increase the deposition rate in order to improve productivity, the conversion efficiency was lowered. It has been found that one of the causes is that impurities are mixed from the lower layer in the initial stage of forming the i layer, and the plasma impact of the lower layer in the early stage of film formation is caused. Then, as a result of various investigations on this countermeasure, by providing the lattice electrode only on the substrate entrance side between the discharge electrodes, the plasma energy can be effectively reduced only in the lattice electrode existing portion and its vicinity, and the plasma damage can be prevented, and It was found that high-speed film formation can be performed without being affected by the lattice electrode except for the lattice electrode portion.

さらに高品質i層を形成する為にはi層膜中の不純物濃
度、特に、隣接するp層を堆積する反応室より混入して
くる極微量のB原子濃度のi層膜中での厚さ方向分布が
重要である事を見いだした。そしてその制御手段を種々
検討の結果、放電電極間に垂直にガスを遮断する仕切板
を設けてプラズマ雰囲気を区画してもプラズマ放電は影
響されず安定製膜ができることを見出すと共に、ガスを
遮断できる仕切板により区画されたプラズマ雰囲気の各
区域間の反応ガスの流路を基板表面近傍等に限定するこ
とにより、ガス導入口と排気口の基板搬送方向の位置に
より基板搬送方向のガス組成分布を制御できることを見
出した。本発明はこれら知見に基いてなされたものであ
る。
In order to form a high-quality i-layer, the impurity concentration in the i-layer film, especially the thickness in the i-layer film having a very small amount of B atom concentration mixed in from the reaction chamber where the adjacent p-layer is deposited. We have found that the directional distribution is important. As a result of various investigations on the control means, it was found that even if a partition plate that vertically shields gas between discharge electrodes is provided to partition the plasma atmosphere, plasma discharge is not affected and stable film formation can be performed. The gas composition distribution in the substrate transfer direction depends on the position of the gas inlet and exhaust ports in the substrate transfer direction by limiting the flow path of the reaction gas between each area of the plasma atmosphere partitioned by the partition plate Found that you can control. The present invention has been made based on these findings.

以下本発明の詳細を説明する。The details of the present invention will be described below.

本発明の格子電極は放電電極の基板入側のみに設ける。
その設ける領域は形成する半導体及び格子電極に印加す
るバイアス電圧等に関係し、実験的に定める必要がある
が膜形成速度を考慮すると基板入口から放電電極の半分
まで位の間で適宜選定するのが実用的である。格子電極
の形状は網状体,櫛状等多数の孔を全面に亘って有する
多孔板が使用される。その孔の大きさは、活性種の通過
が出来るだけ阻げない範囲でプラズマを閉じ込めること
ができる範囲で選定され、実際には実験的に定めるが網
状の場合は50番メッシュ以下で選定するのが実用的であ
る。
The grid electrode of the present invention is provided only on the substrate entry side of the discharge electrode.
The region to be provided is related to the semiconductor to be formed and the bias voltage applied to the lattice electrode, and it is necessary to experimentally determine it. However, considering the film formation rate, it is appropriately selected between the substrate entrance and half the discharge electrode. Is practical. A perforated plate having a large number of holes such as a mesh body and a comb shape is used as the shape of the grid electrode. The size of the hole is selected within the range where plasma can be confined within the range where the passage of active species is not blocked as much as possible. Actually, it is experimentally determined. Is practical.

また、本発明の仕切板はガスを遮断できるものであれば
良く、その材は特に限定されないが、中でもプラズマ損
傷のないものが好ましく、ステンレス等が使用される。
なお、仕切板は反応室と共に接地するのが一般的である
が、浮遊もしくは適当なバイアス電圧を印加させても良
い。そしてその形状は、基板搬送方向のガスの拡散が無
視できるものであれば良く。通常は基板搬送路及び放電
電極面との間に微小な間隙を有するのみで、その他の部
分は完全に遮断し、前記間隙以外ではガス移動のない形
状が選定される。このようにすると間隙部でガス流速が
大となり、ガス拡散の防止がより完全となる点で好まし
い。しかし、反応室内の部材の配置によりガス流路が限
定される場合には該ガス流路を遮断するように仕切板は
設置すれば良いことは云うまでもない。なお、仕切板は
少なくとも基板前面との間にガス流路となるスリットを
有する必要がある。
Further, the partition plate of the present invention is not particularly limited as long as it can block gas and the material thereof is not particularly limited, and one which does not have plasma damage is preferable, and stainless steel or the like is used.
The partition plate is generally grounded together with the reaction chamber, but it may be floated or an appropriate bias voltage may be applied. The shape may be any as long as gas diffusion in the substrate transport direction can be ignored. Normally, a shape is selected in which only a minute gap is provided between the substrate transport path and the discharge electrode surface, and the other portions are completely cut off, and gas movement does not occur outside the gap. This is preferable in that the gas flow velocity in the gap becomes large and the prevention of gas diffusion becomes more complete. However, it goes without saying that when the gas flow path is limited by the arrangement of the members in the reaction chamber, the partition plate may be installed so as to block the gas flow path. The partition plate needs to have a slit serving as a gas flow path at least between the partition plate and the front surface of the substrate.

又仕切板の数及びその間隙は、形成する膜の膜厚方向の
プロファイルに応じて選定される。この選定は実験によ
る。
Further, the number of partition plates and their gaps are selected according to the profile of the film to be formed in the film thickness direction. This selection depends on the experiment.

一方反応ガスの導入口,排気口の配置も、同様に形成す
る膜厚方向のプロファイルに応じて実験により選定され
る。例えば2層膜を形成する場合には夫々の反応ガスの
導入口を反応室の両端に、共通の排気口をその中間に順
次配置すれば良く、又一層膜でその膜内の組成を変化さ
せたい場合は夫々の反応ガスの導入口を反応室の基板搬
送方向の両端部に配置し、その一端に共通の排気口を設
けること等により適当な勾配の組成分布を得ることがで
きる。
On the other hand, the disposition of the reaction gas inlet and exhaust port is also selected by experiment according to the profile in the film thickness direction to be similarly formed. For example, in the case of forming a two-layer film, the reaction gas inlets may be sequentially arranged at both ends of the reaction chamber, and the common exhaust ports may be sequentially arranged in the middle thereof. In addition, a single-layer film may change the composition in the film. If desired, the respective reaction gas inlets may be arranged at both ends of the reaction chamber in the substrate transport direction, and a common exhaust port may be provided at one end thereof to obtain an appropriate gradient composition distribution.

なお、本発明は長尺基板上に必要な半導体層を連続的に
順次形成する場合に有利に適用できる。中でも基板上に
既に半導体層が形成され、その上にこれと別種の半導体
層を形成する場合に効果的である。さらに、特開昭58−
216475号公報等の如く複数の反応室を連結したものにお
いて、その一層のプロファイルを制御するのにも適用で
きる。特に非晶質シリコン半導体層の形成、中でも前述
の通り大きな問題を有する非晶質シリコン太陽電池の連
続製造におけるi層の形成において大きな効果を奏す
る。
The present invention can be advantageously applied to the case where required semiconductor layers are continuously and sequentially formed on a long substrate. Above all, it is effective when a semiconductor layer is already formed on the substrate and a semiconductor layer of a different type from this is formed on the semiconductor layer. Furthermore, JP-A-58-
In the case where a plurality of reaction chambers are connected as in Japanese Patent No. 216475, it can be applied to control the profile of one layer. In particular, the present invention exerts a great effect in forming an amorphous silicon semiconductor layer, particularly in forming an i layer in continuous production of an amorphous silicon solar cell having a large problem as described above.

以下、本発明の詳細を非晶質シリコン太陽電池の連続製
造を例に説明する。
Hereinafter, the details of the present invention will be described by taking continuous production of amorphous silicon solar cells as an example.

〈実施例〉 第1図は上記実施例の非晶質シリコン太陽電池の連続製
造装置の構成図、第2図はその反応室2の断面図であ
る。
<Embodiment> FIG. 1 is a configuration diagram of a continuous production apparatus for an amorphous silicon solar cell of the above embodiment, and FIG. 2 is a sectional view of a reaction chamber 2 thereof.

その基本構成は前述の特開昭58−216475号公報,特開昭
59−34668号公報開示のものと同じで、p型,i型及びn
型の各非晶質シリコン層を形成するCVDプラズマ放電の
各反応室1,2,3及び巻出室18並びに巻取室19をガス隔離
のための緩衝室13で連結し、巻出しロール20から巻取り
ロール21へ基板17をロール・ツー・ロール方式で移送し
つつp,i,nの3層を連続形成する構成となっている。な
お、図の4〜9は放電電極で、図の10は各放電電極に高
周波電力を供給する高周波電源である。
The basic structure is as described in the above-mentioned JP-A-58-216475,
No. 59-34668, which is the same as that disclosed in Japanese Patent Laid-Open No. 59-34668.
The reaction chambers 1, 2, 3 of the CVD plasma discharge forming the respective amorphous silicon layers of the mold and the unwinding chamber 18 and the winding chamber 19 are connected by the buffer chamber 13 for gas isolation, and the unwinding roll 20 The substrate 17 is transferred from the take-up roll 21 to the take-up roll 21 by a roll-to-roll method, and three layers of p, i, and n are continuously formed. In addition, 4-9 of a figure are discharge electrodes, 10 of a figure is a high frequency power supply which supplies high frequency electric power to each discharge electrode.

かかる反応室分離型ロール・ツー・ロール方式のCVDプ
ラズマ放電装置で、SiH4ガス等周知の所定の原料ガスを
各反応室1,2,3に供給してロール状に巻き上げた長尺基
板上にp,i,n形非晶質シリコン膜を順次積層して太陽電
池を形成した。本例では前述の通り太陽電池の特性を左
右するi形非晶質シリコン層を形成する反応室2におい
て、対向する放電電極6,7の中間に格子電極22を設置し
た。該格子電極22は可撓性の長尺の基板17の進行方向に
沿って、放電電極6,7の前半1/3を覆うように設けてあ
る。該格子電極22には電源(図示省略)より所定バイア
ス電位を印加するようになっている。格子電極22の材料
はステンレス合金の金網とし、その網の粗さはプラズマ
を閉じ込めるのに充分細かく、かつ、活性種の通過を阻
げない程度に粗いもの、本例では20番メッシュの網目と
した。格子電極22は基板17から25mm離れて設置され(放
電電極間距離は50mm)、+200〜−200Vの間の適当な値
に直流電圧が設定できる電源によりバイアスされてい
る。
With such a reaction chamber separation type roll-to-roll type CVD plasma discharge device, a well-known predetermined raw material gas such as SiH 4 gas is supplied to each reaction chamber 1, 2, 3 and rolled up on a long substrate. A p-type, i-type, and n-type amorphous silicon film were sequentially stacked to form a solar cell. In this example, as described above, in the reaction chamber 2 in which the i-type amorphous silicon layer that affects the characteristics of the solar cell is formed, the grid electrode 22 is installed between the opposing discharge electrodes 6 and 7. The grid electrode 22 is provided along the traveling direction of the flexible long substrate 17 so as to cover the first half 1/3 of the discharge electrodes 6 and 7. A predetermined bias potential is applied to the grid electrode 22 from a power source (not shown). The material of the grid electrode 22 is a metal mesh of stainless alloy, the roughness of the mesh is fine enough to confine the plasma, and coarse enough not to block the passage of active species, in this example a mesh of 20 mesh did. The grid electrode 22 is installed 25 mm away from the substrate 17 (distance between discharge electrodes is 50 mm), and is biased by a power source capable of setting a DC voltage to an appropriate value between +200 and -200V.

対向する放電電極6,7の中間のプラズマ雰囲気を基板搬
送方向に必要な通路を除いて区画する仕切板11を電極面
に垂直かつ第2図の通り隙間14を除いて反応室の全断面
を遮断するように基板の搬送方向に所定間隔になるよう
に4枚設置した。従って該仕切板11によりプラズマ空間
は、電極面内で複数の区域に区分され、反応室2の基板
搬送方向下流端に設けたガス導入口15から供給された反
応ガスはその上流端部の排気ポート16に達するためには
必ず該仕切板11で設定された隙間14を通って流れる。
A partition plate 11 for partitioning a plasma atmosphere in the middle of the discharge electrodes 6 and 7 facing each other except a passage required in the substrate transport direction is perpendicular to the electrode surface and the entire cross section of the reaction chamber is formed except for a gap 14 as shown in FIG. Four pieces were installed at predetermined intervals in the substrate transfer direction so as to be cut off. Therefore, the partition plate 11 divides the plasma space into a plurality of areas within the electrode surface, and the reaction gas supplied from the gas inlet 15 provided at the downstream end of the reaction chamber 2 in the substrate transport direction is exhausted at its upstream end. In order to reach the port 16, it always flows through the gap 14 set by the partition plate 11.

なお、前述の通り仕切板11は隙間14を形成するように対
向する放電電力の双方に対して若干の距離を離して設置
されている。この隙間14は1つには反応ガスの通路とし
て、また、パワー電極に対して電気絶縁のため、そして
アース電極に対しては基板17の通路を目的としており、
本実施例では3mmとした。ガス仕切板11の材料は電気的
に導体,不導体のいずれであっても本発明の目的を達す
るが、プラズマ雰囲気中に不純物を放出しないことが必
要である。本例ではステンレス合金で作成し、電気的に
はアースに接地した。
As described above, the partition plate 11 is installed so as to form the gap 14 and is apart from the opposing discharge powers by a slight distance. This gap 14 is intended as a passage for the reaction gas, an electrical insulation for the power electrode, and a passage for the substrate 17 for the ground electrode.
In this embodiment, it is 3 mm. Although the material of the gas partition plate 11 is either electrically conductive or non-conductive, the object of the present invention is achieved, but it is necessary that impurities are not emitted into the plasma atmosphere. In this example, it was made of a stainless alloy and electrically grounded to earth.

基板17として、本例では厚さ100μmのポリエチレンテ
レフタリート上のフイルム上に3000Åのアルミ金属と50
Åステンレス合金を順次積層して用い、前述の特開昭59
−34668号公報同様にしp,i,n形の非晶質シリコン層を一
走行で連続成膜した。pおよびn形の非晶質シリコン膜
の厚さは200〜300Å,i形非晶質シリコン層の厚さは5000
Å程度となるように、放電電力,基板搬送速度,反応ガ
ス圧力を制御した。
In this example, as the substrate 17, 3000 Å of aluminum metal and 50 on the film on the polyethylene terephthalate with a thickness of 100 μm are used.
Å Stainless steel alloys are sequentially laminated and used, and
A p, i, n type amorphous silicon layer was continuously formed in one run in the same manner as in Japanese Patent Publication No. 34668. The p-type and n-type amorphous silicon films have a thickness of 200 to 300Å, and the i-type amorphous silicon layer has a thickness of 5000.
The discharge power, the substrate transfer speed, and the reaction gas pressure were controlled to be about Å.

ところで本例のロール・ツー・ロール方式では、通常、
隣接するp,n形非晶質シリコンを形成する反応室1,3から
i層を形成する反応室2へB2H6及びPH3ガスが緩衝室13
を経由して微量混入する。
By the way, in the roll-to-roll system of this example, normally,
The B 2 H 6 and PH 3 gases are transferred from the adjacent reaction chambers 1 and 3 for forming p- and n-type amorphous silicon to the reaction chamber 2 for forming the i-layer.
A small amount is mixed in via.

ところで反応室2は前述の構成としてあるので、i形非
晶質シリコンを形成する反応室2において判のガスはn
層用の反応室3寄りのガス導入口15から導入されp層用
の反応室1寄りの排気口16の方向に流れ、上記混入の拡
散は後述の通り制御される。
By the way, since the reaction chamber 2 has the above-described structure, the reaction gas 2 in the reaction chamber 2 for forming i-type amorphous silicon is n
The gas is introduced from the gas introduction port 15 near the reaction chamber 3 for layers and flows toward the exhaust port 16 near the reaction chamber 1 for p layers, and diffusion of the above mixture is controlled as described later.

第3図に格子電極22に負のバイアス電位(−20V)を印
加し、放電電極6,7に印加する高周波電力を変えてi形
非晶質シリコン層を成膜した場合の、太陽電池特性(変
換効率)と放電電力の関係を実線Aで示した。当然のこ
とながら、放電電力の増加は第3図に同時に示したよう
に堆積速度を上昇させ、高速成膜に対応している。本発
明による製造方法では、第3図の実線A′に示すごと
く、放電電力が増加しても太陽電池の特性の悪化はほと
んど見られない。
FIG. 3 shows the solar cell characteristics when a negative bias potential (−20 V) is applied to the grid electrode 22 and the high frequency power applied to the discharge electrodes 6 and 7 is changed to form the i-type amorphous silicon layer. The relationship between (conversion efficiency) and discharge power is shown by the solid line A. As a matter of course, the increase of the discharge power increases the deposition rate as shown in FIG. 3 at the same time, which corresponds to the high speed film formation. In the manufacturing method according to the present invention, as shown by the solid line A'in FIG. 3, the characteristics of the solar cell are hardly deteriorated even when the discharge power is increased.

一方、格子電極22を除いた上述の装置で全く同様にして
形成した太陽電池の特性は、第3図に破線B′で示した
ごとく、放電電力の増加に伴って太陽電池特性が低下し
た。
On the other hand, regarding the characteristics of the solar cell formed in the same manner as the above apparatus except for the grid electrode 22, the characteristics of the solar cell deteriorated as the discharge power increased, as shown by the broken line B'in FIG.

さらに格子電極22は設置した状態で、仕切板11のみを除
いた上述の装置で全く同様にして形成した太陽電池の特
性は、第3図に一点鎖線C′で示したごとく、全ての放
電電力領域で仕切板11を設けた実線A′に比して太陽電
池特性が低下した。以上の通り本発明にもとづいて作成
した太陽電池はその特性が向上しており、本発明の有効
性が確認された。
Furthermore, the characteristics of the solar cell formed in exactly the same manner as the above-mentioned device except for the partition plate 11 with the grid electrode 22 installed are as shown by the chain line C'in FIG. The solar cell characteristics were lower than the solid line A'provided with the partition plate 11 in the region. As described above, the characteristics of the solar cell produced according to the present invention are improved, and the effectiveness of the present invention was confirmed.

一方、本実施例で成膜したp,i,n積層型の非晶質シリコ
ン膜について、ボロン(B)原子のデプスプロファイル
を二次イオン質量分析法(SiMS)で測定した結果を第4
図に実線Aで示す。比較のために、他の条件は同じに、
仕切板11を設置しない従来装置の場合により形成した同
じp,i,n積層型の非晶質シリコン膜の分析結果を破線B
で同図に示した。
On the other hand, the depth profile of the boron (B) atom in the p, i, n stacked type amorphous silicon film formed in this example was measured by the secondary ion mass spectrometry (SiMS) to obtain the fourth result.
The solid line A is shown in the figure. For comparison, other conditions are the same,
The analysis result of the same p, i, n laminated type amorphous silicon film formed by the conventional device without the partition plate 11 is shown by a broken line B.
Is shown in FIG.

仕切板11を設けない従来装置の場合には隣接反応室1,3
から混入したB2H6ガスがi層用の反応室2全体に均一に
拡散する結果、i層中のB原子の膜厚方向の濃度プロフ
ァイルはフラットになっている。一方、仕切板11を設置
した実施例の場合はp層とi層との界面におけるB原子
の組成プロファイルは切れが急峻になっており、また、
i層中のプロファイルは一定の勾配の傾斜をもっている
ことがわかる。この結果は、仕切板11によってi反応室
2のプラズマ空間を区分することにより、同一反応室内
であってもn層用の反応室3寄りの部分からp層用の反
応室1寄りの部分に亘ってプラズマ雰囲気中の反応ガス
の組成が一定の空間分布を有することを示している。
In the case of the conventional device without the partition plate 11, the adjacent reaction chambers 1, 3
As a result, the B 2 H 6 gas mixed in from the inside uniformly diffuses throughout the reaction chamber 2 for the i-layer, so that the concentration profile of B atoms in the i-layer in the film thickness direction is flat. On the other hand, in the case of the embodiment in which the partition plate 11 is installed, the composition profile of B atoms at the interface between the p layer and the i layer is sharply cut, and
It can be seen that the profile in the i-layer has a constant slope. This result shows that by partitioning the plasma space of the i reaction chamber 2 by the partition plate 11, even in the same reaction chamber, from the portion closer to the reaction chamber 3 for the n layer to the portion closer to the reaction chamber 1 for the p layer. It is shown that the composition of the reaction gas in the plasma atmosphere has a constant spatial distribution.

【図面の簡単な説明】[Brief description of drawings]

第1図は実施例の非晶質シリコン太陽電池の製造装置の
構成説明図,第2図は第1図の反応室2の仕切板11での
断面図,第3図は実施例で得られた太陽電池の特性を示
すグラフ,第4図は該実施例でのi層中のB原子分布を
示すグラフである。 1,2,3:反応室、11:仕切板 13:緩衝室、14:隙間 17:基板、22:格子電極
FIG. 1 is an explanatory view of the structure of an apparatus for manufacturing an amorphous silicon solar cell according to an embodiment, FIG. 2 is a sectional view of a partition plate 11 of a reaction chamber 2 shown in FIG. 1, and FIG. FIG. 4 is a graph showing characteristics of the solar cell, and FIG. 4 is a graph showing B atom distribution in the i layer in the example. 1,2,3: Reaction chamber, 11: Partition plate 13: Buffer chamber, 14: Gap 17: Substrate, 22: Lattice electrode

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】基板を移送しつつ化学的気相分解によるプ
ラズマ雰囲気中で基板上に所定の半導体層を形成する薄
膜半導体の製造装置に於いて、対向した放電電極の基板
入側の所定範囲の中間に放電電極と平行にプラズマ衝撃
を低下させる多孔板からなる格子電極を少なくとも基板
全巾以上に亘って設けると共に、反応ガスを遮断する仕
切板を基板搬送方向に所定間隔で放電電極面に垂直方向
に配設して、少なくともプラズマ雰囲気を基板通路等の
限られた隙間を除いて基板搬送方向にガス拡散のない複
数の区域に区画し、膜厚方向に所定の組成分布を有する
薄膜を形成するようになした反応室を有することを特徴
とする薄膜半導体の製造装置。
1. In a thin-film semiconductor manufacturing apparatus for forming a predetermined semiconductor layer on a substrate in a plasma atmosphere by chemical vapor decomposition while transferring the substrate, a predetermined range on the substrate entry side of discharge electrodes facing each other. A grid electrode made of a perforated plate that reduces the plasma impact is provided in the middle of at least the entire width of the substrate in parallel with the discharge electrode, and partition plates for blocking reaction gas are provided on the discharge electrode surface at predetermined intervals in the substrate transport direction. A thin film having a predetermined composition distribution in the film thickness direction is formed by arranging in a vertical direction and partitioning at least the plasma atmosphere into a plurality of areas where there is no gas diffusion in the substrate transport direction except for a limited gap such as a substrate passage. An apparatus for producing a thin film semiconductor, which has a reaction chamber adapted to be formed.
【請求項2】仕切板は前記隙間を除いて反応室の全断面
を遮断するように設けられている特許請求の範囲第1項
記載の薄膜半導体の製造装置。
2. The thin-film semiconductor manufacturing apparatus according to claim 1, wherein the partition plate is provided so as to block the entire cross section of the reaction chamber except the gap.
【請求項3】前記基板が可撓性の長尺の基板であり、ロ
ール・ツー・ロール方式で搬送される請求項第1項若し
くは第2項記載の薄膜半導体の製造装置。
3. The thin-film semiconductor manufacturing apparatus according to claim 1, wherein the substrate is a flexible long substrate and is transported by a roll-to-roll method.
JP63223395A 1988-09-08 1988-09-08 Thin film semiconductor manufacturing equipment Expired - Fee Related JPH0719912B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63223395A JPH0719912B2 (en) 1988-09-08 1988-09-08 Thin film semiconductor manufacturing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63223395A JPH0719912B2 (en) 1988-09-08 1988-09-08 Thin film semiconductor manufacturing equipment

Publications (2)

Publication Number Publication Date
JPH0272677A JPH0272677A (en) 1990-03-12
JPH0719912B2 true JPH0719912B2 (en) 1995-03-06

Family

ID=16797474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63223395A Expired - Fee Related JPH0719912B2 (en) 1988-09-08 1988-09-08 Thin film semiconductor manufacturing equipment

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Country Link
JP (1) JPH0719912B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5273911A (en) * 1991-03-07 1993-12-28 Mitsubishi Denki Kabushiki Kaisha Method of producing a thin-film solar cell

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JPH0272677A (en) 1990-03-12

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