JPH07201533A - Chip part - Google Patents
Chip partInfo
- Publication number
- JPH07201533A JPH07201533A JP1315794A JP1315794A JPH07201533A JP H07201533 A JPH07201533 A JP H07201533A JP 1315794 A JP1315794 A JP 1315794A JP 1315794 A JP1315794 A JP 1315794A JP H07201533 A JPH07201533 A JP H07201533A
- Authority
- JP
- Japan
- Prior art keywords
- exposed
- end faces
- cut
- pieces
- stick
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011521 glass Substances 0.000 claims abstract description 21
- 239000000919 ceramic Substances 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000004593 Epoxy Substances 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229920005989 resin Polymers 0.000 claims description 16
- 239000011347 resin Substances 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 238000000576 coating method Methods 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 6
- 238000005520 cutting process Methods 0.000 claims description 4
- 238000000465 moulding Methods 0.000 claims description 4
- 238000010304 firing Methods 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 abstract description 5
- 229910052745 lead Inorganic materials 0.000 abstract description 5
- 229920002050 silicone resin Polymers 0.000 abstract description 5
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 abstract description 4
- 239000003822 epoxy resin Substances 0.000 abstract description 4
- 229910001120 nichrome Inorganic materials 0.000 abstract description 4
- 229920000647 polyepoxide Polymers 0.000 abstract description 4
- 230000008020 evaporation Effects 0.000 abstract 3
- 238000001704 evaporation Methods 0.000 abstract 3
- 238000007747 plating Methods 0.000 description 11
- 239000002184 metal Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 238000000151 deposition Methods 0.000 description 6
- 238000007740 vapor deposition Methods 0.000 description 5
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 4
- 229910052801 chlorine Inorganic materials 0.000 description 4
- 239000000460 chlorine Substances 0.000 description 4
- 239000007772 electrode material Substances 0.000 description 4
- 230000004907 flux Effects 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 230000002542 deteriorative effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Landscapes
- Details Of Resistors (AREA)
- Thermistors And Varistors (AREA)
Abstract
Description
【発明の詳細な説明】(段落ごとに、段落番号を付します。)
【0001】
【産業上の利用分野】本発明は電気機器、電子機器で発
生する異常高電圧、ノイズ、静電気などから機器の半導
体及び回路を保護するためのバリスタに関するものであ
る。
【0002】
【従来の技術】近年の電子機器は、信頼性向上等を目的
とした素子が広く使用されている。従来、素子は例えば
形成された積層セラミックバリスタ未焼成シ−トに内部
電極シ−トを交互に露出するように積層、焼成し、更に
内部電極が露出した両端部に金属ペースト等を塗布、焼
付けによる方式と素子の該両端部に金属ペースト等を塗
布、焼付け後、更に該両端部の上層にメッキする方式が
提案されている。
【0003】
【発明が解決しようとする課題】しかしながら、上記の
ような従来の素子の両端部に金属ぺ−スト等を塗布し、
焼き付け後、外部電極を形成する方式や素子の該両端部
に金属ペースト等を塗布、焼付け後、更に該両端部の上
層にメッキする方式では外部電極面以外は素子自体が露
出する為、はんだ付け時に生じるフラックスの悪影響、
例えば塩素成分による素子自体の還元や漏れ電流の増
加、及び絶縁性の低下を引き起こしてしまう。
【0004】また、メッキ時に使用するメッキ液が金属
ペースト等の電極材から素子に浸透する現象が生じる。
これはメッキ層を形成する際に、金属ペースト等の電極
材からメッキ液が浸入し、何らかの反応で素子本体と金
属ペースト状の電極材の境界面を破壊しているものと考
えられる。このような現象が生じることにより、素子本
体と金属ペースト状の電極材の密着性が悪化したり外部
から環境上の悪影響を受け易くなるため、耐湿性を含む
長期寿命等の環境特性の評価において近年の電子機器の
高信頼性への品質の要求に及ばないものになってしまう
危険性を含んでいる。
【0005】
【課題を解決するための手段】上記の欠点を解決するた
めに本発明は、積層セラミックバリスタの未焼成シート
と内部電極シートを積層し、該内部電極が両端面に露出
するようにスティック状に切断後焼成し、該内部電極が
露出した端面を除いてエポキシ、シリコン樹脂、ガラス
等でのモ−ルドやオ−バ−コ−トをし、あるいは該内部
電極が両端面に露出しないようにスティック状に切断後
焼成し、エポキシ、シリコン樹脂、ガラス等でのモ−ル
ドやオ−バ−コ−トをした後、個片状に切断し該内部電
極が露出した両端部に着膜等で導電性の被膜を形成して
面実装化する。
【0006】
【作 用】積層セラミックバリスタの未焼成シートと
内部電極シートを積層し、該内部電極が端面に露出する
ようにスティック状に切断後焼成し、該内部電極が露出
した両端面を除いてエポキシ、シリコン樹脂、ガラス等
でのモ−ルドやオ−バ−コ−トをし、あるいは該内部電
極が両端面に露出しないようにスティック状に切断後焼
成し、エポキシ、シリコン樹脂、ガラス等でのモ−ルド
やオ−バ−コ−トをした後、個片状に切断し該内部電極
が露出した両端部に着膜等で導電性の被膜を形成して面
実装化するには次の理由がある。
【0007】(1)従来、外部電極面以外の素子自体が
露出している電極面と比較して、はんだ付け時に生じる
フラックス中の塩素成分による素子自体の還元や漏れ電
流の増加を防止し、絶縁性を増大させることが可能であ
る。
【0008】(2)また、メッキ工程を経ないために素
子本体にメッキ液が浸透する心配がなく、素子の特性を
低下させずに外部電極を形成でき、外部電極部を厚膜製
法から薄膜製法にすることにより電極部の厚みを大幅に
削減することによって面実装密度を上げることが可能で
ある。
【0009】(3)また、素子全体をエポキシ、シリコ
ン樹脂、ガラス等でモ−ルドやオ−バ−コ−トをしてい
るのでモ−ルドやオ−バ−コ−ト上に捺印することが可
能である。
【0010】
【実施例】図1は、本発明の概略を説明するための積層
構造図である。
【0011】図2は、図1で説明したものを該内部電極
が両端面に露出するようにスティック状に切断後焼成
し、該内部電極が露出した端面を除いてエポキシ、シリ
コン樹脂、ガラス等でのモ−ルドやオ−バ−コ−トをし
た図である。
【0012】図3は、図1で説明したものを該内部電極
が両端面に露出しないようにスティック状に切断後焼成
し、エポキシ、シリコン樹脂、ガラス等でのモ−ルドや
オ−バ−コ−トをした図である。
【0013】図4は、図2、3で説明したものを更に個
片状に切断し該内部電極が露出した両端部に着膜等で導
電性の被膜を形成した断面図である。
【0014】1は上部保護シート、2は下部保護シー
ト、3は内部電極シート、4はセラミックバリスタシー
ト、5はエポキシ、シリコン樹脂、ガラス等でのモ−ル
ドやオ−バ−コ−ト、6は外部電極着膜面、7はNiC
r等の蒸着膜、8はNi等の蒸着膜、9はSn/Pbま
たはAu等の蒸着膜である。
【0015】図1の様な条件で積層し、内部電極3が外
部電極着膜部6に露出するようにスティック状に切断後
焼成し、該内部電極3が露出した該外部電極着膜部6を
除いてエポキシ、シリコン樹脂、ガラス等でのモ−ルド
やオ−バ−コ−ト5をし、あるいは該外部電極着膜部6
が両端面に露出しないようにスティック状に切断後焼成
し、エポキシ、シリコン樹脂、ガラス等でのモ−ルドや
オ−バ−コ−ト5をした後、個片状に切断し該内部電極
3が露出した該外部電極着膜部6にNiCr等の蒸着膜
7、Ni等の蒸着膜8、Sn/PbまたはAu等の蒸着
膜9を順に着膜して外部電極を形成して面実装化する。
【0016】このように本実施例によればはんだ付け時
に生じるフラックス中の塩素成分による素子自体の還元
や漏れ電流の増加を防止し、絶縁性を増大させプリント
基板上に面実装する際の信頼性を得ることができる。ま
た、メッキ工程を経ないために素子本体にメッキ液が浸
透する心配がなく、素子の特性を低下させずに外部電極
を形成でき、外部電極部を厚膜製法から薄膜製法にする
ことにより電極部の厚みを大幅に削減することで面実装
密度を上げることが可能になる。更に、素子全体をエポ
キシ、シリコン樹脂、ガラス等でモ−ルドやオ−バ−コ
−トをしているのでモ−ルドやオ−バ−コ−ト上に捺印
することが可能である。
【0017】
【発明の効果】この発明は、以上説明したように積層セ
ラミックバリスタの未焼成シートと内部電極シートを積
層し、該内部電極が両端面に露出するようにスティック
状に切断後焼成し、該内部電極が露出した両端面を除い
てエポキシ、シリコン樹脂、ガラス等でのモ−ルドやオ
−バ−コ−トをし、あるいは該内部電極が両端面に露出
しないようにスティック状に切断後焼成し、エポキシ、
シリコン樹脂、ガラス等でのモ−ルドやオ−バ−コ−ト
をした後、個片状に切断し該内部電極が露出した両端部
に着膜等で導電性の被膜を形成して面実装化する。
【0018】そうすることによりはんだ付け時に生じる
フラックス中の塩素成分による素子自体の還元や漏れ電
流の増加を防止し、絶縁性を増大させプリント基板上に
面実装する際の信頼性を向上させるという効果が得られ
る。
【0019】また、メッキ工程を経ないために素子本体
にメッキ液が浸透する心配がなく、素子の特性を低下さ
せずに外部電極を製造でき、外部電極部を厚膜から薄膜
にすることにより電極部の厚みを大幅に削減させるとい
う効果が得られる。
【0020】その上、素子全体をエポキシ、シリコン樹
脂、ガラス等でモ−ルドやオ−バ−コ−トをしているの
でモ−ルドやオ−バ−コ−ト上に捺印する事による製品
名等の判読ができ、面実装対応が可能な事である。[Detailed Description of the Invention] (Paragraphs are numbered for each paragraph.) [0001] The present invention is applied to abnormal high voltage, noise, static electricity, etc. generated in electric equipment and electronic equipment. The present invention relates to a varistor for protecting semiconductors and circuits of equipment. 2. Description of the Related Art In recent electronic devices, elements for the purpose of improving reliability are widely used. Conventionally, an element is laminated and fired so that the internal electrode sheets are alternately exposed on the formed unfired laminated ceramic varistor sheet, and metal paste or the like is applied and baked on both ends where the internal electrodes are exposed. And a method in which a metal paste or the like is applied to both ends of the element, baked, and then plated on the upper layers of both ends. However, metal paste or the like is applied to both ends of the conventional element as described above,
In the method of forming external electrodes after baking or applying a metal paste or the like to both ends of the element, and baking and then plating the upper layer of both ends, the element itself is exposed except for the external electrode surface, so soldering The adverse effect of the flux that sometimes occurs,
For example, the chlorine component causes reduction of the element itself, increase of leakage current, and deterioration of insulation. Further, there occurs a phenomenon that the plating liquid used for plating permeates the element from the electrode material such as metal paste.
It is considered that this is because, when the plating layer is formed, the plating solution penetrates from the electrode material such as the metal paste and destroys the interface between the element body and the metal paste-like electrode material by some reaction. When such a phenomenon occurs, adhesion between the element body and the electrode material in the form of a metal paste is deteriorated or the environment is liable to be adversely affected from the outside.Therefore, in evaluation of environmental characteristics such as long life including humidity resistance. This includes the risk that the quality of electronic devices will not meet the demand for high quality in recent years. In order to solve the above-mentioned drawbacks, the present invention laminates an unfired sheet of a laminated ceramic varistor and an internal electrode sheet so that the internal electrodes are exposed on both end faces. After cutting into sticks and baking, mold or overcoat with epoxy, silicon resin, glass, etc. except for the end faces where the internal electrodes are exposed, or the internal electrodes are exposed at both end faces. So that the internal electrodes are exposed at both ends where the internal electrodes are exposed, after being cut into sticks and fired, and then molded and overcoated with epoxy, silicon resin, glass, etc. A conductive coating is formed by film deposition or the like for surface mounting. [Working] [0006] An unfired sheet of a laminated ceramic varistor and an internal electrode sheet are laminated, cut into sticks so that the internal electrodes are exposed at the end faces, and then fired to remove both end faces where the internal electrodes are exposed. Epoxy, silicone resin, glass, etc. by molding or overcoating with epoxy, silicone resin, glass, etc. For example, after conducting a molding or overcoating with etc., it is cut into individual pieces, and a conductive coating is formed on both ends where the internal electrodes are exposed by coating to form a surface mount. Has the following reasons. (1) Conventionally, compared with the electrode surface where the element itself other than the external electrode surface is exposed, reduction of the element itself and increase of leakage current due to chlorine component in the flux generated during soldering are prevented, It is possible to increase the insulating property. (2) In addition, since the plating process is not performed, there is no concern that the plating solution will penetrate into the element body, and the external electrode can be formed without deteriorating the characteristics of the element. By using the manufacturing method, it is possible to increase the surface mounting density by significantly reducing the thickness of the electrode portion. (3) Further, since the entire element is molded or overcoated with epoxy, silicon resin, glass or the like, it is imprinted on the molded or overcoat. It is possible. FIG. 1 is a laminated structure diagram for explaining the outline of the present invention. In FIG. 2, the one described in FIG. 1 is cut into sticks so that the internal electrodes are exposed at both end faces and then baked, and epoxy, silicon resin, glass, etc. are removed except for the end faces where the internal electrodes are exposed. It is the figure which carried out the mode and the overcoat in. In FIG. 3, the structure described in FIG. 1 is cut into sticks so that the internal electrodes are not exposed at both end faces, and then baked, and a mold or an overcoat made of epoxy, silicon resin, glass or the like is used. FIG. FIG. 4 is a cross-sectional view in which the one described in FIGS. 2 and 3 is further cut into individual pieces, and conductive coatings are formed on both ends where the internal electrodes are exposed by film deposition or the like. 1 is an upper protective sheet, 2 is a lower protective sheet, 3 is an internal electrode sheet, 4 is a ceramic varistor sheet, 5 is a mold or overcoat made of epoxy, silicone resin, glass or the like, 6 is the outer electrode film surface, 7 is NiC
Reference numeral 8 is a vapor deposited film of r or the like, 8 is a vapor deposited film of Ni or the like, and 9 is a vapor deposited film of Sn / Pb or Au. The layers are laminated under the conditions shown in FIG. 1, the internal electrodes 3 are cut into sticks so as to be exposed at the external electrode film deposition portion 6 and then baked, and the external electrode film deposition portion 6 where the internal electrodes 3 are exposed is baked. Excluding epoxy or silicon resin, glass or the like, and an overcoat 5, or the external electrode film forming portion 6
Are cut into sticks so as not to be exposed at both end faces, then baked, and molded with epoxy, silicon resin, glass, etc. or overcoat 5, and then cut into individual pieces to form the internal electrodes. Surface-mounting by depositing a vapor deposition film 7 of NiCr or the like, a vapor deposition film 8 of Ni or the like, a vapor deposition film 9 of Sn / Pb or Au on the external electrode deposition film portion 6 where 3 is exposed to form external electrodes. Turn into. As described above, according to the present embodiment, the reduction of the element itself and the increase of the leakage current due to the chlorine component in the flux generated at the time of soldering are prevented, the insulation property is increased, and the reliability in the surface mounting on the printed board is improved. You can get sex. In addition, since there is no need to go through the plating process, there is no concern that the plating solution will penetrate into the element body, and external electrodes can be formed without deteriorating the characteristics of the element. It is possible to increase the surface mounting density by significantly reducing the thickness of the part. Furthermore, since the entire element is molded or overcoated with epoxy, silicon resin, glass or the like, it is possible to imprint on the molded or overcoat. As described above, according to the present invention, the unfired sheet of the laminated ceramic varistor and the internal electrode sheet are laminated, and the internal electrode is cut into sticks so as to be exposed at both end faces and then fired. , Excluding both end surfaces where the internal electrodes are exposed, mold or overcoat with epoxy, silicon resin, glass or the like, or make a stick so that the internal electrodes are not exposed at both end surfaces. After cutting, bake, epoxy,
After molding or overcoating with silicon resin, glass, etc., it is cut into individual pieces, and a conductive coating film is formed on both ends where the internal electrodes are exposed by coating to form a surface. Implement. By doing so, it is possible to prevent the reduction of the element itself and the increase of the leakage current due to the chlorine component in the flux generated at the time of soldering, to increase the insulation property and to improve the reliability of the surface mounting on the printed circuit board. The effect is obtained. Further, since the plating process is not performed, there is no concern that the plating solution will penetrate into the element body, and the external electrode can be manufactured without deteriorating the characteristics of the element. The effect of significantly reducing the thickness of the electrode portion can be obtained. In addition, since the entire device is molded or overcoated with epoxy, silicon resin, glass or the like, it is possible to stamp on the molded product or overcoat. It is possible to read the product name, etc. and support surface mounting.
【図面の簡単な説明】
【図1】本発明の概略を説明するための積層構造図であ
る。
【図2】図1で説明したものを該内部電極が両端面に露
出するようにスティック状に切断後焼成し、該内部電極
が露出した両端面を除いてエポキシ、シリコン樹脂、ガ
ラス等でのモ−ルドやオ−バ−コ−トをした斜視図であ
る。
【図3】図1で説明したものを該内部電極が両端面に露
出しないようにスティック状に切断後焼成し、エポキ
シ、シリコン樹脂、ガラス等でのモ−ルドやオ−バ−コ
−トをした斜視図である。
【図4】図2、3で説明したものを更に個片状に切断し
該内部電極が露出した両端部にNiCr等の蒸着膜、N
i等の蒸着膜、Sn/PbまたはAu等の蒸着膜を順に
着膜した断面図である。
【符号の説明】
1 上部保護シート
2 下部保護シート
3 内部電極シート
4 セラミックバリスタシート
5 エポキシ、シリコン樹脂、ガラス等でのモ−ルドや
オ−バ−コ−ト
6 外部電極着膜面
7 NiCr等の蒸着膜
8 Ni等の蒸着膜
9 Sn/PbまたはAu等の蒸着膜BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a laminated structure diagram for explaining the outline of the present invention. FIG. 2 is a sectional view of the structure described with reference to FIG. 1, cut into sticks so that the internal electrodes are exposed at both end faces, and then baked, and epoxy resin, silicon resin, glass, etc. are removed except for the both end faces where the internal electrodes are exposed. FIG. 3 is a perspective view showing a mold and an overcoat. FIG. 3 is the same as that described with reference to FIG. 1, cut into sticks so that the internal electrodes are not exposed at both end faces, and then baked, and a mold or overcoat made of epoxy, silicon resin, glass or the like is used. FIG. FIG. 4 is a plan view of the structure shown in FIGS. 2 and 3, further cut into individual pieces, and a vapor-deposited film of NiCr or the like, N
It is sectional drawing which deposited the vapor deposition film of i etc. and the vapor deposition film of Sn / Pb or Au in order. [Explanation of reference numerals] 1 upper protective sheet 2 lower protective sheet 3 internal electrode sheet 4 ceramic varistor sheet 5 mold and overcoat with epoxy, silicon resin, glass, etc. 6 external electrode film-coated surface 7 NiCr Vapor deposited film 8 etc. Vapor deposited film 9 Ni etc. Vapor deposited film Sn / Pb or Au etc.
Claims (1)
う)の電極を形成する方法で積層セラミックバリスタの
未焼成シートと内部電極シートを積層し、該内部電極が
両端面に露出するようにスティック状に切断後焼成し、
該内部電極が露出した両端面を除いてエポキシ、シリコ
ン樹脂、ガラス等でのモ−ルドやオ−バ−コ−トをした
後、個片状に切断し該内部電極が露出した両端部に着膜
等で導電性の被膜を形成し、面実装化することを特徴と
するチップ部品。 【請求項2】 素子の電極を形成する方法で積層セラミ
ックバリスタの未焼成シートと内部電極シートを積層
し、該内部電極が両端面に露出しないようにスティック
状に切断後焼成し、エポキシ、シリコン樹脂、ガラス等
でのモ−ルドやオ−バ−コ−トをした後、個片状に切断
し着膜等で導電性の被膜を形成し、面実装化することを
特徴とするチップ部品。 (1)発明の構成に欠くことができない事項のみを記載し
た項(請求項)に区分して記載します。 (2)請求項ごとに行を改め、1の番号を付します(請求
項の数が1の場合でも、「 【請求項1】」と記載します。また、2以上の場合は「 【請求項1】」、「 【請求項2】」のように連続番号とします。)Claim: What is claimed is: 1. An unfired sheet of a laminated ceramic varistor and an internal electrode sheet are laminated by a method of forming electrodes of a chip varistor body (hereinafter referred to as an element), and the internal electrodes are exposed on both end faces. After cutting it into sticks and firing,
After excluding both end surfaces where the internal electrodes are exposed, a mold or an overcoat with epoxy, silicon resin, glass, etc. is performed, and then the pieces are cut into individual pieces to expose the internal electrodes at both ends. A chip component characterized in that a conductive coating is formed by film deposition and the like to be surface-mounted. 2. An unfired sheet of a laminated ceramic varistor and an internal electrode sheet are laminated by a method of forming an electrode of an element, cut into sticks so that the internal electrodes are not exposed at both end faces, and then fired to obtain epoxy or silicon. A chip component characterized by molding or overcoating with resin, glass, etc., then cutting it into individual pieces, forming a conductive coating with a film, etc., for surface mounting . (1) The items shall be divided into the items (claims) that describe only the items that are essential to the composition of the invention. (2) Change the line for each claim and add a number of 1 (even if the number of claims is 1, it is described as "[Claim 1]". If it is 2 or more, "[ Serial numbers such as "Claim 1]" and "[Claim 2]".)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1315794A JPH07201533A (en) | 1994-01-11 | 1994-01-11 | Chip part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1315794A JPH07201533A (en) | 1994-01-11 | 1994-01-11 | Chip part |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07201533A true JPH07201533A (en) | 1995-08-04 |
Family
ID=11825343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1315794A Pending JPH07201533A (en) | 1994-01-11 | 1994-01-11 | Chip part |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07201533A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997027598A1 (en) * | 1996-01-24 | 1997-07-31 | Matsushita Electric Industrial Co., Ltd. | Electronic parts and method for manufacturing the same |
| WO1999053504A1 (en) * | 1998-04-09 | 1999-10-21 | Matsushita Electric Industrial Co., Ltd. | Ptc thermistor chip |
-
1994
- 1994-01-11 JP JP1315794A patent/JPH07201533A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997027598A1 (en) * | 1996-01-24 | 1997-07-31 | Matsushita Electric Industrial Co., Ltd. | Electronic parts and method for manufacturing the same |
| US6171644B1 (en) | 1996-01-24 | 2001-01-09 | Matsushita Electric Industrial Co., Ltd. | Electronic component and method of manufacture therefor |
| US6400253B1 (en) | 1996-01-24 | 2002-06-04 | Matsushita Electric Industrial Co., Ltd. | Electronic component and method of manufacture therefor |
| WO1999053504A1 (en) * | 1998-04-09 | 1999-10-21 | Matsushita Electric Industrial Co., Ltd. | Ptc thermistor chip |
| US6441717B1 (en) | 1998-04-09 | 2002-08-27 | Matsushita Electric Industrial Co., Ltd. | PTC thermister chip |
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