JPH0720291B2 - Remote monitoring controller - Google Patents

Description

TECHNICAL FIELD The present invention relates to a remote supervisory control device that accesses a terminal from a central control device to transmit control data and supervisory data by time division multiplexing.

[Prior Art] Conventionally, as shown in FIG. 11, a remote supervisory control device of this type, in which control data and supervisory data are transmitted in a time division multiplex by accessing a terminal device from a central control device, is ,
A plurality of monitoring terminals 2 for setting the unique addresses and monitoring the operation switches S _{1 to} S ₄ and a plurality of control terminals 3 for controlling the loads L _{1 to} L ₄ are connected by a pair of signal lines 4. And
Transmission signal Va sent from the central controller 1 to the signal line 4
Is a start pulse signal ST indicating the start of signal transmission, a mode data signal MD indicating the signal mode, and an address data signal for transmitting 8-bit address data for calling the terminals 2 and 3, as shown in FIG. 12 (a). AD, a control data signal CD that transmits control data for controlling the loads L _{1 to} L ₄ , a checksum data signal CS, and a multi-pole (±) consisting of a return standby signal WT that sets the signal return period from the terminals 2 and 3. 24V) time division multiplexed signal, and data is transmitted by pulse width modulation. In each of the terminals 2 and 3, the transmission signal Va received through the signal line 4 is rectified and smoothed to form a terminal circuit power supply, and the power of each terminal circuit is supplied through the signal line 4 to the central control unit 1 I am trying to supply from. In addition, in each of the terminals 2 and 3, the control data of the transmission signal Va when the address data transmitted by the transmission signal Va and its own unique address data match are taken in, and the return standby signal WT of the transmission signal Va is received. To send back a monitoring data signal (operation switch operating status monitoring information, load operating status information, etc.) as a current mode signal (a signal sent by connecting an appropriate low resistance between the signal lines 4). It has become. The central control device 1 is shown in FIG. 12 (b), which is a dummy signal signal means for constantly transmitting the dummy transmission signal Va in which the mode data signal MD is in the dummy mode, and one of the monitoring terminals 2 returned. When the interrupt signal Vi is received, an interrupt processing unit for detecting the interrupt-generating terminal device 2, accessing the terminal device 2 and returning the monitoring data is provided. Further, in the central controller 1, the corresponding loads L _{1 to} L ₄ are set based on the operation state information of the operation switches S _{1 to} S ₄ returned from the monitoring terminal 2 to the central controller 1 as described above. Control data to be transmitted to the control terminal device 3 to be controlled is created, and the control data is time-division multiplexed to the control terminal device 3 via the signal line 4 to control the loads L _{1 to} L ₄ , load L ₁ ~L ₄ operating state information monitoring terminal unit 2 of the operation indicator lamp La on the basis of, so as to transmit the control data for lighting control of Lb.

FIG. 13 shows a main circuit configuration of the monitoring and controlling terminals 2 and 3, which includes a diode bridge DB for rectifying the transmission signal Va transmitted through the signal line 4, a diode D ₁ , and a resistor Ra.
And a power supply circuit 11 including a capacitor C ₂ and a transmission signal Va
Terminal circuit 12 including a logic circuit for performing signal processing of the signal, the signal processing of return signal Vb, and the like, resistors Rb, Rc, and transistor Q
_And a return circuit 13 of ₁ . Here, the return signal Vb sent from the terminals 2 and 3 to the signal line 4 has a low resistance value by appropriately turning on the transistor Q ₁ by the return data output from the terminal circuit 12 during the return standby signal WT. The current mode signal is obtained by connecting the resistance Rc of the above circuit between the signal lines 4 and increasing the current flowing through the signal line 4.

FIG. 14 shows a return signal detection circuit 15 provided in the central control unit 1, which includes a current detection resistor R ₀ which is inserted in the signal line 4 and detects a current I flowing in the signal line 4, and a current detection resistor R ₀ . Current detection voltage V _I which is the voltage across detection resistor R ₀ and reference voltage
Comparator that detects current mode signal by comparing with Vs
It is formed by CP and the voltage obtained by integrating the divided voltage of the current detection voltage V _I by resistors R ₁ and R _{2 in the} CR time constant circuit consisting of capacitor C ₁ and resistor R ₃ is zener diode ZD. The return signal detection circuit 15 is formed so that the voltage obtained by adding the constant voltage set in 1 is used as the reference voltage Vs of the comparator CP and the current detection voltage V _I is used as the comparison voltage.

Here, in the above-mentioned conventional example, the current detection voltage V _I detected by the current detection resistor R ₀ and the voltage formed by the resistors R ₁ and R ₂ and the zener diode ZD are compared to the capacitor C ₁ and the resistor. When the current detection voltage V _I becomes larger than the reference voltage Vs held in the capacitor C ₁ by applying it to the time constant circuit composed of R ₃ with a predetermined delay, the comparator CP output goes to “H”. As a result, the current mode signal detection signal V ₀ is output.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional example, when the pulse width of the current mode signal is larger than the time constant of the time constant circuit, the voltage across the capacitor C ₁ , that is, the reference voltage Vs. However, there was a problem that the current mode signal could not be detected. Further, even when the number of pulses of the current mode signal is large, there is a problem that the reference voltage Vs rises and the detection accuracy deteriorates. Furthermore, current fluctuations other than current mode signals (changes in load current flowing in the terminal circuit)
There is a problem in that an erroneous current detection signal is output.

The present invention has been made in view of the above points, and an object of the present invention is to provide a remote monitoring control device capable of reliably detecting a current mode signal returned from a terminal device.

[Means for Solving the Problems] In the remote monitoring control device according to claim 1 of the present invention, the central control device and a plurality of terminals are connected by a pair of signal lines, and each terminal device is accessed from the central control device. Control signal and a return standby signal for setting the return period are transmitted, and the terminal device is rectified and smoothed to form a terminal circuit power supply, and a low resistance is connected to the signal line within the return standby signal period. The current-mode return signal obtained by the above is returned to the central control unit, and the current-mode signal is detected by comparing the current detection voltage consisting of the voltage across the current detection resistor inserted in the signal line with the reference voltage. In a remote monitoring controller with a return signal detection circuit in the central controller, add the constant voltage set by the Zener diode to the voltage obtained by integrating the divided voltage of the current detection voltage with the CR time constant circuit. Voltage to form a return signal detection circuit as a reference voltage is obtained by the divided voltage via a switch means which is turned off upon detection of a current mode signal to be applied to the CR time constant circuit.

According to a second aspect of the present invention, a pulse width detection circuit for detecting whether the pulse width of the detection signal of the current mode signal is a predetermined value or more is provided, and the switch means is turned on when the pulse width is a predetermined value or more. It is the one.

Furthermore, in the third aspect of the present invention, the current detection voltage is applied to the capacitor of the CR time constant circuit via the bypass resistor, and the capacitor is minutely charged via the bypass resistor.

Still further, according to a fourth aspect of the present invention, a plurality of return signal detection circuits having different detection levels are provided, and the peak value of the current mode signal is determined by the output of each return signal detection circuit.

Still further, according to claim 5, the switch means is turned on during the non-reception period of the current mode signal by the signal synchronized with the transmission signal.

[Operation] The present invention is configured as described above, and the return signal detection circuit for detecting the current mode signal by comparing the current detection voltage composed of the voltage across the current detection resistor inserted in the signal line with the reference voltage. In the remote monitoring control device provided in the central control device, the voltage obtained by integrating the divided current of the current detection voltage with the CR time constant circuit is added to the constant voltage set by the Zener diode, which is the reference Since the return signal detection circuit is formed to have a voltage and the divided voltage is applied to the CR time constant circuit via the switch means that is turned off when the current mode signal is detected, it flows through the signal line. Even if the current fluctuates, the current mode signal returned from the terminal can be reliably detected.

According to a second aspect of the present invention, a pulse width detection circuit for detecting whether or not the pulse width of the detection signal of the current mode signal is equal to or larger than a predetermined value is provided, and the switch means is turned on when the pulse width is equal to or larger than the predetermined value. Then, the reference voltage is updated to automatically release the lock state of the return signal detection circuit when the current consumption of the terminal device increases and the current flowing through the signal line changes significantly.

Furthermore, in the third aspect of the present invention, the current detection voltage is applied to the capacitor of the CR time constant circuit via the bypass resistor, and the capacitor is minutely charged via the pulse resistor to lock the return signal detection circuit. Can be automatically released after a certain period of time.

Still further, according to claim 4, a plurality of return signal detection circuits having different detection levels are provided, and the peak value of the current mode signal is determined by the output of each return signal detection circuit, so that the detected current level can be easily adjusted. I am trying to understand.

Still further, according to a fifth aspect of the present invention, the reference voltage is periodically updated by turning on the switch means during the non-reception period of the current mode signal by the signal synchronized with the transmission signal. The locked state can be released automatically.

[Embodiment] FIG. 1 shows an embodiment of the present invention. Like the conventional example, the current detection voltage V _I for detecting the current I flowing through the signal line 4 is shown.
Voltage divided by resistors R ₁ and R ₂ of capacitor C ₁ and resistor R
_The return signal detection circuit 15 is formed so that the reference voltage Vs is the voltage obtained by adding the constant voltage set by the Zener diode ZD to the voltage obtained by integration in the CR time constant circuit consisting of ₃ and the current mode signal. The divided voltage is applied to the CR time constant circuit via the switch means composed of the analog switch AS that is turned off at the time of detection (the output of the comparator CP is "H").

The operation of the embodiment will be described below. FIG. 2 is a diagram for explaining the operation of the embodiment, in which the analog switch AS of the return signal detection circuit 15 detects the current mode signal and the comparator.
It is turned on when the CP output becomes “H”, and the current detection voltage V _I
The divided voltage of is cut off to the CR time constant circuit until the output of the comparator CP becomes “L”. Therefore, the reference voltage Vs, which is the voltage across the capacitor C ₁ , is held at the value immediately before the current mode signal is detected (the value corresponding to the base current of the current I flowing through the signal line 4), and the current mode signal is detected. Since the reference voltage Vs does not fluctuate, the current mode signal can be reliably detected even when the pulse width is long and the number of pulses is large. Also, without considering the pulse width and the number of pulses of the current mode signal,
Since the delay time of the time constant circuit can be set short, it is possible to quickly follow the fluctuation of the base current.

In addition, the CR time constant circuit (capacitor
By setting the time constant of C ₁ and resistance R ₃ ) to the detection delay time or longer, the fluctuation of the reference voltage Vs can be reduced even if the time until the analog switch AS turns off after detection varies. Since it is not necessary to use the restraining element as the detection processing circuit, the cost can be reduced.

FIG. 3 shows still another embodiment, which is provided with a pulse width detection circuit PW for detecting whether the pulse width of the detection signal V ₀ of the current mode signal is a predetermined value or more, and when the pulse width is a predetermined value or more. The analog switch AS is turned on. In the embodiment, the logical sum of the output of the comparator CP and the output of the pulse width detection circuit PW is calculated by the OR circuit OR, and the analog switch AS is controlled by the output of the OR circuit OR.

FIG. 4 is a diagram for explaining the operation of the embodiment described above. Now, in the normal operating state, the detection signal V ₀ is the same as in the embodiment of FIG.
Is “L”, the analog switch AS is turned off to prevent the reference voltage Vs from changing, and when the detection signal V ₀ is “H”, the analog switch AS is turned on and the reference voltage Vs becomes the base current. It is designed to change accordingly. On the other hand, terminal
When the current flowing through the signal line 4 increases as shown in FIG. 4 (a) due to a sudden increase in the consumption current of 2, 3 and the like, and this change in current is detected by the return signal detection circuit 15, the analog switch AS is turned off. The output of the comparator CP remains “L”
Therefore, there is a problem that the current mode signal cannot be detected thereafter. Therefore, in the present embodiment, the pulse width detection circuit PW is provided to detect the locked state, and the analog switch AS is forcibly turned on to release the locked state. That is, when the “L” period of the detection signal V ₀ output from the comparator CP is equal to or larger than the pulse width of the current mode signal of the normal return signal Vb, the pulse width detection circuit PW output becomes “H” and long. The pulse detection signal Vp is output, the analog switch AS is turned on to update the reference voltage Vs, and the return signal detection circuit 15 can be automatically restored from the locked state.

FIG. 5 shows another embodiment, in which the capacitor C ₁ of the CR time constant circuit is connected to the current detection voltage via the bypass resistor R _4.
The V _I is applied, the capacitor C ₁ via the bypass resistor R ₄
It is designed to be charged minutely. The resistance value of the bypass resistor R ₄ is set so that a minute charging current that does not interfere with the detection operation of the normal current mode signal flows.

Now, as the current consumption of the terminals 2 and 3 increases, the current flowing through the signal line 4 fluctuates as shown in FIG. 6 (a), and the analog switch AS of the return signal detection circuit 15 remains off. In the locked state, the capacitor C ₁ of the time constant circuit is designed to be minutely charged via the bypass resistor R ₄ , so the voltage across the capacitor C ₁ gradually rises according to the base current, When the reference voltage Vs becomes equal to or higher than the current detection voltage V _I , the output of the comparator CP becomes “H”, the analog switch AS is turned on, and the locked state can be released. After that, since the reference voltage Vs is updated according to the base current of the current detection voltage V _I , the normal detection operation is performed.

By the way, in order to surely perform the detection operation of the return signal detection circuit 15 in the embodiment of FIG. 1 (to prevent the locked state), the time constant of the smoothing circuit of the terminal power supply circuit 11 of the terminals 2 and 3 and The time constant of the return signal detection circuit is set appropriately, and fluctuations in the current consumption of the terminals 2 and 3 are adjusted to the return signal detection circuit 1
The delay may be set to be slower than the delay of 5, and the reference voltage Vs may be changed following the fluctuation of the consumption current.

FIG. 7 shows still another embodiment, in which a plurality of return signal detection circuits 15 ₁ , 15 ₂ ... 15n having different detection levels are provided, and each return signal detection circuit 15 ₁ , 15 ₂ ... 15n is provided. The peak value of the current mode signal is determined by the output detection signals V ₀₁ , V ₀₂ ... V ₀ n. In the embodiment, the resistance R ₁₁ ,
The reference voltages Vs ₁ , Vs ₂ ... Vsn that set the detection level by changing the resistance value of R ₁₂ ... R ₁ n have different values.

FIG. 8 shows the operation of the above-described embodiment. Now, when the current detection voltage V _I as shown in FIG. 8 (a) is obtained, the peak value is slightly larger than the reference voltage Vs _3. (However, Vs ₄
Since falls below), the detection signal V ₀₁ ~V ₀₃ from return signal detecting circuit 15 ₁ to 15 ₃ are output, the detection signal V ₀₁ ~V ₀₃
The pulse peak value of the current mode signal can be determined based on For example, it is possible to grasp the tendency of the change in the detected current level and issue an alarm immediately before the detection becomes impossible, or to display a margin of the detected current level.

FIG. 9 shows still another embodiment, in which the analog switch AS serving as the switch means is turned on during the non-reception period of the current mode signal by the signal synchronized with the transmission signal Va. In order to turn on the analog switch AS by the gate signal V _G consisting of a pulse signal as shown in FIG. 10 synchronized with the start signal ST (start 1 section) of the transmission signal Va and the return standby signal WT. Current mode detection signal V ₀ and gate signal V _G
The OR circuit OR is used to calculate the logical OR of the analog circuit AS, and the OR switch OR output Vc is used to control the ON / OFF of the analog switch AS.

Even if the current I flowing through the signal line 4 fluctuates significantly and the return signal detection circuit 15 is locked, the gate signal V _G causes the analog switch AS to cyclically (receive the transmission signal Va). Since it is turned on each time the current mode signal is received, the lock state is not maintained and the current mode signal cannot be received.

EFFECTS OF THE INVENTION The present invention is configured as described above, and a return signal for detecting a current mode signal by comparing a current detection voltage composed of a voltage across a current detection resistor inserted in a signal line with a reference voltage. In the remote monitoring control device with the detection circuit provided in the central control device, the voltage obtained by adding the constant voltage set by the Zener diode to the voltage obtained by integrating the divided voltage of the current detection voltage in the CR time constant circuit Since the return signal detection circuit is formed to use as the reference voltage and the divided voltage is applied to the CR time constant circuit via the switch means that is turned off when the current mode signal is detected, it is possible to use the signal line. Even if the flowing current fluctuates, the current mode signal returned from the terminal device can be reliably detected.

In addition, a pulse width detection circuit for detecting whether the pulse width of the detection signal of the current mode signal is a predetermined value or more is provided, and when the pulse width is a predetermined value or more, the switch means is turned on to update the reference voltage. For example, the lock state of the return signal detection circuit can be automatically released when the current consumption of the terminal device increases and the current flowing through the signal line changes significantly.

Furthermore, if the current detection voltage is applied to the capacitor of the CR time constant circuit via the bypass resistor and the capacitor is minutely charged via the bypass resistor, the lock state of the return signal detection circuit is automatically set after a certain time. Can be canceled automatically.

Furthermore, if a plurality of return signal detection circuits having different detection levels are provided and the peak value of the current mode signal is determined by the output of each return signal detection circuit, the detected current level can be easily grasped.

Furthermore, if the reference voltage is periodically updated by turning on the switch means during the non-reception period of the current mode signal by the signal synchronized with the transmission signal, the lock state of the return signal detection circuit is automatically set. Can be canceled.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an essential part of an embodiment of the present invention, FIG. 2 is an operation explanatory diagram of the same as above, FIG. 3 is a circuit diagram of an essential part of another embodiment, and FIG. FIG. 5 is a circuit diagram of main parts of still another embodiment, FIG. 6 is an operation explanatory diagram of the same as above, FIG. 7 is a circuit diagram of main parts of still another embodiment, and FIG. FIG. 9 is a circuit diagram of a main part of still another embodiment, FIG. 10 is an operation explanatory diagram of the same as above, FIG. 11 is a schematic configuration diagram of a conventional example, FIG. 12 is an operation explanatory diagram of the same as above, and FIG. FIG. 14 is a main part circuit diagram of FIG. 1 the central control unit, 2 and 3 terminal unit, 4 denotes a signal line, 11 is a terminal circuit, 12 is returned circuits, 15, 15 ₁ ～15N the return signal detection circuit, R ₀ to R ₃ are resistors, C ₁ Is a capacitor, ZD is a zener diode, CP is a comparator, and PW is a pulse width detection circuit.

Claims (5)

[Claims] 1. A central control device and a plurality of terminals are connected by a pair of signal lines, and each terminal device is accessed from the central control device to transmit control data and a return standby signal for setting a return period, To rectify and smooth the above transmission signal in the terminal device to form the terminal circuit power supply, and to return the current mode return signal obtained by connecting the low resistance to the signal line within the return standby signal period to the central control unit. In the remote monitoring control device, the return signal detection circuit for detecting the current mode signal by comparing the current detection voltage consisting of the voltage across the current detection resistor inserted in the signal line with the reference voltage is provided in the central control device. Form the return signal detection circuit so that the reference voltage is the voltage obtained by adding the constant voltage set by the Zener diode to the voltage obtained by integrating the divided voltage of the current detection voltage with the CR time constant circuit. Remote monitoring and control device, characterized in that a divided voltage through the switch means is turned off was set to be applied to the CR time constant circuit upon detection of a current mode signal. 2. A pulse width detection circuit for detecting whether or not the pulse width of the detection signal of the current mode signal is not less than a predetermined value,
2. The remote monitoring control device according to claim 1, wherein the switch means is turned on when the pulse width is equal to or larger than a predetermined value. 3. The remote monitoring according to claim 1, wherein a current detection voltage is applied to the capacitor of the CR time constant circuit via a bypass resistor, and the capacitor is minutely charged via the bypass resistor. Control device. 4. The remote according to claim 1, wherein a plurality of return signal detection circuits having different detection levels are provided, and the peak value of the current mode signal is determined by the output of each return signal detection circuit. Monitoring and control equipment. 5. The remote monitoring control apparatus according to claim 1, wherein the switch means is turned on during a non-reception period of the current mode signal by a signal synchronized with the transmission signal.