JPH0721624B2 - Reticle for semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a reticle for semiconductor integrated circuits, and particularly to a blank portion existing around an integrated circuit pattern.

[Conventional technology]

Conventionally, the semiconductor substrate cutting margin (hereinafter referred to as a scribe line) existing in the peripheral portion of the circuit pattern of the reticle for semiconductor integrated circuit has been mainly taken by the following method. The related art will be described below with reference to the drawings.

FIG. 3 shows one chip of a reticle for a semiconductor integrated circuit. In the vicinity of the center 301 of the glass plate, there are a region 302 in which a pattern for an integrated circuit is drawn and a scribe region 303 around it. This scribe line width is usually about 250 microns in the case of a 1/5 reduction projection exposure reticle. When exposure is performed by a reduction projection exposure apparatus using this reticle, the left end 304 and the right end 305 of the scribe line cover the range of repeated exposure.
And repeated exposure so that the upper end 306 overlaps the lower end 307. The arrangement on the semiconductor substrate thus exposed is as shown in FIG. Now, assuming that the scribe line width in FIG. 3 is 250 microns, it is reduced to 1/5 on the semiconductor substrate, resulting in 50 microns, and since they are adjacent to each other, it is 100 microns on the semiconductor substrate. It becomes the scribe line.

Next, there is also a method as shown in FIG. Similar to FIG. 4, the circuit pattern area 402 is near the center 401 of the glass plate.
A scribe area 403 exists around it. In this case, the scribe line width is 500 μm, and the repeated exposure is performed so that the left edge 404 and the right edge 405 of the pattern area and the upper edge 406 and the lower edge 407 of the pattern area overlap. As a result, the arrangement on the semiconductor substrate is as shown in FIG. Therefore, the examples of FIGS. 3 and 5 result in the same.

[Problems to be Solved by the Invention]

The above-mentioned conventional technique has a fatal defect as described below. First, in the example shown in FIG. 3, the scribe line has a width of 100 μm on the semiconductor substrate, but since the width is substantially half that, effective use of the scribe line is limited. In other words, it is unnecessary for circuit operation,
Indispensable patterns, such as overlay marks, overlay inspection marks, inspection elements, etc., are generally placed on the scribe lines, and therefore these patterns must be placed on half of the scribe lines. I won't. Even if it is attempted to use the full width of the scribe line, the pattern may not be completely connected due to the repeated error on the left and right sides or the top and bottom sides, and it cannot be used.

On the other hand, in the example shown in FIG. 5, the full width of the scribe line can be used, but since double exposure is performed on the semiconductor substrate, when the inspection pattern is put in one side, the other scribe line corresponding to the position is It must be shielded from exposure. In any case, the reticle pattern layout design becomes a heavy burden, and a great deal of labor is required to establish a check function and system to prevent errors. Moreover, the occurrence of mistakes is not inevitable, and in that case, the loss due to delay in development and research, delay in product shipment, etc. is immeasurable.

[Means for Solving the Problems]

The reticle for semiconductor integrated circuit of the present invention is composed of an integrated circuit pattern and a blank portion for cutting the semiconductor substrate existing around the integrated circuit pattern. The blank portion exists only in two directions around the integrated circuit pattern, and It is configured by the two extra days being in two directions adjacent to each other.

In contrast to the conventional semiconductor integrated circuit reticle, the present invention arranges the scribe lines only in the two adjacent directions of the circuit pattern so that the full width of the scribe line can be effectively used without special measures such as light shielding. There is.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a diagram for explaining the first embodiment of the present invention. There is a center 103 of a circuit pattern range 102 apart from the center 101 of the glass plate that is the substrate of the reticle, and margins 103 for scribing are provided at the right and upper ends of the circuit pattern range 102.
Is provided at 500 microns. Therefore, when transferred to a semiconductor substrate with a 1/5 reduction projection exposure apparatus, this scribe line is 100
The size becomes micron, and the ones arranged by repeated exposure are the same as those in FIG. According to this example, the scribe line
It is possible to effectively use a mark for overlaying the entire width of 500 microns and various other inspection patterns. Moreover, since the scribe line is exposed only once, there is no harm such as double exposure as in the conventional method.

FIG. 2 is a diagram of a second embodiment of the present invention. In this embodiment, the center 201 of the glass plate and the center of the circuit pattern area 202 are aligned. Therefore, the difference from the first embodiment is that the circuit pattern area is at the center of the glass plate or the scribe line
The difference is whether the circuit pattern area including 203 is at the center. That is, the method and the effect are exactly the same except for the coordinate position.

〔The invention's effect〕

As described above, the present invention makes it possible to effectively use the full width of the scribe line by providing the scribe line only in the two directions around the circuit pattern region, and further, the scribe line region is not double-exposed. Especially in recent years, VLSI
With the rapid progress of integration and rapid integration, it is not necessary to operate the circuit inside the circuit pattern area as a circuit operation. Since it can be made small, its effects such as speeding up and cost reduction are immeasurable.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a first embodiment of the present invention, FIG. 2 is a diagram for explaining a second embodiment, FIG. 3, and FIG.
5 and 5 are views for explaining the conventional technique. 101,201,301,401 …… Center of glass plate, 102,202,302,402
...... Circuit pattern area, 103,203,303,403 …… Scribe line area.

Claims (1)

[Claims] 1. A reticle for use in a reduction projection exposure apparatus, which comprises a pattern for one chip consisting of an integrated circuit pattern region and a scribe line region existing around the integrated circuit pattern region, wherein the scribe line region is the integrated circuit pattern region. A semiconductor integrated circuit reticle, which is present only in the periphery of two sides adjacent to each other.