JPH0721818B2 - Character identification method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial Field B Outline of Invention C Conventional Technology D Problems to be Solved by the Invention E Means for Solving Problems (FIGS. 1 to 3) F Action G Example G ₁ Method Description (Figs. 1 to 3) G ₂ Description of device (Figs. 4 to 6) H Effect of the invention A Industrial field of application The present invention relates to a document printed on a medium such as a book. Regarding the method of identifying characters.

B Outline of the Invention The present invention relates to a character identification method, and by performing coding by coding the shape of the portion of the input character pattern that is in contact with the circumscribing frame, accurate identification can be performed with a simple configuration.

C Conventional Technology Various methods for identifying so-called printed characters have been proposed [(Yasuda et al. "Kanji Recognition by Hierarchical Pattern Matching Method in Frequency Domain" IEICE Vol.58-D, No.2, 1975) (Iijima "Discrimination theory based on mixed similarity (generalization of compound similarity method)", Shin-Kenkai Kensuke PRL74-24, 1974)].

Regarding such an identification method, the inventor of the present application has previously noticed that there is a great feature in the outer periphery of the character in the identification, and divides the character into a plurality of layers at a predetermined distance from the outer periphery, and for each of these layers. We proposed a method for comparing and identifying characters (Japanese Patent Application No. 60-147003). According to this, first, large classification is performed based on the characteristics of the outer circumference, and thereafter, characters in the classified range are sequentially identified, so that the identification can be performed easily and quickly.

By the way, in these identification methods, a so-called statistical process is generally used, in which an input character pattern that has been input is compared with a pattern of all characters that are provided in advance and the degree of matching is checked. Atsuta

However, in the apparatus that realizes the method as described above, the input of the character pattern to be identified is usually performed through the reading means such as an image reader. In that case, due to fluctuations in the slicing level in the image reader, residual errors in rotation correction in preprocessing, and distortions in the optical system, fluctuations in the input pattern such as line width fluctuations, tilt fluctuations, phase fluctuations, etc. Is usually added.

However, with the conventional technology, it is difficult to sufficiently compensate for these fluctuations, which also causes a reduction in the identification rate.

D Problems to be Solved by the Invention In the conventional technology, since the identification is performed by the statistical processing, there is a problem that the identification rate is significantly lowered due to the variation of the input pattern. .

E Means for Solving Problems The present invention relates to the input character pattern cut out character by character, and the distance from the circumscribing frames (1a) to (1d) of the input character pattern to the portion forming the character. Is measured, and the length (w ₁ , w ₂ ...) Of this portion is detected for the portion where this distance is less than or equal to a predetermined value (δ = W / 16: where W is the length of each side of the circumscribing frame). Then, the shape (peripheral feature) of the portion in contact with the circumscribing frame of the input character pattern is detected with the above-mentioned portion whose length is an arbitrary threshold value (w _TH = W / 4) or less as the end point and the above portion as the line segment. , Code this detected shape (line segment = "1",
This is a character identification method in which the end point = "0") and the input character pattern is identified based on the coded data.

According to this, the character pattern is coded for identification based on the so-called peripheral feature, and therefore the identification is less likely to be affected by fluctuations in the input pattern, etc., and particularly divided into a plurality of layers for identification. It can be applied to a large classification of cases to significantly improve the identification rate.

G Example G ₁ Description of Method FIG. 1 shows the character “sea” as an example of a character pattern. Four circumscribing frames (1a) (1b) (1c) (1d) are set so as to contact the outer periphery of this pattern. As shown in the figure, each side is named A side to D side.

For each of these sides, the distance from the circumscribing frames (1a) to (1d) to the part that constitutes the character is measured, and so-called peripheral features are detected. FIG. 2 shows the above-mentioned peripheral features on the side A.

Then, the detected peripheral feature is encoded as follows.

That is, for each side, first, the portion where the peripheral feature is less than or equal to the predetermined distance δ is detected. Next, it is determined whether or not there is a portion having the distance δ or less in the predetermined regions C _W at both ends of the side.
Furthermore, the length W ₁ , W of the part less than the distance δ from one end of the side
₂ ... are sequentially detected, and when the length is equal to or greater than a predetermined threshold W _TH, a line segment is determined, and when the length is less than or equal to the end point, an end point is determined.

As the distance δ, the area C _W , and the threshold value W _TH , for example, the length of each side of the circumscribing frames (1a) to (1d) is W, The degree is chosen.

Then, for each determination, the determined result, for each side,
First, there is (1) / no (0) of the character part in the upper end (left end) region, then, whether there is a character part in the lower end (right end) region, and then the line segment of the character part from the upper end (left end) side ( 1) and the end point (0) are sequentially provided to form a code. Since the code of the line segment and the code of the end point has a variable length, an end mark (1) is provided at the end.

As a result, the code on the A side above is W ₁ , W ₂ <W _TH , W ₃ > W
_{As TH} , it becomes as shown in FIG.

The present application uses this code for identification.

That is, codes based on the above-mentioned peripheral features are formed for all characters to be identified, and a dictionary classified by these codes is provided. On the other hand, for example, a document read by an image reader is cut out character by character by detecting line spacing and character spacing, and peripheral characteristics are detected for the cut out characters to form a code. Then, the code from the cut-out character is compared with the code provided in the above-mentioned dictionary, and the character of the matching code is identified.

In this way, the classification of the large classification is performed, and the classification is advanced to the middle classification or the small classification.However, according to the method described above, the character pattern is coded for the recognition, and thus the recognition can be performed in accordance with the variation of the input pattern. Less likely to be affected,
The identification rate can be significantly improved.

Description of G ₂ Device FIG. 4 shows a configuration for forming a code based on the peripheral feature. In this figure, (11) is a data bus, and a main memory (not shown) is connected to this bus (11) via a CPU (not shown). (For example, see Japanese Patent Application No. 59-252173)
The input character pattern of 128.times.128 bits is stored as .delta.8, which is cut out character by character.

The main memory is controlled by the CPU, and the four circumscribing frames (1a) for any one character pattern.
~ (1d) to circumscribed frames (1a) to (1d) to 16
The pattern is read at the depth of the bit and the data bus (11)
Through the memory (12).

On the other hand, (13) is an address bus, and an arbitrary address from the CPU is supplied to this bus (13), and an arbitrary address from this bus (13) is passed through the gate (14a) to the memory (12). Is supplied to. As a result, the 16-bit pattern on the four sides described above is written at a predetermined address in the memory (12). The capacity of the memory (12) is 128 × 4 addresses, 1 address 16 bits.

Furthermore, the signal from the address bus (13) is the decoder (15).
Is supplied to. First, an arbitrary timing signal is decoded, this signal is supplied to the latch circuits (16), (17) and (18), and δ, W _TH , and C _W of the data supplied to the data bus (11) at that time, respectively. The value of each latch circuit (16) to (1
8) is latched on.

Further, the decoder (15) decodes a signal corresponding to the detection period of the pattern on one side as shown by A in the time chart of FIG. 5, and this signal is supplied to the control circuit (19). In the control circuit (19), a CST pulse corresponding to the start of the A signal, an AST pulse generated one clock after that, and a CEN pulse corresponding to the end of the A signal, as shown in FIG. An AEN pulse is generated which is generated two clocks later.

This CST pulse and CEN pulse are the address counter (20).
Is supplied to. Then, in this counter (20), side A supplied to the data bus (11) at the time of the CST pulse
The address corresponding to any one of the starting edges of the D side is preset, and then a predetermined clock signal is counted up until the CEN pulse is supplied. Between CST and CEN pulse
Equivalent to 128 clocks.

The address generated by the counter (20) is supplied to the memory (12) through the gate (14b). As a result, from the memory (12), as shown at C in the time chart, the previously written signal is sequentially read out for each address for each internal clock between the CST and CEN pulses.

The read signal is adjusted in timing by the latch circuit (21) and then supplied to the priority encoder (22) for detecting the peripheral feature. In this encoder (22), the maximum value is "15" when the distance between the circumscribing frame and the character portion is 0, and a detected value that decreases as the distance increases is formed.

This detected value and the value of δ that has been latched by the latch circuit (16) are supplied to the comparator (23), and when the detected value is large, a comparison value that becomes "1" is taken out. Further, this comparison value is supplied to the flip-flop (24), and the comparison value X (refer to D of the time chart) whose timing is adjusted is taken out to the Q output and its inverted value (refer to the same E) is taken out to the output. It The flip-flop (24) is cleared by the OR signal of the CST pulse and AEN pulse.

The comparison value X is supplied to the counter (25). When the value X has a high potential, the clock as indicated by F in the time chart is counted, and when the value X has a low potential, the count value is cleared. This count value and latch circuit (1
The value of W _TH latched in 7) is supplied to the comparator (26), and when the value X is large, "1" is discriminated, and when the value X is small, a discriminant value which is "0" is taken out.

This discriminant value is supplied to the shift register (27). The shift register (27) is supplied with the AST pulse as the load pulse, the value of "100 ..." where only the bit at the input end is set to "1" is supplied as the load value, and the inverted value is supplied as the clock. The above-described discriminant value is taken in at each rise of the lever value time chart indicated by G. As a result, the shift register (27) forms a signal in which the leading bit is set to "1" and thereafter the line segment is sequentially provided with the value "0" at the "1" end point.

Further, the inverted value is supplied to the counter (28), the above clock is counted when this value has a high potential, and the count value is cleared when the value has a low potential.
This count value and the value of C _W latched by the latch circuit (18) are supplied to the comparator (29), and a discriminant value that is "1" when the value is small and "0" when it is large is taken out. .

This discriminant value is supplied to the D flip flops (30) (31). Also, the AST pulse is supplied to the clear terminal of the D flip-flop (32), and the comparison value X is supplied to the clock terminal of this flip-flop (32), whereby the comparison value X of the first comparison value X A CKS pulse indicating a rising edge is formed, and this CKS pulse is supplied to the clock terminal of the D flip-flop (30). AE
The N pulse is supplied to the clock terminal of the D-flop flop (31).

As a result, in the D flip flop (30), the distance from the end of the point where the depth of the character part first becomes δ or less
When the value is smaller than C _W, the value "1" is held, and when the value is large, it holds "0".
Also, the D flip flop (31) has a value of "1" when the distance from the point where the depth of the character part finally becomes δ or less to the end is smaller than C _W , and "0" when it is large. Retained.

The signals of the D flip-flops (30) (31) and the shift register (27) are sequentially read out to the data bus (11) under the control of the CPU, which is based on the above-mentioned peripheral feature. A code is formed. The shift register (27) is read from the input end side. Therefore, the reading order of the memory (12) and the like are adjusted so that the respective bits of the code are in a predetermined order. Also δ, C _W , W _TH
The value of can be arbitrarily changed by discriminating the state of the output code and the like.

Further, FIG. 6 shows a configuration for identifying a large classification from the codes of the input character pattern formed as described above.

In this figure, the codes on each side formed are respectively passed through a data bus (not shown) to a code register [CR].
It is supplied to (41A) to (41D). The codes from these code registers (41A) to (41D) are supplied to the address circuits (42A) to (42D), respectively, whereby the ROM (43
Each of the predetermined addresses A) to (43D) is read.
Here, ROM (43A) ~ (43D), ROM (48A) ~ after the first character that sorts the characters classified by that code at each address with any Kanji code, etc.
The address in (48D) and the number of characters M _i included in the classification are stored.

The address of the first character from the ROM (43A) to (43D) is supplied to the address counters [AC] (45A) to (45D) through the registers (44A) to (44D), respectively,
The number of characters M _i from the ROMs (43A) to (43D) is supplied to the member counters [MC] (46A) to (46D). Then, the addresses from the address counters (45A) to (45D) are supplied to the address circuits (47A) to (47D), respectively, so that the first of the characters classified by the codes of the ROMs (48A) to (48D) respectively. The Kanji code of is read. This ROM (48A)
The signals from (48C) to (48C) are supplied to the gate circuits (49A) to (49C), and the signals from the ROMs (48B) to (48D) are supplied to the gate circuits (50B) to (50D).

On the other hand, a signal indicating the identification mode described later from the data bus is supplied to the mode register [MR] (51), and the signal from this mode register (51) is supplied to the ROM (52). As a result, from the ROM (52), for example, Q ₀ output to the A side, Q ₁
The side B is output, the side C is output to the Q ₂ output, the side D is to the output Q ₃ , and the end code signal is output to the output Q ₄ . These codes are 2
Is composed of bits, the inner side A code since no appear in Q ₁ to Q _4, the same constructed and exit codes and side A code.

The Q ₀ output of this ROM (52) is supplied to the selector (53),
_{The 1 to} Q ₄ outputs are supplied to the shift register (54). The timing signal ▲ ▼ described later is the AND circuit (55).
Is supplied to the shift register (54) through Q ₁ to
The signal from the Q ₄ output is loaded and the output of the AND circuit (55) is fed through the inverter (56) to the selector (5
3), during which the Q ₀ output is selected.

The output of the selector (53) and the first output of the shift register (54) are supplied to the selector (57). Then, the signal from the inverter (56) is supplied to the selector (57) through the OR circuit (58), and the Q ₀ output from the selector (53) is selected during this signal ▲ ▼. This selector (5
The signal from 7) is supplied to the D flip-flop (59) and delayed for one clock period.

The signal from this flip-flop (59) is the selector (5
While being fed back to 3), it is supplied to the decoders (60) and (61), and the decoding corresponding to the above A side to C side is performed. Further, the signals from the shift register (54) are supplied to the decoders (62) (63), respectively, and the sides B to D described above are respectively supplied.
Decoding corresponding to the edge is performed. And the decoder (6
1) The signal from (63) is supplied to the gate circuits (49A) to (49C) and (50B) to (50D).

The signals from the gate circuits (49A) to (50D) thus taken out are supplied to the comparator (64). Then, when the Kanji code from the gate circuits (49A) to (49C) is small, the comparison output is supplied to the selector (57) through the OR circuit (58).

Therefore, for example, when the end signal is output from the Q ₀ output of the ROM (52) on the A side, the Q _{1 to} Q ₃ outputs on the B to D sides, and the Q ₄ output, first output the Q ₀ with the timing signal ▲ ▼. Is supplied to the D flip-flop (59) through the selectors (53) (57), the Q ₀ output is output from the D flip-flop (59) and the Q ₁ output is taken out from the shift register (54) by the next clock signal. It This signal is the decoder (61) (6
3), whereby the gate circuits (49A) and (50A)
B) is opened. At this time, if the Kanji code from the ROM (48A) is small, use the selector (57) to select the selector (5
The signal from 3) is selected, and in this selector (53), D
The signal from the flip-flop (59) is selected,
When the Kanji code from the ROM (48B) is small, the selector (57) selects the signal from the shift register (54), which allows the selector (57) to always select the side with the smaller Kanji code. Signal is taken out. Then, at the next clock signal, the signal from the selector (57) is output from the D flip-flop (59) and the shift register (54).
The Q ₂ output is taken from.

Furthermore, the gate circuit (49A) from the comparator (64) ~
The signal indicating that the Kanji code from (49C) is small is supplied to the enable terminal of the decoder (60) through the NOR circuit (65), and the Kanji code from the gate circuits (50B) to (50D) is small. A signal indicating the same is supplied to the enable terminal of the decoder (62) through the NOR circuit (66), and a signal indicating that the Kanji codes are equal is supplied to the NOR circuits (65) (66). The signal corresponding to the A side of the decoder (60) is supplied to the OR circuit (68A) through the inverter (67A),
The signal corresponding to the B side of the decoder (60) (62) is supplied to the OR circuit (68B) through the NAND circuit (67B), and the signal corresponding to the C side of the decoder (60) (62) is the NAND circuit (67C). The signal corresponding to the D side of the decoder (62) is supplied to the OR circuit (68C) through the inverter (67D). This OR circuit (6
The signals from 8A) to (68D) are supplied to a latch circuit (69) driven for each clock. Further, the latch outputs are supplied to AND circuits (70A) to (70D), respectively, and a signal from the comparator (64) indicating that the Kanji codes are equal is supplied to AND circuits (70A) to (70D). The signals from the AND circuits (70A) to (70D) are supplied to the OR circuits (68A) to (68D).

As a result, the latch circuit (69) sets the bit on the smaller side of the kanji code compared for each clock to "1", and when the kanji codes match, the bits on both sides indicate "1". The bit on the side marked "1" in the previous clock is fed back through the AND circuits (70A) to (70D), and the bits on all sides that match the smallest kanji code up to that time are " 1 ".

This operation is repeated for the outputs Q _{1 to} Q ₃ shifted by the shift register (54) for each clock.

When the end code signal appears at the output terminal immediately before the output terminal to the selector (57), this signal is output by the decoder (7
2) Decoded and supplied to AND circuits (71A) to (71D). As a result, the signals corresponding to the sides of the smallest Kanji code from the OR circuits (68A) to (68D) are taken out from the AND circuits (71A) to (71D), and the signals correspond to the address counters ( 45A) to (45D) and member counters (46A) to (46D) are supplied to the enable terminals, and are advanced by "1" at the next clock.

Further, the signal from the decoder (72) is supplied to the D flip-flop (73), the signal taken out at the output at the next clock is supplied to the AND circuit (55), and the shift register (54) is supplied from the ROM (52). Q _{1 to} Q ₄ outputs are loaded, selectors (53) and (57) are switched to the Q ₀ output side, and the above-described operation is repeated.

Furthermore, when all the bits of the latch circuit (69) become "1",
It is detected by the decoder (74) and this detection signal is supplied to the D flip-flop (75). Also, the Q output of the D flip flop (73) is 1 at the D flip flop (76).
It is clock-delayed and supplied to the D flip-flop (75), and the signal from this D flip-flop (75) is supplied to the data bus.

Further, the signals from the gate circuits (49A) to (49C) are supplied to the latch circuit (77), and the latch circuit (77) is driven by the signal from the D flip-flop (73) to generate the latch circuit (77). The signal from 77) is supplied to the data bus.

As a result, when the signal of the D flip-flop (75) is "1", the latch circuit (77) is latched with a Kanji code that matches on four sides, and this Kanji code is sent to the CPU (not shown) through the data bus. ) Can be taken into.

When the Kanji codes on the four sides match, the OR circuit (68
The outputs of A) to (68D) are all "1", and address counters (45A) to (45D) and member counters (46D)
All of A) to (46D) are advanced by "1", and the above operation is repeated. With this, multiple kanji codes that are roughly classified
Can be captured by the CPU.

Furthermore, the number of Kanji codes that identify each side is counted by the member counters (46A) to (46D), and this number is stored in the ROM.
When the number M _i from (43A) to (43D) is reached is detected. This is because, for example, the member counters (46A) to (46D) are loaded in advance with a one's complement to M _i , and "1" is added to each enable signal from the AND circuits (71A) to (71D). , Member Counter (46A) ~
It is detected when the contents of (46D) are all "1". This detection signal is supplied to the D flip-flops (78A) to (78D), and their outputs are transferred to the SR through the AND circuit (79).
Supplied to the terminals of the flip-flop (80).

As a result, the SR flip-flop (80) is set when all the Kanji codes on any one side are identified, and this Q output is supplied to the data bus as an identification end signal.
The output of the SR flip-flop (80) is supplied to the clear terminals of the member counters (46A) to (46D).

Further, the output of the AND circuit (79) is supplied to the terminal of the SR flip-flop (81). Further, a start signal of the identification operation from the data bus or the like is supplied to the terminal of the SR flip-flop (81), and this Q output is supplied to the input terminal of the shift register (82). And this shift register (82)
Is driven by the clock, the signal output from this A output becomes "1" continuously from the next clock when the Q output of the SR flip-flop (81) becomes "1". Are supplied to the registers (44A) to (44D).

In addition, the B output of the shift register (82) is the inverter (83).
Is supplied to the NAND circuit (8
4) Supplied to. As a result, the timing signal from the NAND circuit (84) becomes "0" only for the next one clock period when the Q output of the SR flip-flop (81) becomes "1".
▼ is taken out, and this signal ▲ ▼ is supplied to the above-mentioned AND circuit (55) and the address counter (45A)
To (45D), the member counters (46A) to (46D), and the clear terminals of the latch circuit (69).

Further, a clear signal from the data bus or the like is supplied to the SR flip-flop (80) terminal and the D flip-flop (75) clear terminal.

Therefore, in the above-mentioned device, the SR flip-flop (81)
By supplying the start signal of the identification operation to the S terminal of, any signal is loaded to the address counters (45A) to (45D), the member counters (46A) to (46D) and the shift register (54), The identification operation is started.

In this way, the kanji code common to the four sides is identified based on the code obtained from the peripheral characteristics, and the kanji can be identified and specified by performing the middle classification or the minor classification by any method below.

By the way, in the above-mentioned device, even if the identification operation is completed and an end signal is output from the SR flip-flop (80), it is possible that no Kanji code has been identified by the operation up to that point. In this case, it is considered that one of the detected four sides of the code is wrong. Therefore, in that case, the above-mentioned device can perform the identifying operation while removing any one of the four sides one by one.

That is, by setting a predetermined identification mode in the mode register (51) in the above device, the ROM (52) outputs codes corresponding to the four sides as shown below.

As a result, it is possible to perform identification in which one side is sequentially removed. At this time, the mode is switched by the decoder (74) so that all "1" s are decoded except for one side thereof.

Further, this identification can be performed by removing any two sides.

In addition, it is possible that noise is mixed in the input character pattern. In such a case, the so-called "crush" that is commonly seen in many cases is classified in ROM (48A).
It is possible to take measures by including it in the Kanji code of ~ (48D).

H According to the present invention, since the character pattern is coded for identification based on the so-called peripheral characteristics, the identification is less likely to be affected by variations in the input pattern, and particularly divided into a plurality of layers. It has become possible to significantly improve the identification rate by applying it to large classifications when performing identification.

[Brief description of drawings]

1 to 3 are diagrams for explaining the method of the present invention, and FIG.
FIGS. 6 to 6 are views for explaining an apparatus for realizing the method. (1a) to (1d) are circumscribing frames.

Claims (1)

[Claims] 1. For an input character pattern cut out character by character, a distance from a circumscribed frame of the input character pattern to a portion forming a character is measured, and a portion having a distance equal to or shorter than a predetermined value is measured. The length of the input character pattern is detected as the end point and the above portion is a line segment, and the shape of the portion in contact with the circumscribed frame of the input character pattern is detected. A character identification method that encodes and identifies the input character pattern based on the encoded data.