JPH0721838B2 - Measuring device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a measuring device, and more particularly to a data capturing method thereof.

[Conventional technology]

FIG. 2 is a system diagram showing a measuring device section of a conventional pulse width measuring timer. Reference numeral 1 is a counter, and 2 is a measuring register for storing the value of the counter 1 by a capture signal CAP.

FIG. 3 is a time chart for explaining the operation of the conventional device and the device according to the present invention. (A) is a count pulse, (b) is a count value, (c) is a capture signal CAP,
(D) is a capture permission signal a, which will be described in the embodiment below.
(E) shows the read signal RD, (f) shows the measurement register value, the period T1 in FIG. 3 corresponds to the operation of the conventional device, and the period T2.
Corresponds to the operation of the device according to the invention.

Next, the operation of the apparatus shown in FIG. 2 will be described with reference to FIG. The value of the counter 1 at that time is taken into the measurement register 2 by the take-in signal CAP generated at the rising or falling of the pulse. This value is externally read by the read signal RD. As shown in FIGS. 3 (c) and 3 (d), in the conventional device, the capture signal CAP becomes the capture permission signal a as it is.

Although the series of operations is as described above, the counter 1 continues counting even after the capture signal CAP is input, and prepares for the next measurement (input of the capture signal CAP).

[Problems to be solved by the invention]

The measuring device unit of the conventional pulse width measuring timer is configured as described above, and when the capture signal CAP is input during the read operation, the value of the measuring register 2 changes. At this time, if there is little time margin, there is a problem that the changing value is read out and is erroneously recognized.

The present invention has been made in view of such a point, and an object of the present invention is to prevent the value of the measurement register from changing during reading and to stabilize the data during reading. To get the equipment.

[Means for solving problems]

In order to achieve such an object, the present invention has a measurement register that temporarily stores measurement data, and stores new measurement data in the measurement register in response to a capture signal and stores it in a read signal. In a measuring device which reads out and outputs the measurement data stored in the measurement register in response to the read signal, a recognition unit that recognizes that the measurement register is performing a read operation, and a read operation by the recognition unit If it is recognized, the delay circuit delays the acquisition signal to delay the measurement data acquisition timing until the completion of the read operation.

[Action]

In the measuring device according to the present invention, the measured value is read out stably, and erroneous recognition is eliminated.

〔Example〕

FIG. 1 is a system diagram showing an embodiment of a measuring device according to the present invention. In FIG. 1, 1 is a counter, 2 is a measurement register for storing the value of the counter 1, 3 is a capture signal control circuit, 4 is a 1-cycle delay circuit, 5 is an inverter, 6,
Reference numeral 7 is an AND circuit, 8 and 9 are paths, and 10 is an OR circuit, and the inverter 5 and the AND circuits 6 and 7 constitute a recognition means. Further, the circuits shown in FIG. 1 are all described as circuits which operate with an "H" level signal as a significant signal.

The operation will be described below with reference to FIG. First, the acquisition of the count value when the read operation is not performed will be described (see period T1 in FIG. 3). Since the circuits shown in FIG. 1 are all circuits which operate with the "H" level signal as a significant signal, the read signal RD is at the "L" level when the read operation is not performed. Therefore, when the capture signal CAP is input, the signal CAP passes through the path 8 in the capture signal control circuit 3 and is output from the OR circuit 10 as the capture permission signal a. This makes counter 1
The count value of is taken into the measurement register 2.

Next, the case where the capture signal CAP is input during the read operation will be described (see period T2 in FIG. 3). In this case, the read signal RD is at "H" level. Therefore, the input capture signal CAP enters the 1-cycle delay circuit 4,
It is delayed until one cycle after the read operation is completed.
Is output from the OR circuit 10 as a capture permission signal a. That is, the read signal CAP during the read operation is 1
The count value of the counter 1 is fetched into the measurement register 2 by the cycle delay, and the delayed fetch signal CAP, which is the fetch permission signal a.

Since the operation is performed as described above, the value of the measurement register 2 does not change during the read operation, and the read operation can be stably performed.

In the above embodiment, the delay amount is set to be constant for one cycle. However, when the read operation is not completed within a certain period, the read signal RD is fetched into the delay circuit 4 to judge the completion of the read operation and the fetch signal CAP. It is also possible to output.

It is also possible to include all the circuits according to the present invention in one semiconductor integrated circuit.

〔The invention's effect〕

As described above, according to the present invention, by recognizing the read state and delaying the data acquisition timing when recognizing that the data is being read, the value of the measurement register does not change during the read operation. The obtained value can be read out stably, erroneous recognition is eliminated, and the stability of the device can be improved.

[Brief description of drawings]

FIG. 1 is a system diagram showing an embodiment of a measuring device according to the present invention, FIG. 2 is a time chart for explaining the operation of the device, and FIG. 3 is a system diagram showing a conventional device. 1 ... Counter, 2 ... Measurement register, 3 ... Acquisition signal control circuit, 4 ... 1 cycle delay circuit, 5 ... Inverter, 6,7 ... AND circuit, 8,9 ... Path, 10 ... OR circuit.

Claims (1)

[Claims] 1. A measurement register for temporarily storing measurement data, wherein new measurement data is fetched and stored in the measurement register in response to a fetch signal, and stored in the measurement register in response to a read signal. In the measuring device for reading out and outputting the measured data, the recognizing means for recognizing that the measuring register is in the reading operation by referring to the read signal, and the recognizing means performing the reading operation. If recognized, by delaying the acquisition signal,
A measuring device, comprising: a delay circuit that delays the timing of taking measurement data until after the reading operation is completed.