JPH0722185B2 - Memory cell array - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read-only memory (ROM) integrated circuit, and more particularly to a memory circuit constituted by serial and parallel connection (serial / parallel connection) of memory elements (memory cells) composed of transistors. For cell arrays.

[0002]

2. Description of the Related Art Recent large-scale integrated circuits (LSI) have been remarkably developed, and the progress of high performance of microprocessors and high speed and high density of semiconductor memories is remarkable. Under such circumstances, many microprocessor application products have been developed, and accordingly, a ROM having a small size and a large capacity has been demanded.

The structure of a general ROM is shown in FIG. In the figure, 11 is an address signal input terminal, 12 is an address buffer, 13 is an address column decoder, 14 is an address row decoder, 15 is a memory cell matrix array section (cell array), and 16 is a column selector and a sense amplifier. 17 is an output buffer, and 18 is an output signal output terminal. Of these, the area that occupies the largest area of the ROM chip is the cell array 1 composed of memory cells.
It is 5. Therefore, in order to increase the capacity of the memory, it is required to reduce the area of this cell array.

A conventional ROM is basically a memory cell MOS, in which an address signal is divided into two inside a ROM chip to be decoded into a row selection signal and a column selection signal and arranged at each intersection of a matrix of a cell array. One bit data fixed to the transistor is selected by a row selection signal and a column selection signal.

FIG. 2 shows a cell array composed of one basic memory cell and one contact portion. 21 of the figure
Is a metal serving as a read line (column line), 22 is polysilicon serving as a select line, 23 is a contact portion, 24 is a diffusion layer,
26 is a field portion, and 25 is a memory cell size including a contact portion.

FIG. 3 shows a case where two memory cells are connected in parallel to one contact. In the figure, 31 is a metal to be a read line (column line), 32 is a polysilicon to be a row selection line, 33 is a contact portion, 34 is a diffusion layer, and 36.
Is a field portion, and 35 is a memory cell size including a contact portion.

[0007]

However, in the cell array of FIG. 2, one contact portion is used for each memory cell, so that the same number of contacts as the memory cells are required, and the cell array of the cell array is required. The area becomes large. In the cell array of FIG. 3, the area of the contact portion occupying the entire memory cell size is half that of the cell array of FIG. 2, and the area of the cell array is smaller than that of FIG. Further, since the two memory cell transistors are connected in parallel to the contacts, the access time is not reduced as compared with that in FIG. However, the number of contacts required is half the capacity of the memory cell, and the chip area is still large.

On the other hand, FIG. 4 shows the case where the memory cell is connected in series to one contact.
In the figure, 41 is a metal to be a read line (column line), 42 is a polysilicon to be a row selection line, 43 is a contact portion, 4
6 is a field part, and 45 is a memory cell size. MO for memory cells connected in series
In general, the number of serial stages of S transistors is 2 ⁿ (n =
1, 2, 3, ...), and the area occupied by the contact portion with respect to the area of one memory cell is 1/2 ⁿ . Therefore, if the number of serial stages is increased, the area occupied by the contact portion can be almost ignored with respect to the memory cell size. This series connection method has a smaller memory cell size than the parallel connection method of FIG. Natsute, large-capacity ROM
Can be collected with high density. However, the access time is MO
It has a drawback that it depends on the number of serial stages of the S transistor and becomes slower as the number of serial stages increases.

The present invention solves the above-mentioned drawbacks of the conventional ROM, enables a high-density memory cell array, can reduce the chip size, and does not delay the access time. It provides a cell array.

[0010]

In a memory cell array of a ROM, there are provided eight groups in which a memory transistor serving as a plurality of storage elements and a plurality of selection transistors are connected in series, and the group is a memory. A diffusion layer group that constitutes the source / drain of the selection transistor and the selection transistor, and the diffusion layer group of the first group and the diffusion layer group of the second group of the eight groups are included in the same column. And the diffusion layer groups of the third group and the diffusion layer groups of the fourth group are arranged in the same column, and the diffusion layer groups of the fifth group and the diffusion layer groups of the sixth group are the same. The diffusion layer groups of the seventh group and the diffusion layer groups of the eighth group are arranged in a row, and are arranged in the same row.
And the seventh group are sequentially arranged in columns adjacent to each other, and the second, fourth, sixth, and eighth groups are sequentially arranged in columns adjacent to each other, and the first, second, and third groups are arranged. And one ends of the diffusion layer groups of the fourth group are formed in common with each other, and one ends of the diffusion layer groups of the fifth, sixth, seventh, and eighth groups are formed in common with each other, and one contact is provided for each contact. Connected to a common wiring via the section, the gate electrodes of the selection transistors of the first, third, fifth and seventh groups are commonly connected, and further, the gate electrodes of the second, fourth, sixth and eighth groups are connected. The gate electrodes of the selection transistors are commonly connected.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 shows a serial-parallel type ROM cell array. It is called a series-parallel type that memory transistors are connected in series to form a group and the groups are connected in parallel. In the figure, 51 is a metal (common wiring) that becomes a read line (column line), and 52 and 515 are memory cells that become storage elements.
Polysilicon (row selection wiring) serving as a row selection line for selecting a cell MOS transistor, and 53 and 54 polysilicon serving as a group selection line for selecting a memory cell group including memory MOS transistors connected in series. (Group selection wiring) 55 to 59 are diffusion layers of a MOS transistor (actually, a diffusion layer is not formed under the gate, each of which is composed of a plurality of diffusion layers) 510 and 511 are contact portions (contacts). Hole), 512 is a depletion type MOS transistor (selection MOS transistor), 513 is an enhancement type MOS transistor (selection MOS transistor), and 514 is a field portion.

In FIG. 5, memory cell MOS transistors are formed in the intersection regions of diffusion layers 56, 57, 58, 59 formed in the column direction and polysilicons 52, 515 arranged in the row direction. A selection MOS transistor is formed in the intersection region of the polysilicon 53, 54 arranged in the direction. As a result, the memory cell MOS
Four memory cell groups are formed by connecting eight transistors in series and two selection MOS transistors in series. The diffusion layers 56, 57 of this memory cell group,
One end of each of 58 and 59 constitutes a common diffusion layer at the contact portion 510 and is connected in parallel. That is, in FIG.
This is a drawing of two sets of ROM cell arrays connected in parallel in eight stages in series.

Memory cell groups connected in parallel via contacts 510 are selected by group select lines 53 and 54. For example, if the selection MOS transistor 512 is a depletion type and the selection MOS transistor 513 is an enhancement type, when the group selection line 53 is in the selected state, the selection MOS transistor 5 on the diffusion layer 56 side is selected.
Since 13 is off and the group selection MOS transistor 513 on the diffusion layer 57 side is on, the memory cell group on the diffusion layer 57 side is connected to the source 55 of the power supply and is in the selected state. Therefore, when the row selection line 515 and the group selection line 53 are selected, the contact 510 is connected to the memory cell group connected to the diffusion layer 57.

Next, the memory cell array will be described. The channel width (equivalent to the width of each diffusion layer) of the MOS transistor forming the memory cell is equal to the metal width, but the metal width of the contact portion is wide to form a contact hole therein. Conventionally, only one diffusion layer (memory cell group) was formed in the column direction with respect to the width of one contact portion, but there was a space waste, but as in the present invention, one contact portion is formed. Against
Further integration can be achieved by forming two diffusion layers in the column direction and arranging the memory cell group.

Further, in FIG. 5, one contact portion 510 exists for the memory cells (4 × 8 transistors) connected in four parallel and eight stages in series, and the ratio of the contacts to the memory cell size. Becomes extremely small. In particular, since the area of the memory cell size can be reduced without increasing the number of serial stages, the high density can be achieved without significantly reducing the access time.

Further, in the conventional example and the present invention, ROs having the same capacity (the same number of memory cell MOS transistors)
Since the number of contacts required for M is much smaller in the present invention, the area of the cell array can be made very small, resulting in a very high density cell array. In addition, FIG.
If the number of memory cells required to form a ROM having the same area as that of the conventional example of 4 is 16 in FIG. 5, the number is 8 in FIG. 5 of the present invention (however, since 2 selection MOS transistors are added, it is actually 10). Since the number of serial stages is small, the access time can be shortened.

Further, the present invention is characterized in that four memory cell groups formed in two columns adjacent to each other are connected to one contact portion.

For comparison, let us consider a structure in which eight memory cell groups are connected to one contact portion, for example. Since the memory cell group is formed in four columns above and below, the common diffusion layer in which the contacts are formed has a diffusion layer width of four columns. Further, four selection MOS transistors are connected in series to each memory cell group.
In this case, the number of series stages is increased and the parasitic capacitance of the contact portion is increased as compared with the present invention, so that the access time is delayed. On the other hand, the area is not so small. Therefore, as in the present invention, by connecting the four memory cell groups in two adjacent columns to one contact and making the selection line common with the four adjacent memory cell groups, the access time can be improved. This is the optimum memory cell array for achieving high density of the cell array without slowing down.

[0020]

As described above, by using the memory cell array of serial / parallel connection according to the present invention, a large capacity ROM cell array can be realized without delaying the access time.

[Brief description of drawings]

FIG. 1 is a diagram showing a block diagram of a general ROM.

FIG. 2 shows a basic memory cell array with one contact per memory cell.

FIG. 3 is a diagram showing a memory cell array in which two memory cells are connected in parallel to one contact.

FIG. 4 is a diagram showing a memory cell array in which memory cells are connected in series to one contact.

FIG. 5 is a diagram showing a serial-parallel type memory cell array.

[Explanation of Codes] 11 ... Address Signal Input Terminal 12 ... Address Buffer 13 ... Address Column Decoder 14 ... Address Row Decoder 15 ... Memory Cell Matrix Array 16 ... Column selector and sense amplifier section 17 Output buffer 18 Output signal output terminal 21 Metal (column line) 22 Polysilicon (row selection line) 23 Contact section 24 Diffusion layer 25 ... Memory cell size 26 ... Field 31 ... Metal (column line) 32 ... Polysilicon (row selection line) 33 ... Contact part 34 ... Diffusion layer 35 Memory cell size 36 ... Field part 41 ... Metal (column line) 42 ... Polysilicon (row selection line) 43 ... Contact part 44 ... Diffusion layer 45 ... Memory cell size 46 Field 51 Metal (column line) 52,515 Polysilicon (row selection line) 53, 54 Polysilicon (memory cell group selection line) 55 Diffusion layer (source side) 56, 57, 58, 59 Diffusion layer 510, 511 Contact part 512 Depletion type MOS transistor (selection MOS transistor) 513 Enhancement type MOS transistor ( Selection MOS transistor) 514 Field unit

Claims (1)

[Claims] 1. A memory of a read-only memory integrated circuit.
.For a memory that has multiple storage elements in a cell array
Transistor and multiple selection transistors connected in series
And a group formed by 8 Kosonae, the group, the memo
Transistor and source of the selection transistor
・ The eight glues having a diffusion layer group that constitutes the drain
The first group of diffusion layers and the second group
And the diffusion layer groups of the third group are arranged in the same row to expand the third group.
Dispersed layer group and diffusion layer group of 4th group are arranged in the same row
And a diffusion layer group fifth group of expansion of the sixth group of
Dispersion layers are arranged in the same row, and diffusion layers of the seventh group
And the diffusion layers of the eighth group must be arranged in the same row.
And the first, third, fifth and seventh groups are
The second, the fourth, the sixth, and the second columns are sequentially arranged in adjacent columns.
The 8th group must be arranged sequentially in rows adjacent to each other.
And the spreading of the first, second, third and fourth groups
One end of the layer group is formed in common with each other, and the fifth, sixth, and
One ends of the diffusion layer groups of the seventh and eighth groups are common to each other.
Common, and a common contact is provided through one contact
Connected to a wire, the first, third, fifth and seventh glues
Gate electrodes of the selection transistors of the
And further before the second, fourth, sixth and eighth groups
The gate electrodes of the selection transistors must not be commonly connected.
Memory cell array according to claim Rukoto.