JPH0722189B2 - Multilayer wiring board - Google Patents
Multilayer wiring boardInfo
- Publication number
- JPH0722189B2 JPH0722189B2 JP60169886A JP16988685A JPH0722189B2 JP H0722189 B2 JPH0722189 B2 JP H0722189B2 JP 60169886 A JP60169886 A JP 60169886A JP 16988685 A JP16988685 A JP 16988685A JP H0722189 B2 JPH0722189 B2 JP H0722189B2
- Authority
- JP
- Japan
- Prior art keywords
- signal wiring
- wiring
- multilayer
- wiring board
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、超高性能コンピユータのLSIチツプを実装す
るために用いて好適な多層配線基板に関するものであ
る。TECHNICAL FIELD The present invention relates to a multilayer wiring board suitable for mounting an LSI chip of an ultra-high performance computer.
従来より、この種の多層配線基板の１例として、アイ・
ビー・エム ジヤーナル オブ リサーチ アンド デ
ベロプメント「IBM Journal of Reserch and Developme
nt,Vol26,No.3,May 1982,286ページ〜296ページ，“The
Thin−Film Module as a High−Performance Semicond
uctor Package",293ページ，第10図（Figure 10）」で
紹介されているようなものがある。Conventionally, as one example of this kind of multilayer wiring board,
IBM Journal of Research and Developme
nt, Vol26, No.3, May 1982, pages 286-296, "The
Thin-Film Module as a High-Performance Semicond
uctor Package ", page 293, Figure 10].
この多層配線基板は、同論文の293ページ左段におい
て、「Iutegrated Capacitor Stractures（容量集積化
構造）」と題した項目の最初の行から「第10図に示す
（配線基板の）構造は薄膜配線とVLSIチツプのために用
意された多層セラミツク基板である。」と記述している
如く、また、同ページの右段の第10図の説明において
「平面上に敷かれた電源層間に形成された集積化デカプ
リング容量をもつ基板の断面図」と示している如く、内
部に電源配線層をもつ多層セラミツク基板と、その上に
形成された薄膜信号配線層とから成り立つ構造のもので
ある。このような多層配線基板は、一般的に高速度動作
を必要とする超高速コンピユータなどにマルチチツプパ
ツケージ、すなわち、配線基板の上に多数個のLSIチツ
プを高密度に搭載できるパツケージの配線基板として、
下記のような理由で最適である。This multilayer wiring board is described in the left column of page 293 of the same paper, from the first line of the item entitled "Iutegrated Capacitor Stractures" to "The structure (of the wiring board) shown in Fig. 10 is thin film wiring". Is a multilayer ceramic substrate prepared for the VLSI chip. ”And in the explanation of FIG. 10 on the right side of the same page,“ It is formed between the power supply layers laid on the plane. As shown in "Cross-sectional view of substrate having integrated decoupling capacitance", it has a structure composed of a multilayer ceramic substrate having a power supply wiring layer therein and a thin film signal wiring layer formed thereon. Such a multilayer wiring board is generally used as a wiring board of a multi-chip package for an ultra-high-speed computer that requires high-speed operation, that is, a package that allows a large number of LSI chips to be mounted on the wiring board at high density. ,
It is most suitable for the following reasons.
すなわち、一般に超高速コンピユータでは、上述のよう
なマルチチツプパツケージを多数個必要とし、しかも、
それぞれのマルチチツプパツケージは機能が全く異なる
場合が多い。つまり、個々の機能を持つマルチチツプパ
ツケージの組み合わせにより、１つの超高速コンピユー
タが構成されている。しかるに、多層配線基板の配線
も、それぞれ全く異なつたものを形成する必要がある。
しかし、他の観点、すなわち多層配線基板を製造する観
点からみると、同じ配線はなるべく、共通化することに
より、多層配線基板の製造工程を少しでも単純化するこ
とが工業的に好ましいことは明らかである。このような
意味から、共通配線、すなわち電源配線をセラミツク基
板内に集約化することにより、製造工程を単純化できる
構造がとれる点で有利である。That is, in general, an ultra-high speed computer requires a large number of multi-chip packages as described above, and
The functions of the respective multi-chip packages are often completely different. That is, one ultra-high speed computer is configured by combining multi-chip packages having individual functions. However, it is necessary to form completely different wirings for the multilayer wiring board.
However, from another viewpoint, that is, from the viewpoint of manufacturing a multilayer wiring board, it is clear that it is industrially preferable to simplify the manufacturing process of the multilayer wiring board as much as possible by making the same wiring common. Is. From this point of view, by consolidating the common wirings, that is, the power supply wirings in the ceramic substrate, it is advantageous in that the manufacturing process can be simplified.
つまり、多層配線基板の品種に関係なく、電源配線の集
約化された多層セラミツク基板を大量生産し、この多層
セラミツク基板の上に個別に薄膜信号配線層を形成する
ことにより、多品種の多層配線基板を作り上げることが
できる。このような製造方法により完成された多層配線
基板の各々は、個別な機能を有するものであつても、そ
の製造工程においては、共通化できる部分が集約化され
ており、大幅に製造性を向上し、低価格化をはかること
ができている。In other words, regardless of the type of multilayer wiring board, a large number of multilayer ceramic boards with integrated power supply wiring are mass-produced, and thin-film signal wiring layers are individually formed on this multilayer ceramic board. The substrate can be built up. Even though each of the multilayer wiring boards completed by such a manufacturing method has individual functions, in the manufacturing process, the common parts are integrated, and the productivity is greatly improved. However, the price has been reduced.
しかしながら、従来のこのような多層配線基板による
と、薄膜信号配線の歩留まりに問題があり、この歩留ま
りの問題がコストアツプの要因となつていた。However, according to such a conventional multilayer wiring board, there is a problem in the yield of the thin film signal wiring, and this yield problem has been a factor of cost increase.
すなわち、薄膜信号配線層を形成するときは、品種対応
で、異なつたマスクを使用しなければならず、マスクの
準備や製造時のマスク取り扱いの複雑さをのがれるため
に、薄膜信号配線層の層数はできるだけ少ないことが好
ましい。通常、このような理由から、薄膜信号配線層の
層数は最少の２層構成が選ばれている。しかるに、多層
配線基板上に搭載する多数個のLSIチツプ間を接続する
信号配線等を充分に提供しようとすると、前記２層の薄
膜信号配線層には、高密度化のために微細な配線が必要
である。薄膜による配線形成は微細化には適していると
は言え、微細な配線を施すほど歩留りが悪くなるという
問題がある。この歩留りの問題がコストアツプの要因と
なるものであり、コストを低減させるための手段として
歩留りの向上を考えるならば、その微細化は必要最小限
に留めておくことが好ましい。That is, when forming a thin film signal wiring layer, different masks must be used depending on the product type, and the complexity of mask handling during mask preparation and manufacturing can be reduced. It is preferable that the number of layers is as small as possible. For this reason, a two-layer structure having a minimum number of thin film signal wiring layers is usually selected. However, if it is attempted to sufficiently provide signal wiring or the like for connecting between a large number of LSI chips mounted on a multilayer wiring board, the two thin film signal wiring layers have fine wiring for high density. is necessary. Although wiring formation using a thin film is suitable for miniaturization, there is a problem that the yield decreases as the wiring is finer. This yield problem is a factor of cost increase, and considering improvement of yield as a means for reducing cost, it is preferable to keep the miniaturization to a necessary minimum.
本発明は、このような問題点に鑑みてなされたもので、
上述した多層配線基板において、多層セラミック基板中
に共通信号配線を設け、この共通信号配線をクロック信
号配線としたものである。The present invention has been made in view of such problems,
In the above-mentioned multilayer wiring board, the common signal wiring is provided in the multilayer ceramic board, and the common signal wiring is used as the clock signal wiring.
したがって、この発明の多層配線基板によれば、薄膜信
号配線層に含まれるべきクロック信号配線を多層セラミ
ック基板に移設して、薄膜信号配線層内の信号配線密度
を減少させることができる。Therefore, according to the multilayer wiring board of the present invention, the clock signal wirings to be included in the thin film signal wiring layer can be transferred to the multilayer ceramic substrate to reduce the signal wiring density in the thin film signal wiring layer.
以下、本発明に係る多層配線基板を詳細に説明する。図
は、この多層配線基板の一実施例を示す側断面図であ
る。同図において、１は多層セラミツク基板、２はこの
セラミツク基板１内に形成された電源配線層、３はこの
セラミツク基板１の上面に形成された薄膜信号配線層、
４は共通信号配線、５は入出力ピン、６はスルーホール
配線、８は薄膜信号配線層３上に複数個搭載されたLSI
チップであり、これらの構成要素により多層配線基板７
が構成されている。Hereinafter, the multilayer wiring board according to the present invention will be described in detail. FIG. 1 is a side sectional view showing an embodiment of this multilayer wiring board. In the figure, 1 is a multilayer ceramic substrate, 2 is a power wiring layer formed in the ceramic substrate 1, 3 is a thin film signal wiring layer formed on the upper surface of the ceramic substrate 1,
4 is a common signal wiring, 5 is an input / output pin, 6 is a through hole wiring, and 8 is an LSI mounted on the thin film signal wiring layer 3 in plural numbers.
Chip, and the multilayer wiring board 7 by these components
Is configured.
スルーホール配線６は、入出力ピン５から供給される電
源を電源配線層２に伝え、さらにLSIチツプ８に供給す
るための導体経路であると共に、薄膜信号配線層３を通
じてLSIチツプ８に信号を伝達する導体経路でもある。
電源配線層２は、複数個のLSIチツプ８に均一に電源を
供給することができるように設けられている。薄膜信号
配線層３は、搭載された複数個のLSIチツプ８間の信号
線の接続およびLISチツプ８と入出力ピン５との信号お
よび電源接続のために設けられており、予め製造された
多層セラミツク基板１の上面に後工程で形成することに
より得られている。この薄膜信号配線層３は、多層配線
基板の品種に応じて異なることは前述した通りである。The through-hole wiring 6 is a conductor path for transmitting the power supplied from the input / output pin 5 to the power supply wiring layer 2 and further supplying it to the LSI chip 8, and also sends a signal to the LSI chip 8 through the thin film signal wiring layer 3. It is also a conductor path for transmission.
The power supply wiring layer 2 is provided so that power can be uniformly supplied to the plurality of LSI chips 8. The thin film signal wiring layer 3 is provided for connecting signal lines between a plurality of mounted LSI chips 8 and for connecting signals and power between the LIS chip 8 and the input / output pins 5, and is a pre-manufactured multilayer. It is obtained by forming it on the upper surface of the ceramic substrate 1 in a post process. As described above, the thin film signal wiring layer 3 differs depending on the type of the multilayer wiring board.
一方、共通信号配線４は、薄膜信号配線層３に包含され
るべき信号配線の内、各品種にわたつて共通化すること
の可能な信号配線を分離し、多層セラミツク基板１内に
移設したものである。したがつて、薄膜信号配線層３内
の信号配線密度は従来に比して減少している。On the other hand, the common signal wiring 4 is a signal wiring that should be included in the thin-film signal wiring layer 3 and is separated from the signal wiring that can be shared among various types, and is transferred to the multilayer ceramic substrate 1. Is. Therefore, the signal wiring density in the thin film signal wiring layer 3 is reduced as compared with the conventional one.
本実施例においては、この共通信号配線４をクロツク信
号配線とした。すなわち、一般的にクロツク信号端子
は、各LSIチツプ８の端子において共通であり、また通
常のコンピユータに使用するデジタル論理回路では必ら
ず必要であるから、予め、多層配線基板の品種に関係な
く固定的、即ち共通的に設けておくことができる。この
ような構造をとることによつて、薄膜信号配線層内のク
ロツク信号配線を除去することができ、その減少割合だ
け薄膜信号配線の歩留りを向上させることができてい
る。クロツク信号配線は超高速論理回路では、クロツク
スキユーの低減のため、しばしば等長配線を要求される
ため、予想外に大きい配線領域を専有し、その割合は10
〜20％のレベルに達することがある。したがつて、クロ
ツク信号配線を移設したことによる効果は極めて大きい
と言える。In this embodiment, the common signal wiring 4 is a clock signal wiring. That is, generally, the clock signal terminal is common to the terminals of each LSI chip 8 and is indispensable for the digital logic circuit used for a normal computer. Therefore, regardless of the type of the multilayer wiring board, It can be fixed, that is, commonly provided. With such a structure, the clock signal wiring in the thin film signal wiring layer can be removed, and the yield of the thin film signal wiring can be improved by the reduction rate. The clock signal wiring occupies an unexpectedly large wiring area because the wiring of ultra-high-speed logic circuits often requires equal-length wiring in order to reduce clock skew.
May reach levels of ~ 20%. Therefore, it can be said that the effect of moving the clock signal wiring is extremely large.
ところで、セラミツク基板１内に、共通信号配線４、即
ちクロツク信号配線を移設したことによつて、セラミツ
ク基板１の製造性が若干悪くなるという問題はあるが、
この製造性の犠牲は、薄膜信号配線の歩留りの向上に比
して少ないと言える。何故なら、まず第１にセラミツク
基板１内の共通信号配線４、即ちクロツク信号配線は、
同一層内において、他に障害となる配線が全くないため
充分な歩留りを確保できるような設計を適用できるこ
と、第２にセラミツク基板１を一括製造できることによ
るコスト低減効果が、共通信号配線４を移設したことに
よるコスト上昇分を凌駕すると言えるからである。By the way, since the common signal wiring 4, that is, the clock signal wiring is transferred into the ceramic substrate 1, there is a problem that the manufacturability of the ceramic substrate 1 is slightly deteriorated.
It can be said that this sacrifice in manufacturability is less than that in improving the yield of the thin film signal wiring. Because, first of all, the common signal wiring 4 in the ceramic substrate 1, that is, the clock signal wiring is
In the same layer, since there is no other wiring which becomes an obstacle, it is possible to apply a design that can secure a sufficient yield. Secondly, the cost reduction effect by the batch manufacturing of the ceramic substrate 1 is to transfer the common signal wiring 4. This is because it can be said that it will outweigh the cost increase due to doing so.
以上説明したように本発明による多層配線基板による
と、多層セラミック基板中に共通信号配線を設け、この
共通信号配線をクロック信号配線としたので、薄膜信号
配線層に含まれるべきクロック信号配線を多層セラミッ
ク基板に移設して、すなわち予想外に大きい配線領域を
専有するクロック信号配線を多層セラミック基板に移設
して、薄膜信号配線層内の信号配線密度を減少させるこ
とができ、従来に比して全体コストを低減させることが
できる。As described above, according to the multilayer wiring board of the present invention, the common signal wiring is provided in the multilayer ceramic substrate, and this common signal wiring is used as the clock signal wiring. Therefore, the clock signal wiring to be included in the thin film signal wiring layer is multilayered. It is possible to reduce the signal wiring density in the thin film signal wiring layer by transferring it to the ceramic substrate, that is, moving the clock signal wiring that occupies an unexpectedly large wiring area to the multilayer ceramic substrate. The overall cost can be reduced.
図は、本発明に係る多層配線基板の一実施例を示す側断
面図である。 １……多層セラミツク基板、２……電源配線層、３……
薄膜信号配線層、４……共通信号配線、７……多層配線
基板。FIG. 1 is a side sectional view showing an embodiment of a multilayer wiring board according to the present invention. 1 ... Multilayer ceramic substrate, 2 ... Power supply wiring layer, 3 ...
Thin film signal wiring layer, 4 ... Common signal wiring, 7 ... Multilayer wiring board.
Claims (1)
このセラミック基板の表面に形成された薄膜信号配線層
と、この薄膜信号配線層上に搭載された複数個のLSIチ
ップとを備えてなる多層配線基板において、 前記多層セラミック基板中に共通信号配線が設けられ、
この共通信号配線がクロック信号配線であることを特徴
とする多層配線基板。1. A multilayer ceramic substrate including a power supply wiring layer,
In a multilayer wiring board comprising a thin film signal wiring layer formed on the surface of this ceramic substrate and a plurality of LSI chips mounted on this thin film signal wiring layer, common signal wiring is provided in the multilayer ceramic substrate. Is provided,
A multilayer wiring board in which the common signal wiring is a clock signal wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60169886A JPH0722189B2 (en) | 1985-08-02 | 1985-08-02 | Multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60169886A JPH0722189B2 (en) | 1985-08-02 | 1985-08-02 | Multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6231146A JPS6231146A (en) | 1987-02-10 |
| JPH0722189B2 true JPH0722189B2 (en) | 1995-03-08 |
Family
ID=15894777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60169886A Expired - Lifetime JPH0722189B2 (en) | 1985-08-02 | 1985-08-02 | Multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0722189B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5039628A (en) * | 1988-02-19 | 1991-08-13 | Microelectronics & Computer Technology Corporation | Flip substrate for chip mount |
| US4926241A (en) * | 1988-02-19 | 1990-05-15 | Microelectronics And Computer Technology Corporation | Flip substrate for chip mount |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6041859B2 (en) * | 1980-02-13 | 1985-09-19 | 三菱電機株式会社 | semiconductor container |
| JPS60117796A (en) * | 1983-11-30 | 1985-06-25 | 日本電気株式会社 | Multilayer circuit board and method of producing same |
-
1985
- 1985-08-02 JP JP60169886A patent/JPH0722189B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6231146A (en) | 1987-02-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |