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JPH0722250B2 - Non-linear amplifier circuit - Google Patents
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JPH0722250B2 - Non-linear amplifier circuit - Google Patents

Non-linear amplifier circuit

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Publication number
JPH0722250B2
JPH0722250B2 JP61152505A JP15250586A JPH0722250B2 JP H0722250 B2 JPH0722250 B2 JP H0722250B2 JP 61152505 A JP61152505 A JP 61152505A JP 15250586 A JP15250586 A JP 15250586A JP H0722250 B2 JPH0722250 B2 JP H0722250B2
Authority
JP
Japan
Prior art keywords
output
transistor
voltage
differential amplifier
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61152505A
Other languages
Japanese (ja)
Other versions
JPS639215A (en
Inventor
彰 村山
文人 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61152505A priority Critical patent/JPH0722250B2/en
Publication of JPS639215A publication Critical patent/JPS639215A/en
Publication of JPH0722250B2 publication Critical patent/JPH0722250B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 産業上の利用分野 本発明は、入力電圧に対し非線形に変化する出力電圧を
得る非線形増幅回路に関し、特に、抵抗型センサー等の
ように非線形に変化する電圧信号を線形の出力電圧に変
換する線形増幅回路に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-linear amplifier circuit that obtains an output voltage that changes non-linearly with respect to an input voltage, and in particular, a non-linear voltage signal that changes non-linearly such as a resistance sensor. The present invention relates to a linear amplifier circuit that converts the output voltage of the linear amplifier.

従来の技術 従来の非線形増幅回路の回路構成を第3図に示す。第3
図において、31は入力端子、32は演算増幅器、33〜39は
抵抗、40〜42はダイオード、43は出力端子、44はバイア
ス端子である。
2. Description of the Related Art FIG. 3 shows a circuit configuration of a conventional nonlinear amplifier circuit. Third
In the figure, 31 is an input terminal, 32 is an operational amplifier, 33 to 39 are resistors, 40 to 42 are diodes, 43 is an output terminal, and 44 is a bias terminal.

そして、入力端子31から入力電圧が入力されると、演算
増幅器32は正転増幅し、入力電圧が増加するにつれて、
出力電圧が増大していき、ダイオード40…41が順次導通
する。そして、出力端子43から演算増幅器32の反転入力
端に負帰還する帰還抵抗Rxが、ダイオード40…41の導通
によって順次切り替わる。ここで、抵抗33〜39の各抵抗
値をR33〜R39とすると、入力電圧が小さく、全てのダイ
オード40…41がオフ状態になる第1の段階では、帰還抵
抗Rx=R35であるが、入力電圧が少し大きくなって、ダ
イオード40が導通する第2の段階は、帰還抵抗Rx=R35R
36/(R35+R36)となる。更に入力電圧が大きくなっ
て、ダイオード40…41が導通する第3の段階は、帰還抵
抗がRx=R35R36R37/(R35R36+R36R37+R37R35)となる
ように、帰還抵抗Rxは入力電圧の増大に応じて抵抗の並
列回路が増加するように変化し、徐々に抵抗値が小さく
なる。
Then, when the input voltage is input from the input terminal 31, the operational amplifier 32 performs normal amplification, and as the input voltage increases,
The output voltage increases and the diodes 40 ... 41 are sequentially turned on. Then, the feedback resistance Rx that negatively feeds back from the output terminal 43 to the inverting input terminal of the operational amplifier 32 is sequentially switched by the conduction of the diodes 40. Here, assuming that the resistance values of the resistors 33 to 39 are R 33 to R 39 , the feedback resistor Rx = R 35 in the first stage in which the input voltage is small and all the diodes 40 ... 41 are in the off state. However, the second stage when the input voltage becomes a little higher and the diode 40 conducts is the feedback resistance Rx = R 35 R
36 / (R 35 + R 36 ) Moreover the input voltage is increased, the third stage of the diode 40 ... 41 conducts the feedback resistor Rx = R 35 R 36 R 37 / (R 35 R 36 + R 36 R 37 + R 37 R 35) and so as In addition, the feedback resistance Rx changes so that the parallel circuit of the resistance increases as the input voltage increases, and the resistance value gradually decreases.

一方、この回路は、電圧増幅度が(1+Rx/R34)で決定
されるから、入力電圧のレベルに応じて電圧増幅度が変
化し、結果として、疑似的に関数変換するものであっ
た。
On the other hand, in this circuit, since the voltage amplification degree is determined by (1 + Rx / R 34 ), the voltage amplification degree changes according to the level of the input voltage, and as a result, the function is converted into a pseudo function.

発明が解決しようとする問題点 上述のような従来の構成では、抵抗の値の温度特性を補
償することは可能であるが、ダイオードの順方向ダイオ
ード電圧の温度特性を補償することができず、各ダイオ
ードの導通する出力電圧のレベルが温度によって変動す
ることが問題であった。
Problems to be Solved by the Invention In the conventional configuration as described above, it is possible to compensate the temperature characteristic of the resistance value, but it is not possible to compensate the temperature characteristic of the forward diode voltage of the diode, It is a problem that the level of the output voltage conducted by each diode varies depending on the temperature.

本発明は、このような問題点を解決するもので、温度変
化に対して安全に動作する非線形増幅回路を提供するこ
とを目的とするものである。
The present invention solves such a problem, and an object of the present invention is to provide a non-linear amplification circuit that operates safely against temperature changes.

問題点を解決するための手段 本発明の非線形増幅回路は、一導電型トランジスタの差
動対と、同差動対の出力にベースを接続しコレクタに第
1の抵抗を接続した一導電型の出力用トランジスタとを
有し、同出力用トランジスタのエミッタ出力を前記差動
対の反転入力端に帰還結合してなる第1の差動増幅器
と、逆導電型トランジスタの差動対の出力をエミッタホ
ロワ構成で出力し、そのエミッタホロワ出力を前記逆導
電型トランジスタの差動対の反転入力端に帰還結合して
なる第2の差動増幅器の複数構体とを備え、前記複数構
体のエミッタホロワ出力と前記出力用トランジスタのエ
ミッタ出力の間に夫々個別の低抗体を接続し、前記複数
構体の各非反転入力端に夫々異なる基準電位を入力する
と共に、前記第1の差動増幅器の非反転入力端に入力信
号を与え、前記第1の抵抗の端子間から出力電圧を取り
出すことを特徴とする構成である。
Means for Solving the Problems The nonlinear amplification circuit of the present invention comprises a differential pair of one conductivity type transistors, and a one conductivity type transistor in which a base is connected to an output of the differential pair and a first resistor is connected to a collector. A first differential amplifier having an output transistor and an emitter output of the output transistor feedback-coupled to an inverting input terminal of the differential pair; and an output of the differential pair of the reverse conductivity type transistor as an emitter follower. A plurality of structures of a second differential amplifier, which is configured to output and whose emitter follower output is feedback-coupled to an inverting input terminal of a differential pair of the reverse conductivity type transistor, and the emitter follower outputs of the plurality of structures and the output. Individual low antibodies are connected between the emitter outputs of the transistor for application, different reference potentials are input to the respective non-inverting input terminals of the plurality of structures, and the non-inverting input terminal of the first differential amplifier is connected. The input voltage is applied to and the output voltage is taken out from between the terminals of the first resistor.

作 用 この構成により、第1の差動増幅器は入力用ボルテージ
ホロワとして機能し、出力用トランジスタのエミッタ出
力は入力電圧と等しい電圧を低インピーダンスで出力
し、各第2の差動増幅器の各エミッタホロワ出力も夫々
低インピーダンスで動作し、入力される異なる基準電位
と等しい電圧を夫々出力する。そして、あるエミッタホ
ロワ出力の電位より第1の差動増幅器のエミッタ出力の
電位が高くなった時、そのエミッタホロワ出力に接続さ
れた抵抗を通じて、基準電位と入力電圧との電圧差に応
じた電流が流れ、この電流が第1の差動増幅器の出力用
トランジスタの動作電流に加算されることになり、入力
電圧に対して非線形に変化する出力電圧が第1の抵抗の
端子間から出力される。
Operation With this configuration, the first differential amplifier functions as an input voltage follower, the emitter output of the output transistor outputs a voltage equal to the input voltage with low impedance, and each of the second differential amplifiers The emitter follower outputs also operate with low impedance, and output voltages equal to the different reference potentials that are input. When the emitter output potential of the first differential amplifier becomes higher than the emitter follower output potential, a current corresponding to the voltage difference between the reference potential and the input voltage flows through the resistor connected to the emitter follower output. This current is added to the operating current of the output transistor of the first differential amplifier, and the output voltage that changes non-linearly with respect to the input voltage is output from between the terminals of the first resistor.

実施例 本発明の非線形増幅回路に係わる一実施例について、そ
の回路構成図を示す第1図を参照しながら以下に説明す
る。
Embodiment An embodiment relating to the nonlinear amplifier circuit of the present invention will be described below with reference to FIG. 1 showing a circuit configuration diagram thereof.

第1図において、11はNPN型トランジスタの差動対を主
体とする第1の差動増幅器、12,13,14はPNP型トランジ
スタの差動対を主体とする第2の差動増幅器である。そ
して、15は入力電圧が入力される入力端子、Vccは電源
電圧が供給される電源電圧端子、16は基準電圧が供給さ
れる基準電圧端子、17〜23,111,1201〜1204並びに1301
〜1304は抵抗、112〜114,1205〜1207並びに1305〜1307
はNPN型トランジスタ、115,116,1208〜1211並びに1308
〜1311はPNP型トランジスタ、117,1212並びに1312は定
電流源、24〜27は接点である。
In FIG. 1, reference numeral 11 is a first differential amplifier mainly composed of a differential pair of NPN type transistors, and 12, 13, 14 are second differential amplifiers mainly composed of a differential pair of PNP type transistors. . Further, 15 is an input terminal to which an input voltage is input, Vcc is a power supply voltage terminal to which a power supply voltage is supplied, 16 is a reference voltage terminal to which a reference voltage is supplied, 17 to 23,111,1201 to 1204 and 1301.
~ 1304 is a resistance, 112 ~ 114, 1205 ~ 1207 and 1305 ~ 1307
Is an NPN transistor, 115, 116, 1208 to 1211 and 1308
1311 are PNP transistors, 117, 1212 and 1312 are constant current sources, and 24 to 27 are contacts.

ここで、第1の差動増幅器11は、エミッタを共通接続し
たNPN型トランジスタ112,113の差動対と、そのエミッタ
共通接続点に電流を供給する定電流源117と、トランジ
スタ112,113のコレクタを結合するPNP型トランジスタ11
5,116と、差動対の出力端(トランジスタ113のコレク
タ)と電圧を出力する出力用のNPN型トランジスタ114と
で構成され、トランジスタ114のエミッタ出力27はトラ
ンジスタ113のベース(差動をトランジスタ1211のエミ
ッタ出力から低インピーダンスで出力する為のものであ
り、後者の差動増幅器13ほ接点25の電圧V25をトランジ
スタ1311のエミッタ出力から低インピーダンスで出力す
る為のものであり、更に、差動増幅器14は接点16の電圧
V26を低インピーダンスで出力する為のものである。
Here, the first differential amplifier 11 couples a differential pair of NPN transistors 112 and 113 whose emitters are commonly connected, a constant current source 117 which supplies a current to the common node of the emitters, and a collector of the transistors 112 and 113. PNP type transistor 11
5, 116, and an output terminal of the differential pair (collector of the transistor 113) and an output NPN transistor 114 that outputs a voltage. The emitter output 27 of the transistor 114 is the base of the transistor 113 (differential of the transistor 1211). It is for outputting with low impedance from the emitter output, and for outputting the voltage V 25 of the latter differential amplifier 13 and contact 25 with low impedance from the emitter output of the transistor 1311. 14 is the voltage of contact 16
It is for outputting V 26 with low impedance.

次に、第1図示の一実施例の回路動作を詳しく説明す
る。まず、接点27と24の電圧V27とV24とがV27<V24の場
合、トランジスタ1209はオン状態、トランジスタ1210は
オフ状態となり、トランジスタ1210のコレクタに接続さ
れるトランジスタ1207,1206並びにトランジスタ1211,12
05,1208はオフ状態になるから、抵抗1203には電流I1203
が流れず、無視できる程度のわずかなトランジスタ1209
のベース電流が抵抗17に向けて流れ出す程度で、差動増
幅器12は基本的にオフ状態になる。
Next, the circuit operation of the embodiment shown in FIG. 1 will be described in detail. First, when a voltage V 27 and V 24 of the contacts 27 and 24 of the V 27 <V 24, the transistor 1209 is turned on, the transistor 1210 is turned off, the transistor 1207,1206 and transistors are connected to the collector of the transistor 1210 1211,12
05,1208 is turned off, so the current I 1203
Does not flow and is negligible transistor 1209
The differential amplifier 12 is basically in the off state only when the base current of the current flows to the resistor 17.

逆に、接点27と24の電圧V27とV24とがV27>V24になった
場合、トランジスタ1209はオフ状態、トランジスタ1210
はオン状態となり、トランジスタ1210のコレクタに接続
されるトランジスタ1207,1206並びにトランジスタ1211,
1205,1208がオン状態になり、抵抗1203には電流I1203
流る。その結果、差動増幅器12は基本的にオン状態にな
り、トランジスタ1211のエミッタ出力に基準電圧V24
等しい電圧が低インピーダンスで出力され、抵抗17には
接点27から差動増幅器12の出力端(トランジスタ1211の
エミッタ)に向けて電流I17が流れる。この電流は、抵
抗17の抵抗値をR17と仮定すると、 I17=(V27−V24)/R17 ……(1) で表すことができる。そして、上記の差動増幅器12と同
一形式の差動増幅器13についても同様に動作し、接点27
と25の電圧V27とV25がV27<V25の場合、差動増幅器13は
基本的にオフ状態になり、V27>V25の場合、抵抗18には
接点27から差動増幅器13の出力端(トランジスタ1311の
エミッタ)に向けて電流I18が流れる。この電流は、抵
抗18の抵抗値をR18と仮定すると、下式のように表すこ
とができる。
On the contrary, when the voltages V 27 and V 24 of the contacts 27 and 24 become V 27 > V 24 , the transistor 1209 is turned off and the transistor 1210 is turned off.
Is turned on, and transistors 1207 and 1206 and transistors 1211 and 1211 connected to the collector of the transistor 1210 are turned on.
The 1205 and 1208 are turned on, and the current I 1203 flows through the resistor 1203. As a result, the differential amplifier 12 is basically turned on, a voltage equal to the reference voltage V 24 is output to the emitter output of the transistor 1211 with low impedance, and the resistor 17 is connected from the contact 27 to the output terminal of the differential amplifier 12. A current I 17 flows toward (the emitter of the transistor 1211). This current can be expressed by I 17 = (V 27 −V 24 ) / R 17 (1) assuming that the resistance value of the resistor 17 is R 17 . The differential amplifier 13 of the same type as the above differential amplifier 12 operates in the same manner, and the contact 27
If the voltages V 27 and V 25 of V and 25 are V 27 <V 25 , the differential amplifier 13 is basically in the OFF state, and if V 27 > V 25 , the resistor 18 is connected to the differential amplifier 13 via the contact 27. A current I 18 flows toward the output terminal (the emitter of the transistor 1311). This current can be expressed by the following equation, assuming that the resistance value of the resistor 18 is R 18 .

I18=(V27−V25)/R18 ……(2) 更に、上記の差動増幅器12と同一形式の差動増幅器14に
ついても同様に動作し、接点27と26の電圧V27とV26がV
27<V26の場合、差動増幅器14は基本的にオフ状態にな
り、V27>V26の場合、抵抗19には接点27から差動増幅器
14の出力端に向けて電流I19が流れる。この電流は、抵
抗19の抵抗値をR19と仮定すると、下式のように表すこ
とができる。
I 18 = (V 27 −V 25 ) / R 18 (2) Further, the differential amplifier 14 of the same type as the above differential amplifier 12 operates in the same manner, and the voltage V 27 of the contacts 27 and 26 becomes V 26 is V
When 27 <V 26 , the differential amplifier 14 is basically turned off, and when V 27 > V 26 , the differential amplifier 14 is connected from the contact 27 to the resistor 19.
A current I 19 flows toward the output terminal of 14. This current can be expressed by the following equation, assuming that the resistance value of the resistor 19 is R 19 .

I19=(V27−V26)/R19 ……(3) 従って、入力端子15から入力される入力電圧が接地電位
がら徐々に大きくなると、基準電位の低い差動増幅器14
から順に13,12にと、第2の差動増幅器が順番に動作状
態になり、各第2の差動増幅器12〜14と第1の差動増幅
器11の出力端27との間に接続された抵抗17〜19に流れる
電流が、第1の差動増幅器11の出力電流に加算されるこ
とになる。このことから、第1の差動増幅器11の出力電
流I27は、接点27の電圧レベルに応じて次のように変化
する。
I 19 = (V 27 −V 26 ) / R 19 (3) Therefore, when the input voltage input from the input terminal 15 gradually increases from the ground potential, the differential amplifier 14 with a low reference potential is used.
The second differential amplifiers are sequentially activated in the order from 13 to 12, and are connected between the second differential amplifiers 12 to 14 and the output terminal 27 of the first differential amplifier 11. The current flowing through the resistors 17 to 19 is added to the output current of the first differential amplifier 11. From this, the output current I 27 of the first differential amplifier 11 changes according to the voltage level of the contact 27 as follows.

V25>V27>V26の時 I27=I19 ……(4) V24>V27>V25の時 I27=I19+I18 ……(5) V27>V24 の時 I27=I19+I18+I17 ……(6) 第1の差動増幅器11の出力電流は、トランジスタ114の
エミッタ電流であり、トランジスタ114のコレクタ電流
とほぼ等しく、抵抗111に流れる電流I111はI111=I27
考えて良い。この抵抗(第1の抵抗)111の端子間から
本回路の出力電圧を取り出すと、第2図に示すような入
力電圧に対して非線形に変化する出力電圧V111が得られ
る。第2図における出力電圧V111の変極点VOUT1とVOUT2
は次式となる。
When V 25 > V 27 > V 26 I 27 = I 19 …… (4) When V 24 > V 27 > V 25 I 27 = I 19 + I 18 …… (5) When V 27 > V 24 I 27 = I 19 + I 18 + I 17 (6) The output current of the first differential amplifier 11 is the emitter current of the transistor 114, which is almost equal to the collector current of the transistor 114, and the current I 111 flowing through the resistor 111 is You can think of I 111 = I 27 . When the output voltage of this circuit is taken out from between the terminals of this resistance (first resistance) 111, an output voltage V 111 that changes non-linearly with respect to the input voltage as shown in FIG. 2 is obtained. Inflection points V OUT1 and V OUT2 of the output voltage V 111 in FIG.
Is given by

VOUT1=(V25−V26)R111/R19 VOUT2=(V24−V26)R111/R19 +(V24−V25)R111/R18 ここで、温度特性について考えてみると、基準電圧端子
16の電圧V16が安定で、各抵抗が同一材質であれば、電
位の異なる基準電位V24〜V26の設定は安定となり、差動
増幅器を用いた各ボルテージホロワは入出力の利得を一
定に保つので、例え、抵抗17〜19に流れる電流I17〜I19
が抵抗の温度特性に依存して変化しても、出力電圧V111
は抵抗17〜19と抵抗111の相対比によって温度補償さ
れ、周囲温度に対して安定に動作する。
V OUT1 = (V 25 −V 26 ) R 111 / R 19 V OUT2 = (V 24 −V 26 ) R 111 / R 19 + (V 24 −V 25 ) R 111 / R 18 Here, consider the temperature characteristics. Looking at it, the reference voltage terminal
If the voltage V 16 of 16 is stable and the resistors are made of the same material, the setting of reference potentials V 24 to V 26 with different potentials will be stable, and each voltage follower using a differential amplifier will provide input / output gain. Since it is kept constant, for example, the current I 17 to I 19 flowing through the resistors 17 to 19
Of the output voltage V 111
Is temperature-compensated by the relative ratio of the resistors 17 to 19 and the resistor 111, and operates stably with respect to the ambient temperature.

なお、本実施例は、第1の差動増幅器11及び第2の差動
増幅器12〜14を構成するトランジスタを各々逆極性のト
ランジスタを用いて構成することは可能であり、同様の
効果が得られることは言うまでもない。
In this embodiment, the transistors forming the first differential amplifier 11 and the second differential amplifiers 12 to 14 can be formed by using transistors of opposite polarities, and the same effect can be obtained. It goes without saying that it will be done.

発明の効果 以上のように本発明によれば、温度変化に対して安定に
動作し、入力電圧の変化に対して非線形に変化する出力
電圧を得る非線形増幅回路が実現できる。
EFFECTS OF THE INVENTION As described above, according to the present invention, it is possible to realize a non-linear amplifier circuit that operates stably with respect to temperature changes and obtains an output voltage that changes non-linearly with respect to changes in the input voltage.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明に係わる一実施例の非線形増幅回路の回
路構成図、第2図は第1図の回路における入出力特性
図、第3図は非線形増幅回路の従来例の回路構成図であ
る。 11……第1の差動増幅器、12〜14……第2の差動増幅
器、15……入力端子、16……基準電圧端子、17〜23,11
1,1201〜1204,1301〜1304……抵抗、112〜114,1205〜12
07,1305〜1307……NPN型トランジスタ、115,116,1208〜
1211,1308〜1311……PNP型トランジスタ、117,1212,131
2……定電流源、Vcc……電源電圧端子。
FIG. 1 is a circuit configuration diagram of a non-linear amplifier circuit according to an embodiment of the present invention, FIG. 2 is an input / output characteristic diagram of the circuit of FIG. 1, and FIG. 3 is a circuit configuration diagram of a conventional non-linear amplifier circuit. is there. 11 ... First differential amplifier, 12-14 ... Second differential amplifier, 15 ... Input terminal, 16 ... Reference voltage terminal, 17-23, 11
1,1201 to 1204,1301 to 1304 ... Resistance, 112 to 114,1205 to 12
07,1305〜1307 …… NPN type transistor, 115,116,1208〜
1211,1308〜1311 …… PNP type transistor, 117,1212,131
2 ... Constant current source, Vcc ... Power supply voltage terminal.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】一導電型トランジスタの差動対と、同差動
対の出力にベースを接続しコレクタに第1の抵抗を接続
した一導電型の出力用トランジスタとを有し、同出力用
トランジスタのエミッタ出力を前記差動対の反転入力端
に帰還結合してなる第1の差動増幅器と、 逆導電型トランジスタの差動対の出力をエミッタホロワ
構成で出力し、そのエミッタホロワ出力を前記逆導電型
トランジスタの差動対の反転入力端に帰還結合してなる
第2の差動増幅器の複数構体とを備え、 前記複数構体の各反転入力端と前記出力用トランジスタ
のエミッタ出力の間に夫々個別の低抗体を接続し、前記
複数構体のエミッタホロワ出力に夫々異なる基準電位を
入力すると共に、前記第1の差動増幅器の非反転入力端
に入力信号を与え、前記第1の抵抗の端子間から出力電
圧を取り出すことを特徴とする非線形増幅回路。
1. A differential pair of one conductivity type transistors, and a single conductivity type output transistor having a base connected to the output of the differential pair and a first resistor connected to the collector, A first differential amplifier in which the emitter output of the transistor is feedback-coupled to the inverting input terminal of the differential pair, and the output of the differential pair of the reverse conductivity type transistor is output in an emitter follower configuration, and the emitter follower output is output in the reverse direction. A plurality of structures of a second differential amplifier, which are feedback-coupled to the inverting input ends of the differential pair of conductivity type transistors, and are respectively provided between the inverting input ends of the plurality of structures and the emitter output of the output transistor. Individual low antibodies are connected, different reference potentials are input to the emitter follower outputs of the plurality of structures, an input signal is applied to the non-inverting input terminal of the first differential amplifier, and terminals of the first resistor are connected. Nonlinear amplification circuit, characterized in that taking out et output voltage.
JP61152505A 1986-06-27 1986-06-27 Non-linear amplifier circuit Expired - Lifetime JPH0722250B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61152505A JPH0722250B2 (en) 1986-06-27 1986-06-27 Non-linear amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61152505A JPH0722250B2 (en) 1986-06-27 1986-06-27 Non-linear amplifier circuit

Publications (2)

Publication Number Publication Date
JPS639215A JPS639215A (en) 1988-01-14
JPH0722250B2 true JPH0722250B2 (en) 1995-03-08

Family

ID=15541924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61152505A Expired - Lifetime JPH0722250B2 (en) 1986-06-27 1986-06-27 Non-linear amplifier circuit

Country Status (1)

Country Link
JP (1) JPH0722250B2 (en)

Also Published As

Publication number Publication date
JPS639215A (en) 1988-01-14

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