JPH0722293B2 - QPSK carrier recovery synchronization detection device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to QPSK (quadrature phase modulation) QPSK signal demodulation.
The present invention relates to a carrier recovery synchronization detecting device.

2. Description of the Related Art Conventionally, when synchronously detecting a QPSK signal, it is necessary to reproduce a carrier wave, and a carrier wave recovery loop by a phase lock loop (PLL) is often required to have a reproduction capability over a wide frequency range. In such a case, a synchronization detection circuit is provided in the carrier recovery loop to control the input frequency in an asynchronous state or sweep the voltage controlled oscillator to artificially expand the synchronization frequency range.

In general, a signal obtained by 90-degree phase shifting of the control voltage signal of the voltage controlled oscillator, which is the phase error voltage of the loop, is used for PLL synchronization detection. Now, when the error voltage is given by sinφ, the signal used for synchronization detection is cosφ. When the loop is synchronous, φ = 0 and cosφ = 1, and when asynchronous, the random phase is φ = 0 to 2π, and the average value of cosφ is 0. Synchronous and asynchronous detection is performed by this signal.

FIG. 2 shows a block diagram of a conventional example in which a sync detection circuit is provided in a QPSK carrier recovery circuit by a Costas loop. Less than,
Description will be given with reference to the drawings. 1,2 are detectors, 3,4 are low pass filters, 5,6,13,14 are squarers, 7,15 are subtractors,
Reference numerals 8 and 9 are multipliers, 10 and 16 are low-pass filters, 11 is a voltage controlled oscillator, 12 is a 90-degree phase shifter, and 17 is a voltage comparator. Here, the QPSK signal input is E · (a cosωt + b sinωt) (a, b = ± 1, E is the amplitude of the QPSK signal), and the reproduced carrier waves are in-phase and quadrature cos (ωt + φ) and sin (ωt + φ), respectively.

The input QPSK signal is detected by the in-phase and quadrature regenerated carriers by the detectors 1 and 2, and their outputs are respectively the low-pass filter 3 and
The high frequency components are removed at 4 and the following signals are obtained.

In-phase component E (a sin φ + b cos φ) Quadrature component E (a cos φ-b sin φ) These signal components are squared by squarers 5 and 6, respectively, and subtracter 7 subtracts the squared components, and subtracter 7 2E ² · sin to the output of
A signal of 2φ is obtained. The output of low-pass filters 3 and 4 are multiplied together in a multiplier 8, the output E ^2/2 ·
It becomes cos2φ. The output of the multiplier 8 and the output of the subtractor 7 are multiplied by the multiplier 9, and the output becomes E ⁴ · sin4φ which is a function of the phase error φ, and this signal is passed through the low pass filter 10,
The output signal controls the voltage controlled oscillator 11 to reproduce the carrier wave.

The output of the multiplier 8 is squared by the squarer 14 and the output thereof is subtracted from the output signal of the squarer 13 by the subtracter 15. This output signal becomes E ⁴ cos 4φ, and the above phase error voltage E ⁴ sin4φ
The phase difference is 90 degrees. When this output signal is input to the low-pass filter 16 and the loop is synchronized, φ = 0, and the output of the low-pass filter 16 becomes E ⁴ , and φ = when asynchronous.
It takes a random phase of 0 to 2π, and the output becomes 0 on average. This output signal is compared with the reference voltage by the voltage comparator 17 to obtain the synchronization detection signal. During the reference voltage of the voltage comparator 0 and E ^4, i.e. synchronized by providing around E ^4/2, it is an asynchronous identification.

[For example, Digital Communications
communications) pp306−307K.Feher1983 Prentice Hal
l] Problems to be Solved by the Invention However, in the above configuration, the number of parts is large,
In addition, because the threshold of the voltage comparator is fixed, if the amplitude of the input signal or the output of the voltage controlled oscillator decreases, the input E ⁴ of the voltage comparator in the synchronous state may fall below the threshold and the synchronous detection Can not be.

For example, if the threshold value and E ^4/2 which is an intermediate of 0 and E ^4, the reduction in amplitude is 1.5 dB, the input of the voltage comparator 17 will be reduced 6dB of the fourth power, threshold Below the value.

As described above, the conventional example has a problem that the configuration is complicated and is unstable with respect to the level fluctuation of the detection signal.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a QPSK carrier recovery synchronization detecting device which has a simple structure and can stably obtain a synchronization detection signal even when the detection level changes.

Means for Solving the Problems In order to solve the above problems, the present invention detects a detection level, applies a threshold value controlled by this detection signal to a voltage comparator as a reference voltage signal, and changes the input level. Alternatively,
By making the reference voltage follow the level change of the output of the voltage controlled oscillator, it is possible to realize reliable determination of synchronization.

Effect The present invention realizes stable synchronous detection even with respect to the fluctuation of the detection signal level by generating a reference voltage that follows the fluctuation of the level of the detection signal and comparing this reference voltage with the E ⁴ cos 4φ component. There is. Moreover, the structure is simplified.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the QPSK carrier recovery synchronization detecting apparatus of the present invention.

Hereinafter, description will be given with reference to the drawings. 18 is a level detector and 19 is a threshold value setting device. As the carrier wave reproduction loop, the Costas loop shown in the conventional example is used. The detected signal components are multiplied by each other in the multiplier 8, and the output thereof is squared. This squared output signal is the QP shown in the conventional example.
Given the SK signal, a ^{1/2 · E 4 8 (1 +} cos4φ).

This signal is synchronized by the low pass filter 16 (φ = 0
It becomes E ^{4 in} degrees and becomes 1/2 · E ^{4 in} asynchronous (φ = 0 to 2π).

The output of the low pass filter 3 is also input to the level detector 18 to detect the level E of the detection signal. This output is input to the threshold setter 19. The threshold setter has a function of obtaining an output 3/4 · E ⁴ with respect to the input E. In this way, the threshold value is controlled so as to follow the fluctuation of the detection level and become the median value of the input voltage to the voltage comparator during synchronization and the input voltage to the voltage comparator during asynchronous.

In the conventional example, by squaring the output of the subtracter ^{7 1/2 · E 4 · (1} -c
os4φ) was generated and subtracted from the output signal of the squarer 14 to cancel the DC term and obtain 1 / 2E ⁴ cos4φ, but in the present embodiment, the reference voltage of the voltage comparator is It is controlled to the median synchronization when the input voltage is not necessary, except for the DC term of 1/2 · E ⁴ for that. For this reason, the squarer 13 and the subtractor 15 are not required as compared with the conventional example because of the structure for obtaining the synchronization detection signal. In addition, an inverse modulation method or 4
If the frequency multiplication method is used, the carrier recovery loop has a squarer 5,
Since 6 is not included, the squarers 5 and 6 are also unnecessary.

As described above, according to the present invention, by detecting the detection level and controlling the reference voltage signal of the voltage comparator, it is possible to operate stably even with respect to fluctuations in the detection level, and E ⁴ / 2
Since (1 + cos4φ) can be used as the synchronization detection signal, the synchronization detection device can be realized with a simpler circuit scale. In the embodiment, the carrier reproduction loop by the Costas loop is taken as an example, but other reproduction methods such as an inverse modulation method and a quadruple multiplication method can be applied.

[Brief description of drawings]

FIG. 1 is a block diagram of a QPSK carrier recovery synchronization detecting apparatus according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional QPSK carrier recovery synchronization detecting apparatus. 1,2 …… Detector, 3,4,10,16 …… Low pass filter, 8,9
…… Multiplier, 5,6,13,14 …… Square multiplier, 11 …… Voltage controlled oscillator, 17 …… Voltage comparator, 18 …… Level detector, 19 ……
Threshold setter.

Claims (1)

[Claims] 1. At least two detection means for detecting an in-phase component and a quadrature component, a first multiplication means for obtaining a product of outputs of the two detection means, and a squaring means for obtaining a squared component of the output. Level detecting means for detecting the output level of either one of the detecting means, threshold setting means controlled by this output signal, and voltage comparing means for inputting the output of the squaring means with the output thereof as a reference voltage. A QPSK carrier recovery synchronization detection device configured to include a synchronization detection signal at the output of the voltage comparison means.