JPH0722316B2 - Image information line buffer device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image information line buffer device used in a facsimile machine or the like.

2. Description of the Related Art In the image information line buffer device used in a conventional facsimile apparatus, the flow of image information is read from the reading section to the encoder,
It has been fixedly selected by hardware such as decoder → recording unit, and it was not possible to directly input / output image information to / from the bus of a microcomputer (MPU). In the conventional image information line buffer device, the number of lines and the capacity per line are fixed.
Further, the conventional image information line buffer device is separated from the character generator.

As described above, the configuration of the conventional image information line buffer device lacks flexibility regarding input / output of image information, and is compatible with future diversification and sophistication of image information processing functions of facsimile devices. Can not. Further, the composition of the character image information is poor in flexibility, and is limited to only composition with specific input image information or output image information. Furthermore, since the number of lines and the capacity per line are fixed as described above, separate image information line buffer devices must be prepared for variable speed binary image information and constant speed gradation image information. It is uneconomical.

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned conventional problems and provide a line buffer device capable of flexibly coping with input / output of various image information such as a facsimile device.

Means for Solving the Problems In order to achieve the above object, the present invention provides an input / output control unit for inputting / outputting image information to / from a reading unit, a recording unit, and an image information line buffer whose total capacity is defined in advance. Storage means, a control register section for holding control information relating to address exchange for the storage means, and a capacity per line of image information transferred to the storage means in accordance with the control information held in the control register section. And a line buffer control unit for executing reading and writing of image information transferred through the input / output control unit in units of the capacity per line, and the control information held in the control register unit. Is variably settable through a bus connected to an external microcomputer.

According to the present invention, with the above configuration, the storage means whose total capacity is defined in advance can be set as a line buffer device having different capacities per line by an external microcomputer according to the model such as a facsimile device. It is possible to flexibly handle input and output of various image information.

Embodiment FIG. 1 is a schematic block diagram showing the overall configuration of an image information line buffer device according to an embodiment of the present invention.

In the figure, 1 is a general-purpose microcomputer (MPU) of a facsimile machine, 2 is a control register unit, 3 is an input / output control unit, 4 is a line buffer control unit, 5 is a character generation unit,
Reference numeral 6 is a line buffer RAM (BRAM), and 7 is a direct memory access control unit (DMAC).

201, 202, 203, 301, 309, 501, 502, 503 are registers, which are directly connected to the MPU bus S1. 504 is RAM for character code buffer
(CRAM) and is directly connected to the MPU bus S1. S2 ~ S
6, S8 to S10 and S11 to S22 will be described later.

The block diagram in Figure 1 mainly focuses on registers,
Details of each part will be shown later.

This image information line buffer device, under the control of MPU1,
By reading / writing the register directly connected to the MPU bus S1, the input / output control of the image information, the control of the generation of the character image information and the combination with the image information, the switching of the line buffer configuration, etc. are performed.

That is, in the control register unit 2, the CRO register 201 and the CR1 register 202 are used to set the line buffer mode and the like.
Further, the iRQ register 203 is used to set the enable of the interrupt signal S10 to the MPU1 when an interrupt factor occurs in the image information line buffer device and to respond to the boring at the time of interrupt processing. In addition, with CRO register 201
It controls S2, S3, and S4 according to the contents of the CR1 register 202. S2 is a line buffer division signal bus. By this control, the division method of the memory space of BRAM6 is set, and 8 types of line buffers as shown in FIG. 15 are realized. S3 is a character image information composition method control bus. Is used to set one of the four types of combining methods shown in FIG. An example of composition by each composition method is shown in FIG. 17. Method (1) is a simple OR operation of image information and character image information, and method (2) is an exclusive OR operation of image information and character image information. The method (3) is a process of erasing the image information in a portion where the character image information exists and preferentially synthesizing the character image information, the method (4) prioritizes the character image information as in the method (3), and This is a process of inverting the character image information in black and white and combining them. S4 is a line buffer control bus, which includes one line enable signal (Line) for selecting image information input / output and inputting / outputting image information from the image information data register (DTR) 301. As shown in Fig. 18, 10 types of input / output modes can be selected. That is, as the input source of the image information or the character image information, any one of the reading unit, the decoder, the MPU bus S1 and the character generating unit 5 of the facsimile device can be selected, and the facsimile is output as the output destination of the image information or the character image information. Recorder of device, decoder, and MP
Either U bus S1 can be selected.

The input / output control unit 3 will be described with reference to FIG. FIG. 2 is a schematic block diagram showing an internal configuration of the input / output control unit 3.

The input / output control unit 3 includes an encoder / decoder dedicated input / output circuit 10,
Read-only input circuit 11, record-only output circuit 12, and MP
It consists of a U bus dedicated input / output circuit 13 (image information bus interface). Encoder / decoder dedicated input / output circuit 10
Is an output image information bus S11, an input image information bus S12, a reference output image information bus S13 (only in the case of two-dimensional encoding / decoding)
And an encoder / decoder interface bus S17. Further, the length of one line of the encoder / decoder is set by the contents of the LSR register 309, and the one line enable signal according to the one line length is output to the encoder / decoder interface bus S17. Selection of input operation and output operation of the encoder / decoder dedicated input / output circuit 10 and its start and stop are controlled by the line buffer control bus S4. The recording interface bus S18 is an output image information bus S by the recording-dedicated output circuit 12.
11 and the character generator interface bus S14. The start / stop of the recording dedicated output circuit 12 is controlled by the line buffer control bus S4. MPU
The operation of the bus dedicated input / output circuit 13 is controlled by the line buffer control bus S4 and the MPU bus S1, and the MPU bus S1, the output image information bus S11, the input / output image information bus S12, and the character generation are performed via the DTR register 301. Part interface bus S14
Generate and interface the signal. This MPU bus dedicated input / output circuit 13 is provided with an image information register data request signal S8,
The image information data DMA (direct memory access) request signal S15 and the DMA acceptance signal S16 are input and output, which will be described later. The read-only input circuit 11 takes an interface bus of a reading section interface bus S19, an input image information bus S12, and a character generating section interface bus S14, and its operation is controlled by a line buffer control bus S4.

The line buffer control unit 4 will be described with reference to FIG. FIG. 9 is a block diagram showing the outline of the internal configuration of the line buffer control unit 4. The line buffer control unit 4 uses the line buffer division signal bus S2 to specify the address of the BRAM 6 via the BRAM address bus S20, and the BRAM data bus S21. Circuit 21,
A read circuit 22 for reading, a reference read circuit 23 for reading a reference line required for two-dimensional encoding / decoding, a synthesizing circuit 24 for synthesizing character image information and image information, and each of these circuits on an internal bus. Control circuit 25 controlled through S25
Consists of. The control circuit 25 includes a line buffer control bus S4, a character generator interface bus S11, and an output image information bus S1.
4. Interfaces with the input image information bus S12 and the reference output image information bus S13, and outputs an input enable / output enable signal to each of the buses 11, 12, 13 to control the input / output of the image information of the input / output control unit 3. At the same time, it controls the line buffer room signal S6 for the control register unit 2 and the data direction signal S22 for the BRAM6. The reference read circuit 23 interfaces with the reference output image information bus S13 via the internal bus S25. Synthesis circuit 2
4 directly interfaces with the character image composition method control bus S3.

The character generation unit 5 is activated by the character generation enable signal S5, and controls the character generation position, character magnification, and line spacing as follows.

By setting the i RLR register 501, the sub-scanning clock is counted to determine the sub-scanning position.

ii The main scanning clock is counted by setting the CLR register 502 to determine the main scanning position.

iii Generate a character pattern (character image information) according to the character code stored in the CRAM beforehand. At that time, the enlargement ratio is controlled as shown in FIG. 20 according to the value of the PRO register 503. By reading the line feed code from the CRAM 504, or ending the scanning, or reading the last character code from the CRAM 504, the generation of the character pattern of one line is completed.

iv The above operations ii and iii are repeated for one line, and the character generation end signal S9 is turned on at the same time when the generation of one line is completed.

Line spacing as shown in FIG. 21 is generated according to the value of the v PRO register 503. The following character code is input to the CRAM 504 during this line spacing. When the input of this character code is completed, the character generation end signal S9 is reset.

When the occurrence of the line between vi ends, it repeats from ii again.

The above operation is repeated until the character generation enable signal S5 is turned off.

Fig. 22 shows an example of the character generation format.

The main scanning clock and the sub-scanning clock are generated by the input / output control unit 3, and the character generator interface bus S14
Is given to the character generator 5. The character generator 5 sends the generated character / image information and the character / image information enable to the control circuit 25 of the line buffer controller 4 via the same bus S14.

FIG. 3 is a detailed block diagram in which a part of the MPU bus dedicated input / output circuit 13 in FIG. 2 is omitted.

302 is a shift register for parallel / serial conversion of image information, 303 is a D flip-flop for state transition, and 304 is 3
It is a bit counter. Reference numeral 305 is a control gate circuit directly connected to the MPU bus S1, and 306 is an R / S flip-flop used as a data transfer request flag. 307 is an ungate, 308
Is PLA (Programmable Logic Array) S301 is PLA30
8 is a status signal bus that determines the current status of the PLA308, and S317 is a status signal bus that determines the next status of the PLA308. The signal relationship will be described later.

Fig. 4 shows PLA in the mode of inputting and outputting image information from MPU bus S1.
FIG. 5 is a state transition diagram of 308, and FIG. 5 is a diagram showing states of PLA output signals in respective states shown in FIG. ST1 is a standby state, ST2 is a state where the image information register data request signal S8 is turned on, ST3 is a data transfer waiting state of the DTR register 301, ST4 is a transfer state from the DTR register 301 to the shift register 302, and ST5 is an image information shift. The state, ST6 is a waiting state for completion of transfer to the line buffer, and ST7 is a one-line transfer end state.

Fig. 6 shows PLA30 in the mode of outputting image information to MPU bus S1.
8 is a state transition diagram of FIG. 8, and FIG. 7 is a diagram showing states of PLA output signals in respective states in FIG. ST1 is shown in Fig. 4.
The same standby state as ST1, ST8 is the image shift state, ST9 is the transfer wait state from the DTR register 301 to the MPU bus S1, ST10 is the transfer state from the shift register 302 to the DTR register 301, and ST11 is the one-line transfer end state. .

The operation in the MPU bus → line buffer (BRAM6) mode will be described with reference to FIGS.
The BUS RX signal S307 in the line buffer control bus S4 is turned on, and the PLA 308 waits in the ST1 state and turns off all the signals of S311 to S316.

The image information bus interface line enable (LINE) signal S305 in the line buffer control bus S4 is turned on,
When the line buffer image information input enable (OR) signal S303 in the input image information bus S12 is turned on, the PLA308 transitions to the ST2 state, and the transfer of one line starts. That is, the data transfer request flag set signal S312 is turned on to turn on the R / S flip-flop 3
Set 06 and turn on the image information register data request signal S8. The PLA 308 transits to the ST3 state and waits for the signal S8 to turn off.

When the image information is transferred from the MPU1 to the MPU bus S1, the control gate circuit 305 turns on the signal S323 to cause the image information (8 bits) on the MPU bus S1 to be latched in parallel in the DTR register 301, and the simultaneous signal S320 Turns on and R / S flip-flop 306
To reset.

When the image information register data request signal S8 is turned off by resetting the R / S flip-flop 306, the PLA 308 transits to the ST4 state. In ST4 state, the shift register load signal S315 is turned on and the bus 3 is transferred from the DTR register 301 to the shift register 302.
Image information is loaded in parallel via 26. at the same time,
The data transfer request flag set signal S312 is turned on, the R / S flip-flop 306 is set, and the image information register data request signal S8 is turned on to request the transfer of the next image information.

Then, the PLA 308 transits to the ST5 state, turns on the image information shift enable signal S316, causes the shift register 302 to perform the shift operation in synchronization with the internal clock S325, and also the counter.
Causes 304 to start the counter for internal clock S325. As a result, serial image information S319 from the shift register 302
Is output, sent to the line buffer control unit 4 via the input image information bus S12, and written in the BRAM 6. When carry signal S309 of counter 304 turns on, PLA 308 returns to the ST3 state. After this, until the LINE signal S305 turns off, PL
The A308 repeats the loop of ST3-ST4-ST5-ST3 to transfer the image information from the MPU bus S1 to the line buffer control unit 4.

When the signal S8 is on and the LINE signal S305 is off in the ST3 state, P
The LA 308 transits to the ST6 state, turns on the data transfer request flag reset signal S311 to reset the R / S flip-flop 306, and turns off the signal S8. And input image information bus S12
Wait for the upper line buffer input image information remaining (WTLR) signal S304 to turn off.

When the WTLR signal S304 turns off, the PLA 308 transits to the ST7 state, turns on the 1-line transfer end signal S314 on the line buffer control bus S4, and returns to the initial ST1 state.

In this way, image information transfer from the MPU bus to the line buffer is performed line by line.

Next, the image information transfer mode in the line buffer → MPU bus direction will be described with reference to FIGS. 3, 6, and 7.

In this transfer mode, BU in line buffer control bus S4
The STX signal S306 is turned on and the PLA 308 is waiting in the ST1 state. The LINE signal S305 turns on and the output image information bus S11
When the inside line buffer image information output enable (OR) signal S302 turns on, the PLA 308 transits to the ST8 state and turns on the image information shift M enable signal S316. As a result, the counter 304 starts counting the internal clock S325, and the serial image information S318 on the output image information bus S11 shifts to the shift register 302.
Is shifted in in synchronization with the internal clock S325. When the carry signal S309 of the counter 304 is turned on, the PLA 308 transits to the ST9 state if the image information register data request signal S8 is on, and the PLA 308 transits to ST10 if the signal S8 is off. The transition from the ST9 state to the ST10 state occurs by turning off the signal S8.

In the ST10 state, the PLA 308 turns on the DTR load signal S313 to load the image information in the shift register 302 into the DTR register 301 in parallel through the bus S326, and turns on the data transfer request flag reset signal S312 to turn on the R / S flip-flop. 3
Set 06 and turn on the image information register data request signal S8. After that, the PLA 308 returns to the ST8 state. DTR register
The image information in 301 is output to the MPU bus S1 through the bus S327 when the signal S321 from the control gate circuit 305 turns on.

Until the LINE signal S305 turns off, PLA308 keeps ST8 (± ST9) −
By repeating the state transition of ST10-ST8, conversion of the serial image information S318 from the line buffer into parallel data (8 bits) and output to the MPU bus S1 are performed.

In any of ST8, ST9, ST10, LINE signal S305
When turns off, the PLA308 immediately transitions to the ST11 state,
By turning on S311 and resetting the R / S flip-flop 306, the image information register data request signal S8 is turned off, and at the same time, the 1-line transfer end signal S314 is turned on and ST1
Return to the state.

When the image information transfer is performed in the program mode, when the register select and read / write signals are given from the MPU bus S1 via the bus S328, the control gate circuit 305 causes the signal S323 or the signal S321 and the signal S320. Turn on.

On the other hand, when transferring image information in the DMA mode, the image information register data request signal S8 is sent to the AND gate 30 when the DMA enable signal S324 in the line buffer control bus S4 is turned on.
The image information data DMA request signal S15 is sent from 7 to the DMAC7. This image information data DMA request is accepted by DMAC7, and DM
When the A acceptance signal S16 turns on, the control gate circuit 305 turns on the signal S320 and the signal S323 (when the BUSRX signal S307 is on) or the signal S321 (when the BUSTX signal S306 is on). Image information data DMA request signal in this DMA mode
The timing of S15, the DMA acceptance signal S16, and the MPU bus S1 is shown in FIG.

FIG. 10 is a detailed block diagram showing the internal configuration of the address control circuit 20 (FIG. 9) in the line buffer control unit 4.

405 is an input line select (WLS) counter, 406 is an output line select (RLS) counter, and 407 is a reference output line select (RFLS) counter, all of which are 4-bit counters. 408 is an input line address (WLA) counter, 409 is an output line address (RLA) counter, 410 is a reference output line address (RFLA) counter, and these are 10-bit counters. The control circuit 25 increments or resets these counters through the internal bus S25. 411 and 412 are selectors. The selector 411 selects one of the output bus S411 of the WLS counter 405, the output bus S412 of the RLS counter 406, and the output bus S413 of the RFLS counter 407 according to the line buffer mode selection signal S410 provided by the internal circuit S25 from the control circuit 25. Select and connect to the line select bus S414. The selector 412 selects one of the output buses S416, S417, and S418 of the WLA counter 408, RLA counter 409, and RFLA counter 410 according to the line buffer mode selection signal S410, and connects it to the line buffer address bus S415. All bits of the line select bus S414 are input to the line buffer division gate circuit 413.
Only the upper 2 bits of 415 are input to the same gate circuit 413,
The remaining lower 8 bits remain as they are in the BRAM address bus S20 (1
The lower 8 bits (3 bits). BRAM address bus S20
The upper 5 bits of are output from the gate circuit 413.

The WLS counter 405 and WLA counter 408 are for managing the line select and line address of the line buffer for the image information input mode, and the RLS counter 406 and RLA counter 409 are the line select and line for the image information output mode. Manage addresses. The RFLS counter 407 and the RFLA counter 410 manage the line select and line address of the line buffer for the reference output mode. Depending on the line buffer mode, the line buffer mode selection signal S410 controls the selectors 411, 412,
A corresponding counter is selected, a BRAM address is generated based on the value of the selected counter, and BRAM6 is accessed.

The line buffer division gate circuit 413 performs address conversion in eight different ways according to the line buffer mode division signal bus S2. In other words, the line buffer division signal bus S2 switches the addressing method of the BRAM 6 to eight types and switches the method of dividing the memory space of the BRAM 6. As a result, on the BRAM 6, it is possible to realize eight different line buffers as shown in FIG.

FIG. 11 is a circuit diagram showing a detailed configuration of the line buffer division gate circuit 413.

414 is a PLA (Programmable Logic Array), which is a signal depending on the value (m _{1 to} m ₈ ) of the line buffer division signal bus S2.
S430 to S438 are controlled and output as shown in FIG. First
In FIG. 12, a circle indicates a signal that turns on.

415 to 419 are gates. The logical sum signal of the signal S419 (the second upper bit of the line address bus S415) and the signal S435 and the logical sum signal of the logical product signal of the signal S421 (the least significant bit of the line select bus S414) and the signal S436 are gated. 41
5 is output as signal S425. Of the logical product signal of the signal S420 (most significant bit of the line address bus 415) and the signal S438, the logical product signal of the signal S421 and the signal S437, and the logical product signal of the signal S422 (the second bit of the line select bus 414) and the signal S436. The OR signal is output from the gate 416 as the signal S426. AND signal of signal S421 and signal S438, signal S422
The gate 417 outputs the logical product signal of the signal S437 and the logical product signal of the signal S432 (the third bit of the line select bus S414) and the signal S436. A signal S428 obtained by logically adding the logical product signal of the signals S422 and S434, the logical product signal of the signals S423 and S433, the logical product signal of the signal S424 (the most significant bit of the line select bus S414) and the signal S432 is output from the gate 418. . From gate 419, signal S423 and signal S4
The logical product signal of 31 and the logical sum signal S429 of the logical product signals of the signals S424 and S430 are output. The signals S425 to S429 are the upper 5 bits of the BRAM address bus S20, and the signal S429 is the most significant bit.

With such a configuration, a BRAM address (S20) is created for each value (m _{1 to} m ₈ ) of the line buffer division signal bus S2 by the method shown in FIG. The memory space is divided, and a line buffer having the number of lines and the capacity per line as shown in FIG. 15 is formed on the BRAM6. That is, in the m ₁ 8192 bit / line × 2 lines, m ₂ at 4096 bits / line × 4 lines, ..., line buffer configuration of m ₈ 4096 bits / line × 16 lines is made.

FIG. 14 is a detailed block diagram showing the internal structure of the synthesizing circuit 24 (FIG. 9).

401, 403, 404 are selectors, 402 is a composite logic gate, 40 is BRA
It is a line buffer created in M6. S401 is input image information from the input image information bus S12 and is input to the selector 401 via the internal bus S25. S402 and S405 are character image information and character image information enable (CPE) signals on the character generator interface bus S14, which are input to the synthesis logic gate 402 via the internal bus S25. S409 is a composite image information selection signal on the line buffer control bus S4, and the internal bus S25
Through selectors 401, 403, 404. S408 is line buffer input image information, and S403 is line buffer output image information, which are actually input / output to / from the BRAM 6 through the circuits 21 and 22 in FIG.

In cases other than the decoder interface → interface, the selector 401 controls the input image information bus S by the control of the composite image information selection signal S409.
Input image information S401 from 12 is selected, and composite input image information S404 is selected.
Is input to the synthesis logic gate 402. Synthetic logic gate 4
02 outputs image information obtained by synthesizing the synthetic input image information S404 and the character image information S405 as synthetic output image information S407. The contents of the combining process at this time are specified by the character image information combining system control bus S3 as described above. This composite output image information S4
07 is the line buffer input image information S40 by the selector 403
8 is selected and input to the line buffer 40. The line buffer output image information S403 is output by the selector 404.
It is selected as the output image information S318 to be output to the output image information bus S11.

In the case of decoding the two-dimensional sequential code, since the decoded image information is referenced again to decode the next line, the image information input from the decoder is directly combined with the character image information and placed in the line buffer 40. If so, the reference image information to be referred to in the next line will be in a form including the character image information, and decoding will be impossible. Therefore, in the case of the decoder interface, the selector 403 selects the input image information S401 (input image information from the decoder) as the line buffer input image information S408 and inputs it to the line buffer 40 as it is. Then, the line buffer output image information S403 for the line before the reference line of the current decoding line is selected by the selector 401 as the combined input image information S404, while the character image information S405 is selected.
And synthesize with. The composite output image information S407 is output as output image information S318 through the selector 404.

FIG. 19 is a block diagram showing the main and sub-scanning counter portions in the character generator 5 (FIG. 1).

Reference numerals 505 and 506 are sub-scanning counters (1) and (2). 507,5
08 and 509 are main scanning counters (1), (2) and (3). S501 is a reset signal for the sub-scanning counters (1) 505 and (2) 506, and S502 is a main scanning counter (1) 507, (2) 508,
(3) Reset signal of 509, S507 is sub-scanning clock, S503
Is the main scanning clock. These signals are provided by the character generator interface bus S14. S509 is 1 magnification
The setting signal, S510, is a magnification 2 setting signal, which is given from the PRO register 503 described above.

The sub-scanning counter (1) 505 counts the sub-scanning clock S507 with the value of the magnification 1 setting signal S509 as an initial value, and the carry signal S508 is counted by the sub-scanning counter (2) 506. The sub-scanning counter (2) 506 generates a row address for a character generator (not shown) in the character generator 5. The main scanning counter 507 counts the main scanning clock S503 with the value of the magnification 2 setting signal S510 as an initial value.
The main scanning counter (2) 508 carries the carry signal S of the main scanning counter (2) 508 with the value of the magnification 2 setting signal S509 as the initial value.
When 504 is counted, the carry signal S505 is counted by the main scanning counter (3) 509. The carry signal S506 of the main scanning position counter (3) 509 is a character clock,
Each time the character clock is output, the character code is sequentially read from the CRAM 504 and sent to the character generator.

With such a configuration, the raster scan type character image information (character pattern) can be enlarged, and the main and sub-scanning magnifications can be variously changed by setting the PRO register 503 as shown in FIG. . The sub-scanning magnification is determined by the product of the magnification 1 set by the magnification 1 setting signal S509, and the main scanning magnification by the product of the magnification 1 and the magnification 2 set by the magnification 2 setting signal S510.

To explain the operation, in the initial state, the reset signals S501, S
502 turns on and each counter is cleared. The sub-scanning counter (2) 506 indicates the first row. When the character generator enable signal S5 is turned on, the main scanning clock S503 enters the main scanning counter (1) 507, and the generation of the character image information for the first line starts. Main scan clock for carry signal S505
The frequency division ratio for S503 is 1 / (magnification 1 × magnification 2).
The main scanning counter (3) 509 performs column counting with the carry signal S505 and outputs the carry signal S506 (character clock) for each character. Therefore, main scanning magnification = magnification 1 × magnification 2. When the generation of the character image information for one line is completed in this way, the sub-scanning clock S507 is input to the sub-scanning counter (1) 505. The sub-scanning counter 506 continues to indicate the first row until the carry signal S508 is output, and the character image information of the first row of the character pattern is output on the lines between them. Sub-scanning clock for carry signal S508
The division ratio for S507 is 1 / magnification 1. Therefore,
Sub-scanning magnification = magnification 1.

EFFECTS OF THE INVENTION As is apparent from the above description, the present invention is provided with a control register unit that holds control information relating to address conversion of a storage unit whose total capacity is defined in advance, and this control information is connected to an external microcomputer. By enabling variable settings via the bus, it is possible to set line buffer devices with different capacities per line according to the model of the facsimile device, etc., and flexibly support input / output of various image information. In addition to making it possible to shorten the development period for new models such as facsimile machines,
It has an excellent effect that the price can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an overall configuration of an image information line buffer device according to an embodiment of the present invention, FIG. 2 is a schematic block diagram showing a configuration of an input / output control unit in FIG. 1, and FIG. A detailed block diagram of the MPU bus dedicated input / output circuit in FIG. 2, FIG. 4 is a state transition diagram of the PLA in FIG. 3, and FIG. 5 is a diagram showing signal control in each state in FIG. FIG. 6 is a state transition diagram in another mode of PLA in FIG. 3, FIG.
The figure shows the control of the signal in each state in FIG.
FIG. 8 is a timing diagram for explaining the timing of inputting image information in the DMA mode, FIG. 9 is a block diagram showing the configuration of the line buffer control unit in FIG. 1, and FIG. A detailed block diagram of the address control circuit, FIG.
Circuit diagram of the line buffer division gate circuit in the figure, FIG. 12 is a diagram showing the control of the output signal of the PLA in FIG. 11, and FIG. 13 is B
FIG. 14 is a diagram for explaining a method of generating a RAM address, FIG. 14 is a detailed block diagram of the synthesizing circuit 24 in FIG. 9, FIG. 15 is an explanatory diagram of line buffer division, and FIG. 16 is synthesizing character image information and image information. FIG. 17 is an explanatory view of the method, FIG. 17 is a view showing an example of composition by each composition method shown in FIG. 16, FIG. 18 is an explanatory view of input / output selection of image information, and FIG. 19 is a character generation part in FIG. FIG. 20 is a block diagram showing a part of the configuration of FIG.
FIG. 21 is an explanatory diagram of line spacing setting, and FIG. 22 is a diagram showing a format example of character generation. 1 ... General purpose microcomputer (MPU), 2 ... Control register section, 3 ... Input / output control section, 4 ... Line buffer control section, 5 ... Character generation section, 6 ... For line buffer
RAM (BRAM), 7 ... Direct memory access control unit (DMAC), S1 ... MPU bus, S2 ... Line buffer division signal bus, S3 ... Character image information composition method control bus, S4 ...
Line buffer control bus, S5 …… Character generation enable signal, S6 …… Line buffer empty signal, S8 …… Image information register data request signal, S9 …… Character generation end signal, S10 ……
Interrupt signal, S11 output image information bus, S12 …… input image information bus, S13 …… reference output image information bus, S14 …… character generator interface bus, S15 …… image information data DMA request signal, S16 …… DMA acceptance Signal, S17 ... Encoder / decoder interface bus, S18 ... Recording interface bus, S19 ... Reading interface bus, S20 ...
BRAM address bus, S21 …… BRAM data bus, S22 …… Data direction signal, 201,202,203,301,309,501,502,503 ……
Register, 504 ... RAM for character code buffer (CRAM).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shonori Oshima 2-3-8 Shimomeguro, Meguro-ku, Tokyo Within Matsushita Electric Transmission Co., Ltd. (72) Makoto Yamatani 1006 Kadoma, Kadoma-shi, Osaka Matsushita Electronics Industrial Incorporated (56) Reference JP 57-157687 (JP, A) JP 57-14247 (JP, A) JP 54-89521 (JP, A) JP 54-55329 (JP, A) European Patent Application Publication 55374 (1982.7.7)

Claims (1)

[Claims] 1. An input / output control unit for inputting / outputting image information to / from a reading unit, a recording unit, etc., a storage unit for an image information line buffer whose total capacity is defined in advance, and a control relating to address exchange for this storage unit. A control register unit for holding information, and a capacity per line of image information transferred to the storage unit is set according to the control information held in the control register unit and is transferred via the input / output control unit. Line buffer control means for executing reading and writing of image information according to the capacity per line, and the control information held in the control register section is variably set via a bus connected to an external microcomputer. An image information line buffer device characterized in that it is possible.