JPH0722319B2 - Image scanning clock generator in optical scanning device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image scanning clock generator in an optical scanning device, and more particularly to an image scanning clock generator in an optical scanning device having a rotary deflector as an optical deflecting means.

(Prior Art) An optical scanning device periodically deflects a light beam to form a scanning beam, and scans a predetermined scan target with the scanning beam,
It is known as a device for reading information on a surface to be scanned or writing information on the surface to be scanned.

Among such optical scanning devices, there is a system using a rotary deflector as means for periodically deflecting a light beam.

The rotary deflector is, for example, a device that deflects a light beam by rotating a rotary polygon mirror or a hologram disk having a linear diffraction grating formed by a hologram. When the light beam is deflected, the polarization of the light beam does not repeat exactly in the same period due to a manufacturing error of the rotating polygon mirror or the hologram disk or a mechanical error in mechanical rotation of these.

On the other hand, in the scanning of the surface to be scanned by the scanning beam, the starting point of the scanning region, that is, the starting point of the scanning by the scanning beam must be properly aligned. If the origins of the scanning areas are not aligned, the image distortion due to jitter occurs in the written image, or the image distortion due to jitter also occurs in the reproduced image of the read information.

One of the methods to align the starting points of scanning by the scanning beam is to install an optical sensor outside the scanning area, detect the scanning beam heading to the optical scanning area for each deflection, and generate a synchronization detection signal. There is a method in which a predetermined number of clocks of the image scanning clock are counted with reference to, and optical scanning is performed after the count is completed. That is, immediately after the synchronization detection signal is generated, the count of the image scanning clock is started, for example, the number of clocks for m clocks is counted, and the scanning is started at the (m + 1) th clock.

In the case of this method, since the image scanning clock is continuously generated, if the generation of the synchronization detection signal varies due to the error of the rotary deflector, the synchronization detection signal also varies with respect to the image scanning clock. If the clock is counted when the image scanning clock changes from the “low” state to the “high” state, the image scanning clock changes from the “low” state to the “high” state in the state where the synchronization detection signal is generated. Immediately before it changes, it is counted immediately for one clock, while when it occurs immediately after the sync detection signal changes from the "low" state to the "high" state of the image scanning clock, Since the subsequent change from the “low” state to the “high” state is counted as the first one clock, the starting point of the image scanning varies by one clock of the image scanning clock at the maximum.

The image scanning clock is a clock serving as a reference for optical scanning, and the width of one clock is one pixel for reading or writing in optical scanning. Therefore, in the above method, the starting point of optical scanning is one pixel. As a limit, the variation occurs, and a jitter corresponding to the variation occurs in the written image and the read and reproduced image. Image distortion due to jitter becomes more noticeable when the image is more than 1/2, which greatly impairs the aesthetic beauty of the image.

As a method for reducing the variation of the scanning starting point due to the scanning beam, there are conventionally known Japanese Patent Laid-Open Nos. 51-89346 and 56-126.
The method disclosed in Japanese Patent No. 378 is known.

However, in the former method, for example, in order to reduce the variation of the scanning start point to 1 / n or less, a reference clock having a frequency n times as high as the image scanning clock is required, and the effect of reducing the variation and the frequency of the reference clock remain unchanged. Since they are proportional to each other, the effect itself is limited by the feasible value of the frequency of the reference clock.

In addition, the latter method is affected by the operation tolerance of the delay element when actually implemented, and in order to obtain the desired effect, it is necessary to suppress the variation of the error. As a result, there is a problem that the cost becomes high.

(Purpose) The present invention has been made in view of the above-described circumstances, and the object thereof is to realize at low cost and yet to easily and surely reduce the variation of the scanning start point. The present invention provides an image scanning clock generator.

(Structure) Hereinafter, the present invention will be described in the case where the variation of the scanning starting point is set to 1 / n.

The image scanning clock generation device of the present invention includes a reference clock oscillator, a correction clock oscillator, a shift register, a latch circuit, and a clock selection circuit.

The reference clock oscillator generates a reference clock having the same frequency f as the image scanning clock.

The correction clock oscillator has N times the reference clock (N = n / 2; n
Generates a correction clock having a frequency of 2 or more.

The shift register receives the reference clock and the correction clock, and generates a plurality of types of clocks that are out of phase with each other at the frequency f.

The latch circuit, by the synchronization detection signal from the optical sensor,
The plurality of types of clocks are latched, and signals corresponding to the respective states of the plurality of types of latched clocks are output.

The clock selection circuit calculates the relative positions of the plurality of types of clocks and the synchronization detection signal based on the output of the latch circuit, and based on the calculation result, sets the relative position to a predetermined relative position among the plurality of types of clocks. Select a clock,
The selected clock is output as the image scanning clock.

Hereinafter, the operation of the present invention will be described with reference to the drawings.

First, refer to FIG. 1 to FIG.

In FIG. 1, the part surrounded by a chain line indicated by reference numeral 22 is
This is a device part that generates a plurality of types of clocks.

Now, in FIG. 1, from the reference clock oscillator 10,
A reference clock C _{0 of} frequency (equal to the frequency of the image scan clock) is generated. In addition, the correction clock oscillator 12
From N times the frequency of the reference clock C ₀ (N = n / 2, n
Are two or more natural numbers), and two correction clocks SCK ₁ and SCK ₂ are generated. These, reference clock C ₀ , correction clock SC
K ₁ and SCK ₂ are shown in FIG. Correction clock SCK ₁ ,
SCK ₂ has the same frequency in the example of this description, and its phases are 180 degrees out of phase with each other.

The reference clock C ₀ is applied to the shift registers 14 and 16. On the other hand, the correction clocks SCK ₁ and SCK ₂ are input to the shift registers 14 and 16, respectively.

Shift register 14, as shown in FIG. 2, based on the reference clock C ₀ to be input, corrected by the clock SCK _1, clock C ₁ of the frequency whose phase is shifted by one cycle width correction clock SCK _1, C ₃ , C ₅ …, C _n-1 are generated, and the shift register 16 uses the correction clock SCK ₂ to generate the same clock.
Clock with frequency shifted by 1 cycle width of SCK ₂
Generate C ₂ , C _4, ..., C _n . Note that n is treated as an even number here. When n is an odd number, shift register 14
Clock generated from C _1, C ₃ ..., a C _n, the clock generated from the shift register 16 is C _2, C _4, ..., a C _n-1.

Thus, the shift register 14, 16 to n kinds of clock C
₁ , C ₂ ..., C _n are obtained. These n kinds of clocks are the third
Shown in the figure. These n kinds of clocks C ₁ to C _n have a clock cycle T ₀ and a pulse width tw, and are out of phase with each other by Δto. This phase shift amount Δto is the correction clock SCK ₁ ,
Similar to the pulse width of SCK ₂ .

These clocks C _{1 to} C _n are input to the latch circuit 18 and the clock selection circuit 20.

The latch circuit 18 latches the input clocks C _{1 to} C _n with the synchronization detection signal from the optical sensor, and outputs the value of each clock in the latched state and its inverted value as Q ₁ ,
_It is output as ₁ to Q _n , _n and applied to the clock selection circuit 20.

Where Q _i , _i is the latched clock C _i (i = 1
.About.n) and its inverted value, Q _i = 1 and _i = 0 when the latched clock C _i is in the "high" state,
In the "low" state, Q _i = 0 and _i = 1.

The clock selection circuit 20 performs a predetermined arithmetic processing based on the input Q ₁ , _{1 to} Q _n , _n . This calculation process is
The purpose is to know the relative relationship between the synchronization detection signal and the clocks C _{1 to} C _n, and for example, from the inputs Q ₁ , ..., _n , Q
_{i i + 1} (i + 1 = 1 when i = 1 to n, i = n) is calculated.

In this way, when the relative relationship between the sync detection signal and the clocks C ₁ to C _n is known, the clock selection circuit 20 determines that the clock having the predetermined relative relationship with the sync detection signal. Is selected and is output as an image scanning clock. Thus, in this device, an appropriate image scanning clock is generated based on the synchronization detection signal.

A specific case of n + 6 will be described below with reference to FIG.

The six types of clocks C _{1 to} C ₆ shown in FIG. 4 have the same period as the image scanning clock, and the phases of the clocks are sequentially shifted by 1/6 period.

If these clocks are latched by the latch circuit with the synchronization detection signals as shown in FIG. ₄ , the states of the clocks C ₁ , C ₂ , C ₃ , C ₄ , C ₅ , C ₆ at this time are “ The states are "low", "low", "low", "high", "high", and "high". Therefore, the values of Q ₁ to _{n and} the values of Q _i · _{i + 1} are as shown in the following table.

As is apparent from this table, Q _{i i + 1} becomes 1 only in the case of Q _{6 1} , and 0 in other cases.
This synchronous detection signal is between the clock C ₆ and C _1,
That is, after the clock C ₆ goes "high",
It means that it occurred before the clock C ₁ went to the “high” state, which is exactly the same as in FIG.

In this way, when the relationship between the sync detection signal and the clocks C _{1 to} C ₆ is obtained, a clock having a fixed relative relationship with the sync detection signal is always selected as the image scanning clock.
The above fixed relative relationship can be arbitrarily selected, and therefore any clock may be selected. In the example of FIG.
The relative relationship is selected so that the clock that is in the "low" state immediately before the generation of the synchronization detection signal is selected. As shown in Fig. 4, the sync detection signals are clocks C ₆ and C ₁
, The clock C ₃ satisfies this relative relationship, and this clock C ₃ is selected as the image scanning clock. The image scanning clock is in a completely indeterminate state before the synchronization detection signal is generated, as shown in FIG. When the image scanning clock is selected by the synchronization detection signal, the line is scanned and the predetermined number of clocks are output, and then the image scanning clock is stopped. is there.

FIG. 5 is a block diagram of a circuit for selecting a clock that is in the “low” state immediately before the generation of the sync detection signal, in the example described with reference to FIG. It is composed of six AND circuits 4-1 to 4-6 and an OR circuit 4-7.

In this way, when the image scanning clock is selected, the variation of the scanning start point is suppressed to 1/6 pixel or less, but the frequency of the correction clock required for this is equal to the frequency of the image scanning clock. To 3
6/2 times.

By the way, when n clocks are obtained from the shift register, the frequency of the correction clock is n / n of the image scanning clock.
Since it is doubled, in general, when obtaining N clocks, the correction clock SCK ₁ or SCK ₂ is frequency-divided into N / 2 by a N / 2 divider as shown in FIG. if,
As it is, the reference clock C ₀ can be obtained. In other words, in this case, the correction clock oscillator and the N / 2 frequency divider can constitute the reference clock oscillator (where N is an even number in this case). In the N clocks C _{1 to} C _N obtained at this time, the ratio of the even-numbered and odd-numbered phase shift amounts is the ratio of the pulse widths of the correction clocks SCK ₁ and SCK ₂ . Then, the variation of the scanning starting point is caused by the correction clocks SCK ₁ and SC.
It is less than the pulse width of the clock with the wider pulse width of K ₂ .

To make the correction clocks SCK ₁ and SCK _{2 have} the same pulse width,
As shown in FIG. 7, if the reference clock for correction having a frequency twice that of the clock SCK (= SCK ₁ = SCK ₂ ) is divided into ½ frequency by the frequency divider, the correction clock SCK can be obtained. You can In this case, as shown in FIG. 8, the reference clock C ₀ and the correction clock are applied to the single shift register 24 to obtain the clocks C ₁ , C _2, ..., C _n. You can

(Effect) As described above, according to the present invention, a novel optical scanning device,
An image scanning clock generator can be provided. In this apparatus, even though the frequency of the correction clock for correction is N / 2 times the frequency of the image scanning clock, it is possible to suppress the variation of the scanning start point to 1 / N pixels or less.

Further, since a plurality of types of clocks are generated by the shift register, the phase accuracy of these clocks is high, the accuracy is higher than that of the delay line configuration, and the clock can be implemented at low cost.

Further, since the entire device can be configured as a digital device, it can be made into a digital gate array, which makes it possible to reduce the cost as an electrical system.

[Brief description of drawings]

1 to 3 are diagrams for explaining the present invention, FIGS. 4 and 5 are diagrams for explaining one embodiment of the present invention, and FIG. 6 is a reference clock in the present invention. FIG. 7 is a diagram for explaining one example of the oscillator, FIG. 7 is a diagram for explaining one example of the correction clock oscillator in the present invention, and FIG. 8 is a block diagram showing another embodiment of the present invention. C ₀ ... reference clock, SCK ₁ , SCK ₂ , SCK ... correction clock, C ₁ , C ₂ , ..., C _n ... clocks of the same frequency with mutually shifted phases, Q ₁ , ₁ , ..., _n ... ... clock C _1, ..., signals corresponding to C _n.

Claims (1)

[Claims] 1. A scanning beam which is provided outside a light scanning region and is directed to the light scanning region in an optical scanning device which periodically scans a light beam using a rotary deflector to optically scan a predetermined scan surface. A device for generating an image scanning clock on the basis of a synchronization detection signal from an optical sensor for detecting a reference clock oscillator, which generates a reference clock having the same frequency f as the image scanning clock, and N times (N) the reference clock. = N / 2; n is a correction clock oscillator that generates a correction clock having a frequency of 2 or more), the reference clock and the correction clock are input, and the pulse of the correction clock is input at the frequency f with reference to the reference clock. A shift register that generates a plurality of types of clocks whose phases are sequentially shifted by the width and a synchronization detection signal from the optical sensor cause the clocks of the plurality of types to be synchronized. Latch circuit that outputs a signal according to the state of each of the latched multiple types of clocks, and the relative position between the multiple types of clocks and the synchronization detection signal is calculated based on the output of the latch circuit. A clock selection circuit that selects a clock at a predetermined relative position with respect to the synchronization detection signal from among the plurality of types of clocks based on the calculation result, and outputs the selected clock as an image scanning clock. An image scanning clock generation device in an optical scanning device, comprising: