JPH0722395B2 - Motion vector detector - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motion vector detecting device for detecting a motion vector at high speed in motion compensation for encoding an image signal with high efficiency.

2. Description of the Related Art Image data has a large amount of information, which increases the cost of the transmission line in image transmission. Therefore, as a method of reducing the information amount of the image signal, there are techniques such as motion-compensated interframe coding and motion interpolation for interpolating a thinned frame using a motion vector. In order to realize these, a device for detecting a motion vector at high speed has been developed.

FIG. 2 is a block diagram of a conventional motion vector detecting device. In FIG. 2, 201 is a signal input terminal, 202 is an address counter, 203 is a count-up circuit, 204 is a first count latch, 205 is a first adder, 206 is a second adder, 20
7 is a frame memory, 208 is a distortion calculation circuit, 209 is a minimum distortion detection circuit, 210 is a second count latch, 211 is an address latch, and 212 is a signal output terminal.

The operation will be described below with reference to FIG. When a signal obtained by dividing one frame of an image signal into a plurality of blocks is input to the signal input terminal 201, the address counter 20
2 outputs an address value according to the input signal to the second adder 206. The count-up circuit 203 counts up three times in each of the horizontal direction and the vertical direction, four counts each, and then similarly counts three times, two counts each, and further three times, one count each. And the first adder 20
Output to 5. The first count latch 204 is a signal input terminal
When a signal is input to 201, a predetermined first count latch value is output, and when the second count latch value from the second count latch 210 is fetched, the fetched second count latch value is changed to the first count latch value. The value is output to the first adder 205. The first adder 205 includes a count-up value from the count-up circuit 203 and a first count latch 204.
The first count latch value from is added and output as the count address value to the second adder 206 and the second count latch 210. The second adder 206 adds the counter address value from the first adder 205 and the address value from the address counter 202 to obtain an absolute address value as the frame memory 20.
7 and output to address latch 211. Frame memory 207
Outputs an image signal corresponding to the absolute address value from the second adder 206 to the distortion calculation circuit 208. The distortion calculation circuit 208 calculates the absolute value of the difference between the input signal from the signal input terminal 201 and the image signal from the frame memory 207 for each pixel value, and obtains the sum. The minimum distortion detection circuit 209 sequentially compares the totals and, when giving the minimum distortion, outputs a minimum distortion recognition signal to the second count latch 210 and the address latch 211. Upon receiving the minimum distortion recognition signal from the minimum distortion detection circuit 209, the second count latch 210 reads the count address value from the first adder 205 and makes the count address value equal to the predetermined count number determined in advance. Then, the count address value that has been read is output to the first count latch 204 as the second count latch value. The address latch 211, when receiving the minimum distortion recognition signal from the minimum distortion detection circuit 209, reads the absolute address value from the second adder 206, and when the absolute address value is sent 27 times, the absolute read value is read. The address value is output as the motion vector to the signal output signal 212. (For example, "High Efficiency Coding Techniques in Image Transmission" Chapter 5 by Trikeps) Problems to be Solved by the Invention However, in the above method, since the entire motion vector search range is not searched, the first motion vector is erroneous. If detected, the true motion vector cannot be reached. Further, there is a demand for a motion vector detecting device having a higher speed.

In view of the above-mentioned problems, the present invention aims to increase the speed by reducing the processing of the distortion calculation by performing a rough search within the motion vector search range by further dividing into blocks during block matching.

Means for Solving the Problems In order to solve the above problems, a motion vector detection apparatus of the present invention uses a signal obtained by dividing one frame of an image signal into a plurality of blocks as an input signal, and the blocks in the current frame. A first blocking circuit for further dividing the converted input signal into blocks and accumulating a total value of image signals for each block; and an address corresponding to the input signal each time the input signal is added to the first blocking circuit. A first address counter that outputs an address value that is sequentially counted up from a value sign; a frame memory that stores the frame and outputs an image signal according to the address value from the first address counter; A second blocking circuit that performs blocking according to an output signal from the frame memory and accumulates a total value of image signals for each block; The second
Each time a block in the blocking circuit is updated, the absolute value of the difference between the total values of the blocks read from the first blocking circuit and the second blocking circuit is calculated, and the total of the absolute values is calculated. A first distortion calculation circuit for obtaining, a minimum distortion detection circuit that sequentially compares the sums and outputs a first minimum distortion recognition signal when minimum distortion is applied, and the first address when the first minimum distortion recognition signal is input. A first address latch that reads an address value from a counter and outputs the read address value as an address latch value when the address value becomes equal to a predetermined count number that is determined in advance; Outputs an address latch value, a second address counter that sequentially outputs a predetermined predetermined count value, and an output of the first address latch Address latch value and a counter value output from the second address counter are added as an address counter value, and the frame memory outputs an image signal corresponding to the address counter value from the adder. Then, a second distortion calculation circuit that calculates the absolute value of the difference of each pixel of the input signal in the current frame and calculates the sum thereof is sequentially compared with the second distortion calculation circuit to give the minimum distortion. When the second minimum distortion detection circuit for outputting the second minimum distortion recognition signal and the second minimum distortion recognition signal are input, the address counter value from the adder is read, and when the address counter value counts a predetermined number A second address latch for outputting the read address counter value as a motion vector is provided.

The present invention has the above-described configuration, by further dividing into blocks at the time of block matching, a rough search is performed in the motion vector search range, a temporary motion vector is detected, and then distortion calculation for each pixel is performed. Since the true motion vector can be detected, the processing for distortion calculation is reduced and the speed is increased.

Embodiment Hereinafter, a motion vector detecting device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the motion vector detecting device of the present invention. In FIG. 1, 101 is a signal input terminal, 102 is a first block circuit, 103 is a first address counter, 104 is a frame memory, 105 is a second block circuit, 106 is a first distortion calculation circuit, and 107 is a first distortion calculation circuit. 1 minimum distortion detection circuit,
108 is a first address latch, 109 is a second address counter, 110 is an adder, 111 is a second distortion calculation circuit, 112 is a second minimum distortion detection circuit, 113 is a second address latch, and 114 is a motion vector output terminal. is there.

The operation of the motion vector detecting device configured as described above will be described below with reference to FIG.

The signal S input from the signal input terminal 101 is divided into blocks of block size 4 × 4 as follows.

When the signal S is input from the signal input terminal 101 to the first blocking circuit 102, it is further blocked into a block size of 2 × 2, and after the signal T is converted as described below, it is sent to the first distortion calculation circuit 106. The signal T is output.

However, t ₁ = S ₁₁ ＋ S ₁₂ ＋ S ₂₁ ＋ S ₂₂ t ₂ ＝ S ₁₃ ＋ S ₁₄ ＋ S ₂₃ ＋ S ₂₄ t ₄ ＝ S ₃₁ ＋ S ₃₂ ＋ S ₄₁ ＋ S ₄₂ t ₄ ＝ S ₃₃ ＋ S ₃₄ ＋ S ₄₃ ＋ S ₄₄ First block When the input signal S is sent to the circuit 102, the first address counter 103 sends out address values that are sequentially incremented by 2 from the address value corresponding to the input signal S. Every time the frame memory 104 reads the address value, the following signals A are sequentially taken out from the previous frame.

The signal A from the frame memory 104 is the second blocking circuit 1
Each time it is input to 05, it is further divided into blocks of block size 2 × 2, and after converting the signal B as follows,
It is sent to the distortion calculation circuit 106. Once the block is formed, the elements b ₁ and b ₃ of the previous block are changed to the first block in the subsequent block formation.
Since the address counter 103 counts up by 2 counts and shifts by 2 pixels, the calculation is not performed by substituting the values of b ₂ and b ₄ .

However, b ₁ = a ₁₃ ＋ a ₁₄ ＋ a ₂₃ ＋ a ₂₄ b ₂ ＝ a ₁₅ ＋ a ₁₆ ＋ a ₂₅ ＋ a ₂₆ b ₃ ＝ a ₃₃ ＋ a ₃₄ ＋ a ₄₃ ＋ a ₄₄ b ₄ ＝ a ₃₅ ＋ a ₃₆ ＋ a ₄₅ ＋ a ₄₆ Second block When the circuit 105 makes a block, the signal B is sent to the first distortion calculation circuit 106. When the signal B is sent to the first distortion calculation circuit 106, the distortion d ₁ is obtained from the signal T from the first blocking circuit 102.

The distortion d ₁ thus obtained is sent to the first minimum distortion detection circuit 107. The first minimum distortion detection circuit 107 uses the same vector T for distortion d
_{When the} distortion d ₁ that is smaller than ₁ is sent, the distortion d ₁ is read, the first minimum distortion recognition signal is sent to the first address latch 108, and nothing else is done. The first address latch 108 receives the first minimum distortion recognition signal
The address value from the address counter 103 is read, and when the address value becomes equal to a predetermined count number that is determined in advance, the read address value is sent to the adder 110 as an address latch value. When the address latch value is sent to the adder 110, the second address counter 109 sequentially outputs a predetermined predetermined count value. The adder 110 adds the address latch value sent from the first address latch 108 and the count value sequentially sent from the second address counter 109, and sends it as an address counter value. The frame memory 104 sequentially outputs the signal A ′ corresponding to the address counter value sent from the adder 110 to the second distortion calculation circuit 111.

When the signal A ′ is sent to the second distortion calculation circuit 111, the distortion d ₂ is obtained from the signal S from the signal input terminal 101.

The distortion d ₂ thus obtained is sent to the second minimum distortion detection circuit 112. Second minimum distortion detecting circuit 112, when the distortion d ₂ is smaller distortion d ₂ than before sent in the same signal S is its distortion d ₂
Reading, when the distortion d ₂ of the same signal S is less distortion d ₂ is sent than before it reads the distortion d _2, the second address latch 113 sends a second minimum distortion recognition signal, otherwise Also do nothing. The second address latch 113 reads the address counter value from the adder 110 when the second minimum distortion recognition signal is sent, and is read when the address counter value becomes equal to a predetermined count number determined in advance. The address counter value is sent as a motion vector to the motion vector output terminal 114. In order to simplify the explanation, the signal input from the signal input terminal 101 is 4 × 4.
Is divided into blocks of the first blocking circuit 102.
Further, the second block forming circuit 105 is further divided into 2 × 2 blocks, the first address counter 103 counts up by 2 counts on the left and right, and the second address counter 109 counts by 1 count on the left and right. Is output, but the output is not limited to this.

EFFECTS OF THE INVENTION As described above, the present invention does not calculate the distortion for each pixel from the beginning at the time of block matching, but reduces the distortion calculation by calculating the distortion for each block after forming the blocks, thereby reducing the distortion within the vector search range. The search can be performed quickly, and the intra-block operation can be reduced by searching for each block width. Then, by performing distortion calculation for each pixel,
The motion vector can be detected accurately.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a motion vector detecting apparatus according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional motion vector detecting apparatus. 102 ... First block circuit, 103 ... First address counter, 104 ... Frame memory, 105 ... Second block circuit, 106 ... First distortion calculation circuit, 107 ... First minimum distortion detection circuit , 108 ... first address latch, 109 ... second address counter, 110 ... adder, 111 ... second distortion calculation circuit,
112 ... second minimum distortion detection circuit, 113 ... second address latch, 114 ... motion vector output terminal, 202 ... address counter, 203 ... count-up circuit, 204 ... first count latch, 205 ... 1st adder, 206 ... 2nd adder,
207 ... Frame memory, 28 ... Distortion calculation circuit, 209 ... Minimum distortion detection circuit, 210 ... Second count latch, 211 ... Address latch.

Claims (1)

[Claims] 1. A signal obtained by dividing one frame of an image signal into a plurality of blocks is used as an input signal, and the blocked input signal is further divided into blocks in the current frame to obtain a total value of image signals for each block. A first blocking circuit for accumulating, and a first address counter for outputting an address value sequentially counted up from an address value corresponding to the input signal every time the input signal is applied to the first blocking circuit. , A frame memory that stores the previous frame and outputs an image signal corresponding to the address value from the first address counter, and a block memory that performs block formation according to the output signal from the frame memory. A second blocking circuit that accumulates a total value;
Each time a block in the blocking circuit is updated, the absolute value of the difference between the total values of the blocks read from the first blocking circuit and the second blocking circuit is calculated, and the total of the absolute values is calculated. The first distortion calculating circuit for obtaining, the first minimum distortion detecting circuit for sequentially comparing the sums and giving the minimum distortion when the minimum distortion is given, and the first minimum distortion recognizing signal for inputting the first minimum distortion recognizing signal, A first address latch for reading the address value from the address counter and outputting the read address value as an address latch value when the address value becomes equal to a predetermined count number, which is previously determined; When the latch outputs the address latch value, a second address counter that sequentially outputs a predetermined count value, and the first address counter.
The address latch value output from the address latch and the second
When an adder that outputs a signal obtained by adding a counter value output from the address counter as an address counter value and the frame memory outputs an image signal corresponding to the address counter value from the adder, A second distortion calculation circuit that calculates the absolute value of the difference of each image of the input signal and sequentially calculates the sum, and outputs the second minimum distortion recognition signal when the total is sequentially compared and minimum distortion is given When the circuit and the second minimum distortion recognition signal are input, the address counter value from the adder is read, and the address counter value read when the address counter value is counted up to a predetermined count number. And a second address latch for outputting as a motion vector.