JPH0722414B2 - Black Jitter correction circuit - Google Patents

Description

The present invention relates to a digital video signal processing circuit having a time base correction circuit for TVs, VTRs and the like.

[Conventional technology]

Conventionally, in such a digital video signal circuit,
As described in "Dr. Takahashi, Doctor of Engineering, Supervision of Broadcasting by the Japan Broadcasting Corporation, Digital Broadcasting Technology, Digital Technology for Broadcasting PP163-175" In the circuit, the signal is processed with a clock that is n times as many as the subcarrier phase-locked to the burst signal. Then, writing is performed in a line memory having a storage capacity of one horizontal scanning period with a clock phase-locked with the burst signal.

On the other hand, when this memory is read, jitter is generated on the screen unless it is read with a clock that is phase locked to the horizontal sync signal. Prepare multiple taps on the variable analog delay line using
Phase adjustment is performed by varying the delay amount of the analog delay line according to the phase shift from the clock phase-locked to the burst signal.

[Problems to be solved by the invention]

The above-described conventional time-axis correction circuit that corrects the delay amount using the gate delay or the like has a drawback in that there are many delay variations and is unstable, and it is extremely disadvantageous in making an IC.

As is well known, in a standard NTSC signal, there is an interleaved relationship between the burst clock (frequency f _SC ) and the horizontal synchronization clock (frequency f _H ), and f _SC = (455 /
2) ・ The relationship of f _H is established. Therefore, there is no problem even without using the time axis correction circuit. However, the above relationship is often not established for video output from home VTRs and the like. Therefore, in order to perform processing such as double speed conversion and additional writing of character signals in units of horizontal synchronization, it is often easier to perform subsequent processing by re-sampling with the horizontal synchronization clock. Since the video signal is sampled with the clock synchronized with the burst signal, it is necessary to minimize the jitter in the time base conversion circuit that re-acquires the data with the clock locked with the horizontal synchronization signal.

It is an object of the present invention to provide a clock jitter correction circuit that adjusts the phase of the horizontal sync clock to the burst sync clock in units of horizontal sync.

[Means for solving problems]

The clock jitter correction circuit of the present invention is such that a horizontal synchronizing signal from a video signal, or a synchronous processing circuit for taking out an oscillation output synchronized with the horizontal synchronizing signal, and a phase locked to the output of the synchronous processing circuit, the frequency is nf _H (f _H : frequency of horizontal sync signal), a VCO that generates a clock, a first frequency divider that divides the VCO output by a frequency division ratio n, an output of the synchronization processing circuit, and a first frequency divider. A phase comparator circuit that takes the output as an input and outputs it to the VCO, a reset counter that takes the VCO output as an input and divides the input frequency by 1, and outputs the VCO output with a division ratio of 1
Burst signal is extracted from the second frequency divider that divides by and the video signal input, and the burst signal nf _H / (lf _SC ) (f
_SC : frequency of burst signal) Burst synchronization clock generation circuit that generates a clock that is phase-locked to the frequency, and the output of the first frequency divider is the first input, and the output of the second frequency divider is the second Input, and the output of the burst synchronization clock generator as the third input, and one pulse having a predetermined width is generated for each horizontal synchronization period from the first and second inputs, and the pulse is generated as the second pulse. It has a phase detection circuit which delays by a time corresponding to the phase difference between the input and the third input and outputs the delayed signal to the reset input of the reset counter.

Now, assuming that the sampling clock frequency is 4 f _SC ,
The period of one clock is about 70 ns. The value of 70 ns is a sufficiently high frequency as the sampling rate of the video input band, but is a value that can be sufficiently detected from the viewpoint of jitter. Usually, the detection limit of the jitter is said to 4 ns, in this case, the clock frequency is made possible by the digital processing after if 64 f _SC least a 16-fold 4 f _SC.

Therefore, when nf _H = 64 f _SC , l = 16, the jitter of the horizontal sync clock for sampling is below the detection limit,
By re-timing the horizontal synchronization clock with the burst synchronization clock, a horizontal synchronization clock phase-locked with the burst signal can be obtained, and the jitter can be digitally corrected.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 3 is a block diagram of a digital video processing device using an embodiment of the clock jitter correction circuit of FIG.

The clock jitter correction circuit 1 inputs the video signal, and the burst synchronization clock S2 having a frequency of 4 f _SC and the frequency synchronized with the burst synchronization clock S2 at every horizontal scanning period.
Outputs 910 f _H horizontal sync clock S1 with no jitter (jitter is below the detection limit). The A / D conversion circuit 20 inputs the video signal and performs A / D conversion using the burst synchronization clock S2 as a sample clock. The video processing circuit 21 processes the digital video signal output from the A / D conversion circuit 20 in synchronization with the burst synchronization signal S2. The time axis conversion circuit 22 resamples the data input from the video processing circuit 21 with the horizontal synchronization clock S1 output from the clock jitter correction circuit 1, and the data is re-sampled by the time axis processing circuit 23 in units of horizontal synchronization. It is processed. The D / A conversion circuit 24 D / A converts the output of the time axis processing circuit 23 and outputs the video. FIG. 1 is a block diagram of the clock jitter correction circuit 1 of FIG. 3, and FIG. 2 is a timing chart showing the operation of the circuit of FIG.

The synchronization processing circuit 2 extracts the horizontal synchronization signal from the video signal input. The phase comparator 3, VCO 4, and first frequency divider 6 form a PLL circuit that receives the output of the synchronization processing circuit 2 as an input. The oscillation frequency of VCO4 is 64 f _SC , and thus the frequency division ratio n of the first frequency divider 6 is 14560. Reset counter 5 is VCO
Input 4 output, divide frequency by 16 and output 910 f _H horizontal sync clock. Second frequency divider 7 is 16 divides the output of the VCO 4, the frequency outputs a clock of 910 f _H. The burst synchronization clock generation circuit 8 extracts the burst signal from the video signal input and outputs the burst synchronization clock S2 having a frequency of 4 f _SC (= 910 f _H ) phase-locked to the burst signal. The phase detection circuit 9 is composed of first and second D-type flip-flops (denoted as FF in FIG. 1) 10, 12 and an AND gate 11. The D input of the first D-type flip-flop 10 is connected to the output of the first frequency divider 16, and the C _P input is connected to the output of the second frequency divider 7. The two inputs of the AND gate 11 are connected to the output of the first frequency divider 6 and the output of the first D-type flip-flop 10, respectively. The second D-type flip-flop 12 is D
Input to the output of the AND gate 11, also, C _P input connected to the output of the burst synchronizing signal generating circuit 8,
The Q output is connected to the reset signal input R of the reset counter 5. In addition, the burst synchronization clock generation circuit 8
The output S2 is input to the A / D conversion circuit 20, the video processing circuit 21, and the time axis conversion circuit 22 as a clock.

Next, the operation of this embodiment will be described with reference to the time chart of FIG.

The horizontal sync signal with jitter extracted from the video signal input by the sync processing circuit 2 is input to the phase comparison circuit 3 of the PLL circuit. Since the cycle of the oscillation output S3 of VCO4 is about 4 ns, the output S1 of the reset counter 5 and the output S4 of the second frequency divider 7 contain no detectable jitter. The AND gate 11 outputs a horizontal gate clock S5 which becomes high level for one clock cycle T _R of a clock having a frequency of 910 f _{H in} one horizontal scanning period. Horizontal gate clock S5
Is the second flip-flop 12 is latched in standing each downlink negative logic C _P burst is input to the input synchronizing clock S2, as a result, the horizontal gate clock S5, is Torinaosa timing by the burst synchronization clock S2 And is output as a reset pulse S6. When the reset pulse S6 is input at time t ₁ , the reset counter 5 forcibly performs the reset operation, stops the counting operation only during the period when the reset pulse S6 is input, that is, the period T _R , and the reset pulse S6 is Counting is started again at the falling time t ₂ . Therefore, the output S1 of the reset counter 5 becomes an output frequency-locked to the horizontal synchronizing signal (frequency f _H ) and phase-locked to the burst signal after the reset is released. In this embodiment, the horizontal gate clock S5 is
Since the burst synchronization clock S2 is latched by the falling edge of the burst synchronization clock S2, the output of the phase detection circuit 9 corresponds to the time T _D corresponding to the phase difference between the burst synchronization clock and the horizontal synchronization clock from the horizontal gate clock S5 (T _R / 2) The phase is delayed by −T _D.

〔The invention's effect〕

As described above, according to the present invention, in a circuit that performs digital video processing of a video signal having a horizontal synchronizing signal that is not phase-synchronized with the burst signal, the signal is synchronized with both the phase of the burst signal and the phase of the horizontal synchronizing signal. By creating a clock whose phase is synchronized with the horizontal synchronization signal by the clock, the phase can be delayed corresponding to the time corresponding to the phase difference between the burst synchronization clock and the horizontal synchronization clock. Since jitter correction can be performed digitally without using it, there is an effect that the circuit can be downsized and stabilized.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a clock jitter correction circuit of the present invention, FIG. 2 is a timing chart showing the operation of the circuit of FIG. 1, and FIG. 3 uses the clock jitter correction circuit 1 of FIG. FIG. 3 is a block diagram of a digital video processing device that has been used. 1 ... Clock jitter correction circuit, 2 ... Synchronization processing circuit, 3 ... Phase comparison circuit, 4 ... VCO, 5 ... Reset counter, 6 ... First frequency divider, 7 ... Second minute Frequency divider, 8 ... Burst synchronization clock generation circuit, 9 ... Phase detection circuit, 10 ... First D-type flip-flop, 11 ... AND gate, 12 ... Second D-type flip-flop, 20 ... A / D conversion circuit, 21 ... video processing circuit, 22 ... time axis conversion circuit, 23 ... time axis processing circuit, 24 ... D / A conversion circuit.

Claims (1)

[Claims] 1. A synchronization processing circuit for extracting a horizontal synchronization signal or an oscillation output synchronized with the horizontal synchronization signal from a video signal, and a phase locked to the output of the synchronization processing circuit so that the frequency is nf _H (f
_H : VCO that generates the clock of the horizontal sync signal)
And a first frequency divider that divides the output of the VCO by the frequency division ratio n, and an input of the output of the synchronization processing circuit and the output of the first frequency divider,
A phase comparator circuit that outputs to the VCO, a reset counter that outputs the input of the VCO by dividing the input frequency by 1 and a second divider that divides the output of the VCO by a dividing ratio of 1 , A burst synchronous clock generation circuit for extracting a burst signal from a video signal and generating a phase locked clock at a frequency nf _H / (lf _SC ) (f _SC : burst signal frequency) times the burst signal, The output of the frequency divider is used as the first input, the output of the second frequency divider is used as the second input, and the output of the burst synchronization clock generator is used as the third input, and horizontal synchronization is performed from the first and second inputs. A phase for generating one pulse having a predetermined width for each period, delaying the pulse by a time corresponding to the phase difference between the second input and the third input, and outputting the delayed pulse to the reset input of the reset counter. A clock jitter correction circuit having a detection circuit.