JPH0723993B2 - Active matrix liquid crystal display - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device,
In particular, it relates to an active matrix liquid crystal display device in which a switching element is arranged in each pixel of the liquid crystal display device. 2. Description of the Related Art In an active matrix type liquid crystal display device, even if there is a defect in one gate bus to which the gates of MOS transistors of pixels in one horizontal row are commonly connected, a signal is displayed in a liquid crystal display cell. As a means to enable
For example, the one described in JP-A-58-144888 is known. That is, the gates of two transistors whose sources and drains are commonly connected to one pixel in the n-th row are
Even if the gate bus of the nth row is connected to the gate bus of the nth row, and the gate bus of the nth row has a defect, the pixel selection by the gate bus of the (n-1) th row results in the (n-1) th row. Display the pixels in a row so that they are not completely defective. Further, as to the defect of the drain bus in which the drains of the pixel MOS transistors in one column are connected in common, for example, the one described in Japanese Patent Laid-Open No. 58-143377 is known. That is, by connecting two adjacent drain buses to the MOS transistor of each pixel via a non-linear element each having a constant threshold value,
Even if there is a defect in a specific one row drain bus, the pixel is driven by the other drain bus. These methods are very effective in relieving horizontal or vertical defects due to defects in the gate bus and drain bus, but it is easy to detect defects in the switching transistor of each pixel. Nor is there any remedy for transistor short circuit defects. It is an object of the present invention to provide an active matrix type liquid crystal display device which can easily detect a pixel switching transistor defect and can repair the pixel defect. Means for Solving the Invention m extending approximately to the left and right
Pixel gate bus, n vertically extending drain buses, a pixel having a liquid crystal element and a switching element arranged at their intersections, and n scanning transistors for sequentially applying video signals to the n drain buses In the active-matrix liquid crystal display device including a horizontal scanning unit including, the n scanning transistors form a plurality of groups whose gate terminals are commonly connected every k, and k + 1 or more signal input terminals. And the drains (or sources) of the k scanning transistors in the same group are connected to k independent signal input terminals, and at least one of the k independent signal input terminals is A signal input terminal not used as a signal input terminal of the adjacent group was used. According to the present invention, two switching transistors are arranged in series in one pixel, the drain electrode and the gate electrode of each transistor are connected to different bus lines, and the on resistance of the transistors connected in series is increased. The off-state resistance and off-state resistance can be easily measured at the external terminal, and the defect of the switching transistor of each pixel can be detected. A transistor having a short circuit defect can be repaired by electrically disconnecting it from the liquid crystal cell. An embodiment of the present invention will be described below with reference to FIG. The MOS transistors MA _ij shown here,
MB _ij (i = 1 to m, j = 1 to n) are all of the same conductivity type, and will be described below as an N-channel MOS transistor, for example. Pixels composed of liquid crystal LC _ij corresponding to a unit pixel and switching MOS transistors MA _ij and MB _ij for addressing the liquid crystal LC _ij are arranged in a matrix of m rows and n columns, and a MOS transistor MB _ij belonging to the i-th row. And a MOS transistor M belonging to the (i + 1) th row
A gate bus Y _j is provided so that the gates of A _{i + 1, j} are common. However, the gate of the MOS transistor MA _1j is connected to the gate bus Y ₀ . Also, MOS
The sources of the transistors MA _ij and MB _ij are connected to the liquid crystal LC _ij drive electrode corresponding to each pixel, and belong to the j-th column MO.
The drain bus Xj is provided such that the S transistor MB _ij and the MOS transistor MA _{ij + 1} belonging to the (j + 1) th column have the same drain. However, the transistor MA _i1
Is connected to the drain bus X ₀ . Further, in the present embodiment, the liquid crystal element capacitance of each pixel is used as a substitute for the signal holding capacitance that continues to apply the video signal voltage to the liquid crystal when the MOS transistor of each pixel is in the off state. It may be connected in parallel with the liquid crystal. Next, a method of driving (scanning) the liquid crystal will be described. First, the gate bus Y _{0 is connected} to the MOS transistor MA.
_A video signal is applied to the drain buses X ₀ , X ₁ , ..., X _n while a positive selection voltage (hereinafter abbreviated as V _GON ) for turning on ₁₁ , MA ₁₂ , ..., MA _1n is applied. A video signal is written in the liquid crystal cells LC ₁₁ , LC ₁₂ , ..., LC _1n in the first row. Next, on the gate bus Y ₀ , MOS transistors MA ₁₁ ,
A non-selection voltage (hereinafter abbreviated as V _GOFF ) for turning off MA ₁₂ , ..., MA _1n is applied, a selection voltage V _GON is applied to the next gate bus Y ₁ , and MOS transistors MB ₁₁ , MB ₁₂ ,
, MB _1n and MA ₂₁ , MA ₂₂ , ..., MA _2n are turned on, and new video signals applied to the drain buses X ₀ , X ₁ , ..., X _n are supplied to the first and second rows. Liquid crystal cell L
C ₁₁ , LC ₁₂ , ..., LC _1n , LC ₂₁ , LC ₂₂ ,.
Write to _2n . After the writing is completed, the non-selection voltage V _GOFF is applied to the gate bus Y _{1 so} that the MOS transistors MB ₁₁ , MB
₁₂ , ..., MB _1n , MA ₂₁ , MA ₂₂ , ..., MA _2n are turned off, and then the selection voltage V _GON is applied to the gate bus Y ₂ .
Liquid crystal cells LC ₂₁ , LC ₂₂ , ..., L in the second and third rows
New video signals are written in C _2n , LC ₃₁ , LC ₃₂ , ..., LC _3n . This operation is repeated thereafter, and gate bus Y
_A selection voltage V _GON and a non-selection voltage V _GOFF are applied to _i , and a new video signal is written in each liquid crystal cell. As described above, the liquid crystal cells in each row receive the writing of the image signal twice within one screen scanning time.
Since writing is performed twice, for example, when there are 460 gate buses, the video signal of the previous row is given for a period of about 1/460, but the signal holding time constant of the liquid crystal cell is sufficient. If so, it means that the video signal to be displayed is given during the remaining period of about 459/460.
It can be displayed with almost no problem. Next, a method for detecting a pixel defect, that is, a pixel switching MOS transistor defect will be described.
Short circuit defects and open defects can be considered as defects of the MOS transistor. Here, taking the pixel in the second row and the second column (represented by the subscript 22) as an example, the short-circuit defect detection will be described first. The resistance between the drain buses X ₁ and X ₂ is measured with the selection voltage V _GON applied to the gate bus Y ₁ and the non-selection voltage V _GOFF applied to the other gate buses. At this time, the MOS transistors MA ₂₂ and MB ₁₂ are in the on state, but the other MOS transistors connected between the drain buses X ₁ and X ₂ are in the off state, so that there is no short circuit defect. The resistance between the drain buses X ₁ and X ₂ should be large enough. If this resistance value is smaller than a predetermined value, the MOS transistor MA _{22 connected} between the drain buses X ₁ and X ₂ is connected.
Continued want to MB ₁₂ and the MOS transistor MB ₂₂ or MA ₁₂
Will have a short circuit defect. Since the probability that both of the two MOS transistors MA ₂₂ and MB ₂₂ and MA ₁₂ and MB ₁₂ connected in series are both short-circuit defects is much smaller than the probability that one MOS transistor is short-circuit defect, the
It is presumed to be a short circuit defect of the transistor MB ₂₂ or MA ₁₂ . It is not possible to determine which of the two MOS transistors MB ₂₂ and MA ₁₂ is a short circuit defect by the above method, but the defect location is limited, so it is easy to use another defect detection method such as shape confirmation. There are advantages. Similarly, the selection voltage V _{GON is} applied to the gate bus Y ₂ and the non-selection voltage V _GOFF is applied to the other gate buses, and the resistance value between the drain buses X ₁ and X _{2 is} measured to measure the MOS transistor MA ₂₂ or MB ₃₂ . It can be seen that the short circuit defect can be detected and the pixel short circuit defect in the second row and the second column can be detected. Next, a method of detecting open defects in the MOS transistors MA ₂₂ and MB ₂₂ will be described. Gate bus Y ₁
And Y ₂ select voltage V _GON and other gate bus non-select voltage V _GON
GOFF is added and the resistance value between the drain buses X ₁ and X ₂ is measured. In the absence of open defects, this resistance should be small enough. If the resistance value is large, the MOS transistor MA ₂₂ or MB _{22 has} a defect, and the open pixel defect in the second row and second column can be detected. The detection of pixel defects has been described above.
The method of repairing this pixel defect will be described below. First, no additional processing is required for pixel open defect relief.
This is because the video signal is written once to each liquid crystal cell by a different MOS transistor during one screen scanning period as described in the description of the scanning method.
This is because display can be performed even if the video signal is written only once due to the open defect of each MOS transistor. For example, considering the liquid crystal cell LC _{22 in} the second row and second column, when the MOS transistor MA ₂₂ has an open defect, M
If the OS transistor MB ₂₂ is normal, the gate bus Y
_{When 2} is selected, the video signal is supplied from the drain bus X ₂ to the liquid crystal cell LC ₂₂ by the MOS transistor MB _22, so that the liquid crystal cell LC ₂₂ can display normally. If the MOS transistor MB ₂₂ has an open defect, MO
If the S transistor MA ₂₂ is normal, the gate bus Y ₁
MOS for the image signal from the transistor MA ₂₂ to the liquid crystal cell LC ₂₂ than the drain bus X ₁ is supplied, a half defect states to perform the same display as the top left pixel or first row, first column pixel LC ₁₁ when but selected . This semi-defect state is not a defect that cannot be completely displayed, but is a state in which the resolution is reduced, and is not so noticeable as a pixel defect. Further, the display content of the semi-defective pixel is the same as that of the upper left pixel, which means that when the color filters are arranged in a slanting pattern to the lower right in a mosaic in a color liquid crystal panel, the display color of the semi-defective pixel is the same as that of the upper left pixel. Therefore, the color is not noticeable. When the color filters are arranged obliquely downward to the left, the MOS transistors MA _ij and MB _ij of each pixel are arranged.
This can be easily dealt with by exchanging the drain connection bus. Regarding the short-circuit defect of the switching MOS transistor in the pixel, after detecting the short-circuit defect by the above method, the short-circuit MOS transistor is disconnected from the drain bus or the like by using, for example, a laser beam, and the short-circuit defect is changed to an open defect. As in the case of the open defect described above, the defect can be changed to a less noticeable defect. Here, when the short-circuit defect is detected only by the resistance value measuring method described above, it is impossible to distinguish the short-circuit defect of the MOS transistors MA ₁₂ and MB ₂₂ , for example. At this time, since the correct video signal writing to the liquid crystal cell LC ₁₂ is performed using the MOS transistor MB ₁₂ , the unnecessary MOS transistor MA ₁₂ may be disconnected from the drain bus or the like by using laser light or the like first. . After that, the short-circuit defect is detected again by the resistance value measuring method, and if there is no short-circuit defect, a normal display can be made.
If it is determined that the S transistor MB ₂₂ is short-circuited, this M
The OS transistor MB ₂₂ is disconnected from the drain bus or the like to complete the pixel defect relief. In this case, since the signal of the same content as the upper left pixel is written by the MOS transistor MA ₂₂ to the pixel of the second row and the second column including the MOS transistor MB ₂₂ , it is possible to make the defect inconspicuous. Next, in order to reduce the number of connections between the active matrix substrate forming the pixel switching MOS transistor array and the external drive circuit, an embodiment of a configuration in which a scanning circuit is built in the active matrix substrate is shown. As shown in FIG. A one-dot chain line frame 1 shows the MOS transistor array of the embodiment of FIG. First, the scanning method will be described. In the case of displaying a television signal, for example, the horizontal shift register 2 operates by a horizontal scanning start signal which is synchronized with a horizontal synchronizing signal which is input to a terminal 4 and a horizontal clock signal which is input to a terminal 5, and outputs pulses of Q ₁ and Q ₂ , ..., are sequentially output to Q _n. By this sequential pulse output, the MOS transistors MC ₁ , MC ₂ , ..., MC _n are sequentially turned on and off, and the video signals applied to the terminals 8 and 9 are drained to the drain buses X ₀ , X ₁ , X ₂ ,. ..., so-called dot sequential scanning is sequentially applied to X _n . On the other hand, the vertical shift register 3 operates by the vertical scanning start signal synchronized with the vertical synchronizing signal input to the terminal 6 and the vertical clock signal input to the terminal 7, and outputs pulses Q ₁ , Q ₂ , ..., Q. Output to _n sequentially. As described above, it is clear that the video signal can be written to each liquid crystal cell by the screen scanning described in the embodiment of FIG. A scanning method for detecting a pixel defect in the pixel switching MOS transistor array 1 will be described below. To select only one gate bus or two consecutive gate buses, input terminal 6 of vertical shift register 3 is used.
In addition, the vertical scanning start signal is input in synchronization with the vertical clock applied to the terminal 7 for a period of one or two vertical clock pulses, and then a predetermined vertical clock is input, which can be easily realized. To measure the resistance value between two adjacent drain buses, the input terminal 4 of the horizontal shift register 2 is synchronized with the horizontal clock applied to the terminal 5,
Input the horizontal scanning start signal for two horizontal clocks,
By then inputting a predetermined horizontal clock, for example, a MOS transistor MC ₂ and MC ₃ only is turned on, by measuring the resistance value between the terminals 8 and 9 and the other off, the drain bus X ₁ The resistance value during X ₂ can be measured. As described above, according to the embodiment of FIG. 2, even when all or part of the horizontal scanning circuit or the vertical scanning circuit is built in the active matrix substrate, the pixel defect can be easily detected, and the pixel defect is remedied. It is also possible easily. Obviously, it is also possible to provide an inspection probe pad on each drain bus, each gate bus, etc., and directly apply a probe to the pad for signal application or measurement at the time of defect inspection. FIG. 3 shows another embodiment in which the horizontal scanning circuit and the vertical scanning circuit are wholly or partially incorporated on the active matrix substrate. The MOS transistor array 1 and the vertical shift register 3 are the same as those in FIG. 2, and here, the description will focus on the horizontal scanning portion.
The horizontal shift register 10 performs the same function as the horizontal shift register 2 of FIG. 2, but the latter has n stages, while the former has n / 3 stages, and the horizontal shift register is for writing video signals. The difference is that the clock frequency is 1/3 of the latter. The terminal 11 is a horizontal scanning start signal input terminal, and the terminal 12 is a horizontal clock input terminal. The writing scanning of the video signal is one pixel unit in FIG. 2, but is three pixel units in FIG. Therefore, the video signal input terminals 13, 14, 15 and 16 are respectively supplied with video signals having a time difference corresponding to the pixel, and the adjacent three video signals are input.
The video signal is simultaneously sent to the drain bus of the book. However, video signals at the same time are applied to the video signal input terminals 13 and 14, and the reason why these terminals are separated will be described later. A method of measuring a resistance value between adjacent drain buses for detecting a pixel defect in the MOS transistor array 1 will be described below. An appropriate input signal is given to the horizontal shift register 10, and, for example, MOS transistors MD ₁ and M
D ₂ and MD ₃ are turned on and other MOS transistors M
It is assumed that D ₄ , MD ₅ , ..., MD _n are turned off. At this time, by measuring the resistance values between the terminals 13 and 15 and between the terminals 15 and 16, the resistance values between the drain buses X ₀ and X _{1 and} between the drain buses X ₁ and X ₂ can be measured. . When measuring the resistance value between the drain buses X ₂ and X ₃ , an appropriate input signal is applied to the horizontal shift register 10 to turn on the MOS transistors MD ₁ , MD ₂ , ..., MD ₆ and turn off the other MOS transistors. MD ₇ , MD ₈ , ..., M
It suffices to turn off D _n and measure the resistance value between the terminals 14 and 16. By the same method, the resistance value between any two adjacent drain buses can be measured, and the pixel defect can be easily detected. In addition, although FIG. 3 exemplifies the three-pixel simultaneous writing scanning, the video signal input terminal is set to k + 1 even in the case of arbitrary k-pixel simultaneous writing scanning.
Obviously, with this preparation, it becomes possible to easily detect pixel defects as in the case of FIG. FIG. 4 shows another embodiment of the present invention. In the embodiment of FIG. 1, as described in the previous description, the i-th row, the j-th row
When MOS transistors MB _ij of the pixel column is defective, but the video signal writing into the liquid crystal cell LC _ij is effected by MA _ij, a video signal to be written first i-1 row j
-Because it is the same signal as the pixel on the 1st column, it is the same display as the pixel on the upper left, and when the color filters are arranged diagonally in a mosaic pattern, the same color as the pixel on the upper left is displayed. The advantage is that the pixel defects are not noticeable.
However, when arranging the color filters in vertical stripes,
Since the displayed color is different from the diagonally upper pixel, the pixel defect may be conspicuous on the contrary. Considering this point, in case of pixel defect, write the same video signal as the pixel directly above,
Fig. 4 shows how the pixel defects due to the difference in color are suppressed.
It is an example of. The method of writing a video signal, the method of detecting a pixel defect, and the like are almost the same as those in FIG. Here, the writing of the video signal will be briefly described, and in the case of a pixel defect, the reason why the same display as the pixel immediately above will be described. When the selection voltage V _GON is applied to the gate bus Y ₀ and the non-selection voltage V _GOFF is applied to the other gate buses, the MOS transistors MA ₁₁ , MA ₁₂ , ..., MA _1n are turned on,
Drain bus X _0, X _1, ..., each of the liquid crystal cell a video signal applied to _{X n-1 LC 11, LC} 12, ..., it will be written to the LC _1n. Subsequently, when the selection voltage V _GON is applied to the gate bus Y ₁ and the non-selection voltage V _GOFF is applied to the other gate buses, the MOS
Transistors MB ₁₁ , MB ₁₂ , ..., MB _1n , MA ₂₁ , M
A _22, ..., MA _2n are turned on, the drain bus X _1, ..., each of the liquid crystal cell a video signal applied to the X _n L
C ₁₁ , LC ₁₂ , ..., LC _1n , LC ₂₁ , LC ₂₂ ,.
It will be written in _2n . Then, by sequentially selecting the gate buses, the video signal can be written to each liquid crystal cell. At this time, the liquid crystal cell LC in the second row and second column
Focusing on two video signals continuously written in ₂₂ , the first time, when the selection voltage V _GON is applied to the gate bus Y ₁ , the liquid crystal cell LC of the previous row by the drain bus X _{2 The} same video signal is written together with ₁₂ , and when the selection voltage V _GON is applied to the gate bus Y ₂ for the _second time, the same video signal is written with the liquid crystal cell LC ₃₂ after one row by the drain bus X ₁ . Here, if there is no pixel defect,
Since each liquid crystal cell displays the video signal written for the second time, each pixel can perform independent display. When there is a pixel defect and the second video signal writing cannot be performed, the display is performed by the first video signal writing, but as described above, the first video signal writing is performed by the video signal in the same column one row before. Therefore, when the color filters are formed in vertical stripes, the same color display is provided, and therefore, there is an advantage that pixel defects are less noticeable. Another embodiment of the present invention is shown in FIG. Figure 1
In this embodiment, as described above, it is difficult to specify which of the short-circuit defects of the MOS transistors MA ₁₂ and MB ₂₂ , for example, only by measuring the resistance value between the adjacent drain buses.
In consideration of this point, FIG. 5 shows a configuration example in which it is possible to easily determine which MOS transistor has a short circuit defect.
Is. 5 is different from FIG. 1 in that the number of drain buses is doubled. In the case of writing a video signal, if the drain buses X _j1 and X _j2 are connected in common and regarded as the drain bus X _j , the embodiment of FIG. 5 is the same as the embodiment of FIG. 1 and the same writing scanning can be performed. Is clear. The detection of the open defect can be considered in the same manner, so the description thereof will be omitted, and the method of detecting the short circuit defect will be described below. When the selection voltage V _{GON is} applied to the gate bus Y ₁ and the non-selection voltage V _{GO FF} is applied to the other gate buses, the MOS transistors MB ₁₁ , MB ₁₂ , ..., MB _1n , MA ₂₁ , MA ₂₂ ,
..., MA _2n is turned on. In this state, for example, by measuring the resistance value between the drain buses X ₁₁ and X _21,
The off resistance of the OS transistor MA ₁₂ can be measured, and by measuring the resistance value between the drain buses X ₁₂ and X _{22, the} MO
The off resistance of the S transistor MB ₂₂ can be measured. Therefore, there is an effect that a MOS transistor having a short circuit defect can be identified by the same method.
It becomes extremely easy to perform separation and rescue of the transistor with a laser or the like. In FIG. 5, all two drain buses are provided, but for example, only the odd-numbered drain buses are separated into two, and the even-numbered drain buses X ₂₁ and X ₂₂ , X ₄₁ and X ₄₂ , ... It is possible to specify the above-mentioned short-circuit defective MOS transistor even if the drain buses X ₂ , X ₄ , X ₆ , ... In the embodiment of FIG. 5, in addition to the video signal writing scanning method described above, the following two-row simultaneous writing scanning method can be considered. This scanning method is compatible with interlaced scanning of NTSC television signals. One screen (one frame) of a television signal is composed of two fields, and one field has 241 effective display scanning lines. The scanning lines of the second field are located between the scanning lines of the first field, and there are 482 scanning lines as one frame. At this time, the vertical pixel of the liquid crystal panel is set to 460.
Considering the number of lines, it is convenient to write the video signal to the pixels of two rows adjacent to each other in one horizontal scanning period of the television signal. That is, in the first field, odd-numbered subscript gate buses Y ₁ , Y ₃ , ... Are sequentially selected to write video signals to the liquid crystal cells of the first and second rows, the third and fourth rows ,. In the second field, the even-numbered gate buses Y ₀ , Y ₂ , ... Are sequentially selected and the video signals are supplied to the liquid crystal cells of the first row, the second row and the third row, the fourth row and the fifth row ,. Interlaced scanning is possible. Similar interlaced scanning is possible in the embodiments of FIGS. 1 and 4, but in this case, since the drain bus has only the number of horizontal pixels, the liquid crystal cells in the adjacent two rows have the same video signal. Although not writable, in the embodiment of FIG. 5, since the drain bus is twice the number of horizontal pixels, different video signals can be written in the liquid crystal cells of the adjacent two rows selected, and vertical signals are added by the time axis control complementation of the signals. There is an advantage that deterioration of resolution can be compensated. As described above, according to the present invention,
Since an active matrix substrate for driving a liquid crystal in which a defect in a pixel switching MOS transistor can be easily detected and repaired can be obtained, an active matrix type liquid crystal display device can be manufactured with high yield.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 MOS of a liquid crystal display device according to an embodiment of the present invention
It is a block diagram of a transistor array. FIG. 2 is a substrate configuration diagram of an active matrix liquid crystal display device according to an embodiment of the present invention in which a scanning circuit is incorporated. FIG. 3 is a substrate configuration diagram of an active matrix liquid crystal display device according to an embodiment of the present invention in which a scanning circuit is incorporated. FIG. 4 is a schematic diagram of a liquid crystal display device M according to another embodiment of the present invention.
It is a block diagram of an OS transistor array. FIG. 5 shows an M of a liquid crystal display device according to another embodiment of the present invention.
It is a block diagram of an OS transistor array. [Explanation of symbols] X ₀ , X ₁ , X ₂ ... Drain bus, Y ₀ , Y ₁ , Y ₂ ... Gate bus, MA ₁₁ , MA ₁₂ , MB ₁₁ , MB ₁₂ , MC ₁ , MC ₂ , MD
₁ , MD ₂ ... MOS transistor, LC ₁₁ , LC ₁₂ ... Liquid crystal cell corresponding to pixel, 1 ... MOS transistor array, 2, 3, 10 ... Shift register.

Claims (1)

[Claims] 1. N gate buses extending approximately to the left and right, n drain buses extending approximately up and down, pixels having liquid crystal elements and switching elements arranged at their intersections, and video signals are sequentially applied to the n drain buses. In an active matrix type liquid crystal display device including a horizontal scanning unit including a plurality of scanning transistors, the n scanning transistors form a plurality of groups whose gate terminals are commonly connected for every k, and k + 1 are formed. Having the above signal input terminals, the drains (or sources) of the k scanning transistors in the same group are connected to the k independent signal input terminals, and among the k independent signal input terminals. At least one of the active groups uses a signal input terminal that is not used as a signal input terminal of an adjacent group. Matrix type liquid crystal display device.