JPH07240680A - Electronic device, integrated circuit and termination device - Google Patents

Abstract

PURPOSE:To ensure the stability of a termination voltage by connecting two voltage generating circuits in series to provide a voltage being a sum of voltages of both circuits to an output circuit and applying a voltage at the connecting point to the termination resistor as the termination voltage. CONSTITUTION:Since a voltage V1+V2 is applied to an output circuit 48 as a power supply voltage and the voltage V2 is applied to a termination resistor 52 as a termination voltage VTT, a signal whose voltage V2 is an intermediate voltage is transmitted. Since a voltage generating circuit 37 is formed by connecting voltage generating circuits 38, 39 in series, even when a current is outputted from a voltage output terminal 41 or a current is received thereby, the voltage at the terminal 41 is maintained at the voltage V2 to ensure the stability of the termination voltage VTT equal to be V2. Furthermore, when a signal is not sent through a bus line 51, since no current flows to a termination resistor 52, the power consumption is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device in which a signal is transmitted, and an integrated circuit and a terminating device used in such an electronic device.

[0002]

2. Description of the Related Art Conventionally, for example, an electronic device shown in FIG. 34 is known as an electronic device for transmitting a small amplitude signal.

In the figure, 1 is a microprocessor, 2 ₁ ,
2 ₂ and 2 _n are SDRAM (Synchronous DRAM [dynami
c random access memory]), 3 is a bus line forming a signal transmission path.

Currently, the microprocessor 1 and SDRA
Transmission of signals to and from the M2 ₁ to 2 _n is being performed by the number 10MHz frequency, the transmission of the signal at frequencies above 100MHz is requested.

FIG. 35 is a circuit diagram showing an example of a conventional interface circuit and bus system applied to such an electronic device.

In the figure, 5 is a microprocessor, and 6
Is a signal input / output terminal used for inputting / outputting the signal DQ, 7 is a reference voltage input terminal for taking in the reference voltage Vref, and 8
Is an input circuit composed of a differential amplifier circuit.

Further, 9 is a VCC power supply line for supplying a power supply voltage VCC (3.3 V), and 10 is a power supply voltage VSS (0 V).
Is a VSS power supply line, 11 is a main body circuit, and 12 is a push-pull type output circuit.

In the push-pull type output circuit 12, 13 is an enhancement type pMOS transistor which forms a pull-up element, and 14 is an enhancement type nMOS transistor which forms a pull-down element.

Further, 15 is a bus line forming a signal transmission path,
6 is a termination voltage source that generates a termination voltage VTT (1.65 V), 17 is a VTT voltage line that supplies the termination voltage VTT, 1
Numerals 8 and 19 are terminating resistors having a resistance value of 50Ω.

Further, 20 is an SDRAM, 21 is a signal input / output terminal used for inputting / outputting the signal DQ, 22 is a reference voltage input terminal for taking in the reference voltage Vref, and 23.
Is an input circuit composed of a differential amplifier circuit, and 24 is a push-pull type output circuit.

In this example, the termination voltage VTT output from the termination voltage source 16 is used as the reference voltage Vref and the reference voltage input terminal 7 of the microprocessor 5 and the SDRAM.
It is supplied to the reference voltage input terminal 22 of 20.

In the interface circuit and the bus system, the signal DQ having the reference voltage Vref = 1.65V as the intermediate voltage and the amplitude of ± 400 mV is transmitted between the microprocessor 5 and the SDRAM 20.

Here, for example, the microprocessor 5
When the signal DQ is transmitted from the SDRAM 20 to the SDRAM 20, when the pMOS transistor 13 = OFF (non-conductive) and the nMOS transistor 14 = ON (conductive), the signal DQ = L level (low level). .

On the other hand, the pMOS transistor 13
= ON and nMOS transistor 14 = OFF, the signal DQ = H level (high level).

Therefore, when the output circuit 12 outputs the L level, current flows from the termination voltage source 16 to the load side, but when the output circuit 12 outputs the H level, the termination voltage source from the load side. A current will flow into 16.

Here, as the termination voltage source 16, a voltage source such as a switching regulator or a series regulator is generally used, but these voltage sources have a configuration in which it is expected that current will flow from the load side. However, if a current flows into these voltage sources from the load side, the termination voltage VTT will fluctuate.

Therefore, a bus system as shown in FIG. 36 is actually used. In the figure, 25 is the power supply voltage VC
A power supply voltage generation circuit for generating C, 26 is a VCC power supply line,
27 is a VSS power supply line.

Further, 28 to 31 are terminating resistors having a resistance value of 100Ω, 32 and 33 are voltage dividing resistors for dividing the power supply voltage VCC to obtain the reference voltage Vref, and 34 and 35 are power supply voltage of the microprocessor 5. It is an input terminal.

This bus system has terminating resistors 28 and 29.
The termination resistance value of the termination portion made of is 50Ω and the termination resistance value of the termination portion made of the termination resistors 30 and 31 is 50Ω.

[0020]

However, in this bus system, the terminating resistors 28 and 29 and the terminating resistor 3 are used.
0 and 31 are the VCC power supply line 26 and the VSS power supply line 2 respectively
Since it is connected in series with 7 and 7, even when no signal is transmitted, a current flows through these terminating resistors 28 to 31, which causes an increase in power consumption. there were.

On the other hand, the voltage dividing resistors 32 and 33 are increased in resistance value so that the voltage dividing resistors 32 and 3 are increased.
Although the current flowing through 3 can be reduced, if the precision of these voltage dividing resistors 32 and 33 is not high, the reference voltage Vref may not match the termination voltage VTT.

Here, the reference voltage Vref and the termination voltage VTT
The non-coincidence becomes a DC offset voltage of the input signal, and the operation margin on the H level side or the L level side of the input signal is reduced.

Therefore, as the voltage dividing resistors 32 and 33,
It is necessary to use a highly accurate resistor, but in this case, there is a problem that the price is increased.

In view of the above points, the present invention is an electronic device for transmitting signals, which stabilizes the termination voltage and reduces power consumption, and depending on the configuration,
An electronic device that is designed to match the reference voltage and the termination voltage, prevent the offset voltage from occurring in the input signal, and ensure a sufficient operating margin for the input signal, and the electronic device used in this electronic device. An object is to provide a suitable integrated circuit and termination device.

[0025]

[Means for Solving the Problems]

1st invention: FIG. 1 FIG. 1 is a circuit diagram showing the principle of an electronic device according to the first invention of the present invention. In the figure, 37 is a voltage generating circuit.
8 is a voltage generating circuit for generating a voltage V1, 39 is a voltage V2
Is a voltage generating circuit, and 40 and 41 are voltage output terminals.

The voltage generating circuit 37 has a voltage generating circuit 38 for generating a voltage V1 and a voltage generating circuit 39 for generating a voltage V2 connected in series, and a voltage Vout is applied to a voltage output terminal 40.
1 + V2 is output, and the voltage V2 is output to the voltage output terminal 41.

Reference numeral 42 is a power supply line for supplying the voltage V1 + V2 output from the voltage generation circuit 37 as a power supply voltage,
Reference numeral 43 is a termination voltage line for supplying the voltage V2 output from the voltage generation circuit 37 as the termination voltage VTT.

Reference numeral 44 is an integrated circuit for inputting / outputting signals, 45 is a signal input / output terminal for inputting / outputting signals, 46 is a power supply voltage input terminal for taking in the voltage V1 + V2 as a power supply voltage, and 47 is a power supply voltage. As voltage V1 + V2
Is a push-pull type output circuit.

In the push-pull type output circuit 48, 49 is a p-channel insulated gate field effect transistor which constitutes a pull-up element, and 50 is an n-channel insulated gate field effect transistor which constitutes a pull-down element.

Further, 51 is a bus line forming a signal transmission path, 5
2 is a terminating resistor for terminating the bus line 51.

Reference numeral 53 is an integrated circuit for inputting / outputting signals, 54 is a signal input / output terminal for inputting / outputting signals, and 55 is a voltage V2 output from the voltage generating circuit 37 and is supplied as a reference voltage Vref. Reference voltage input terminals, 5
Reference numeral 6 is an input circuit.

Second invention: FIG. 2 FIG. 2 is a diagram for explaining the principle of the second invention in the present invention. In the figure, 58 is a voltage generating circuit for generating a voltage V3, and 59 is a power supply voltage for the voltage V3. Is a power supply line for supplying.

Further, 60 is a voltage generating circuit for generating the voltage V4, 61 is a power supply voltage input terminal for taking in the voltage V3, 62 is a power supply line, and 63 is an operational amplifier (operational amplifier).

Further, 64 and 65 are voltage dividing resistors for dividing the voltage V3, 66 is a voltage output terminal for outputting the voltage V4, and 6
Reference numeral 7 denotes a termination voltage line for supplying the voltage V4 output from the voltage generation circuit 60 as the termination voltage VTT.

The voltage generating circuit 60 supplies a voltage obtained by dividing the voltage V3 by the voltage dividing resistors 64 and 65 to the first input terminal of the operational amplifier 63 and outputs the output of the operational amplifier 63 to the second input of the operational amplifier 63. The voltage is fed back to the input terminal, and the power supply voltage V3 is divided by the resistors 64 and 65 to the second input terminal, that is, the voltage output terminal 66, and the voltage V4 that is the same voltage as the voltage is output.

Further, 68 is an integrated circuit for inputting / outputting signals, 69 is a signal input / output terminal for inputting / outputting signals, 70 is a power supply voltage input terminal for taking in the voltage V3 as a power supply voltage, and 71 is a power supply voltage. Is a power supply line for supplying the voltage V3, and 72 is a push-pull type output circuit.

In this push-pull type output circuit 72, 73 is a p-channel insulated gate field effect transistor which forms a pull-up element, and 74 is an n-channel insulated gate field effect transistor which forms a pull-down element.

Further, 75 is a bus line forming a signal transmission path, and 7
6 is a terminating resistor for terminating the bus line 75.

Reference numeral 77 is an integrated circuit for inputting / outputting signals, 78 is a signal input / output terminal for inputting / outputting signals, and 79 is a voltage V4 output from the voltage generating circuit 60, which is supplied as a reference voltage Vref. Reference voltage input terminal, 8
0 is an input circuit.

[0040]

[Action]

1st invention ... FIG. 1 In 1st invention, the voltage V is used as the power supply voltage for the output circuit 48.
Since 1 + V2 is supplied and the voltage V2 is supplied to the terminating resistor 52 as the terminating voltage VTT, it is possible to transmit a signal having the intermediate voltage V2. The voltage V1 =
If the voltage is V2, the termination voltage VTT can be 1/2 of the voltage V1 + V2.

When the p-channel insulated gate type field effect transistor 49 = OFF and the n-channel insulated gate type field effect transistor 50 = ON, the output of the output circuit 48 becomes L level.

In this case, the voltage generating circuit 39 → terminating voltage line 43 → terminating resistor 52 → bus line 51 → n-channel insulated gate field effect transistor 50 → ground → voltage generating circuit 3
The current i ₀ flows in the closed circuit 9 and the voltage of the voltage output terminal 41 is maintained at V2.

On the other hand, when the p-channel insulated gate field effect transistor 49 is ON and the n-channel insulated gate field effect transistor 50 is OFF, the output of the output circuit 48 is H level.

In this case, the voltage generating circuit 38 → the power supply line 42 → the p-channel insulated gate field effect transistor 4
9 → bus line 51 → terminating resistor 52 → current generating circuit 38, current i ₁ flows in the closed circuit, and the voltage of the voltage output terminal 41 is V
Maintained at 2.

As described above, according to the first aspect of the invention, since the voltage generating circuit 37 is configured by connecting the voltage generating circuits 38 and 39 in series, when the current is output from the voltage output terminal 41. Even when the current is input, the voltage of the voltage output terminal 41 can be maintained at V2, and the stability of the termination voltage VTT = V2 can be ensured.

Further, in the first aspect of the invention, when the bus line 51 is not transmitting a signal, no current flows through the terminating resistor 52, so that power consumption can be reduced.

Further, in the first aspect of the invention, since the termination voltage VTT can be used as the reference voltage Vref of the integrated circuits 44 and 53, the reference voltage Vref and the termination voltage VT.
By matching with T, an offset voltage is not generated in the input signal, and a sufficient operation margin of the input signal can be secured.

Second invention: FIG. 2 In the second invention, when the resistance value of the resistor 64 is R ₆₄ and the resistance value of the resistor 65 is R ₆₅ , the termination voltage VTT is V3 × R _65.
/ (R ₆₄ + R ₆₅ ), and it is possible to transmit a small amplitude signal with the termination voltage VTT as an intermediate voltage. In addition,
If R ₆₄ = R ₆₅ , the termination voltage VTT can be VTT = V3 / 2.

When the p-channel insulated gate field effect transistor 73 is OFF and the n-channel insulated gate field effect transistor 74 is ON, the output of the output circuit 72 is L level.

In this case, the operational amplifier 63 → the termination voltage line 6
7 → Terminal resistor 76 → Bus line 75 → N-channel insulated gate field effect transistor 74 → Ground → Voltage generation circuit 58
→ The power supply lines 59 and 62 → The current i ₃ flows in the closed circuit composed of the operational amplifier 63.

On the other hand, when the p-channel insulated gate field effect transistor 73 is ON and the n-channel insulated gate field effect transistor 74 is OFF, the output of the output circuit 72 is H level.

In this case, the voltage generating circuit 58 → the power supply line 5
9, 71 → p-channel insulated gate field effect transistor 73 → bus line 75 → termination resistor 76 → termination voltage line 67 →
The current i ₄ flows in the closed circuit composed of the operational amplifier 63 → ground → voltage generating circuit 58.

As described above, according to the second aspect of the invention, since the voltage generating circuit 60 is configured to feedback control the voltage V4 = the termination voltage VTT by using the operational amplifier 63, the voltage output terminal 66 Whether the current is output or the current is input, the stability of the terminal voltage VTT = V4 can be ensured.

Further, in the second aspect of the present invention, when the bus line 75 is not transmitting a signal, no current flows through the terminating resistor 76, so that power consumption can be reduced.

Further, in the second aspect of the invention, since the termination voltage VTT can be used as the reference voltage Vref of the integrated circuits 68 and 77, the reference voltage Vref and the termination voltage VT are used.
By matching with T, an offset voltage is not generated in the input signal, and a sufficient operation margin of the input signal can be secured.

[0056]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first to ninth embodiments of the present invention will be described below with reference to FIGS. 3 to 33, taking the case where the present invention is applied to an electronic device including a microprocessor and an SDRAM as an example. To do.

First Embodiment FIG. 3 to FIG. 11 FIG. 3 is a circuit diagram showing a main part of the first embodiment of the present invention.
In the figure, 83 is a voltage generating circuit, and 84 and 85 are voltage V.
A voltage generating circuit for generating 5 = 1.0 V, and 86 and 87 are voltage output terminals.

The voltage generating circuit 83 has voltage generating circuits 84 and 85 for generating a voltage V5 connected in series, and a voltage output terminal 86 having a power supply voltage VCCQ of voltage 2 × V5 =
2.0V is output and the terminal voltage VTT is output to the voltage output terminal 87.
As a result, a voltage V5 = 1.0V is output.

Further, 88 is a VC for supplying the power supply voltage VCCQ = 2 × V5 output from the voltage generating circuit 83.
A CQ power supply line 89 is a termination voltage line for supplying a termination voltage VTT = V5 output from the voltage generation circuit 83.

Further, 90 is a microprocessor, 91-
Reference numeral 94 is an SDRAM for inputting / outputting 8-bit data DQ0 to DQ7, and 95 to 99 are data input / output terminals for inputting / outputting data DQ0.

Reference numerals 100 to 104 are reference voltage input terminals for taking in the reference voltage Vref. In the first embodiment, the termination voltage VTT is supplied to the microprocessor 90 and SDRAMs 91 to 94 as the reference voltage Vref. It is configured.

Numerals 105 to 109 are input circuits composed of a differential amplifier circuit provided for the data DQ0, and 110.
˜114 are push-pull type output circuits provided for the data DQ0.

Further, 115 is a bus line provided for the data DQ0, 116 and 117 are terminating resistors for terminating the bus line 115, and the terminating resistor 116 has a resistance value of 5
The resistance value of the terminating resistor 117 is 0Ω, and the resistance value of the terminating resistor 117 is 30Ω.

Here, the microprocessor 90 and SD
In the RAMs 91 to 94, the input / output circuit portion has the same circuit configuration, and FIG.
A part of 0 is shown.

In FIG. 4, reference numeral 119 is the power supply voltage VCC (3.3
V) is supplied to the VCC power supply terminal, 120 is the power supply voltage V
VCCQ power supply terminal to which CCQ (2.0V) is supplied, 1
Reference numeral 21 is a VSS power supply terminal to which the ground voltage VSS (0V) is supplied.

Further, 122 is a VCC power supply line connected to the VCC power supply terminal 119, and 123 is a VCCQ power supply terminal 12
A VCCQ power supply line connected to 0 and a VSS power supply line 124 connected to the VSS power supply terminal 121.

Further, 125 is a main body circuit to which the power supply voltage VCC is supplied, / DATA is data output from the main body circuit 125, and / HZ is a control signal for controlling whether or not the output state is a high impedance state. .

Further, 126 is an output control circuit to which the power supply voltage VCC is supplied, 127 is a NOR circuit, 128 is an inverter, and 129 is a NAND circuit.

Further, 130 is an output drive circuit (pre-driver) to which the power supply voltage VCCQ is supplied, 131 and 132 are CMOS type inverters, 133 and 134 are enhancement type pMOS transistors, and 135 and 13 respectively.
6 is an enhancement type nMOS transistor.

In the output circuit 110, reference numeral 137 is an enhancement type pMOS transistor which forms a pull-up element, and 138 is an enhancement type nMOS transistor which forms a pull-down element.

Here, pMOS transistors 133, 1
Power supply voltage VC is applied to the N well in which 36 and 137 are formed.
When C is supplied as the back bias voltage, when the power supply voltage is VCC = 0V and the power supply voltage VCCQ = 2V when the power is turned on or off, from the sources of the pMOS transistors 133, 136, 137, A current may flow in the N well in which the pMOS transistors 133, 136, 137 are formed, and the pMOS transistors 133, 136, 137 may be destroyed.

Therefore, in the first embodiment, pM
The power supply voltage VCCQ is supplied as a back bias voltage to the N well in which the OS transistors 133, 136, 137 are formed, and even when the power is turned on or off, even if the power supply voltage VCC = 0V and the power supply voltage VC
Even if CQ = 2V is reached, p
The current is prevented from flowing from the sources of the MOS transistors 133, 136, 137 to the N well in which these pMOS transistors 133, 137 are formed, and pMO
The S transistors 133, 136, 137 are prevented from being destroyed.

Here, in the microprocessor 90, as shown in FIG. 5, when the control signal / HZ = L level, the output of the inverter 128 = H level and the output of the NOR circuit 127 = L level.

As a result, the pMOS transistor 133 =
ON, the nMOS transistor 135 = OFF, the output of the inverter 131 = H level, and the pMOS transistor 137 = OFF.

The output of the NAND circuit 129 = H level, the pMOS transistor 134 = OFF, the nMOS transistor 136 = ON, the output of the inverter 132 = L.
The level becomes nMOS transistor 138 = OFF.

Therefore, in this case, the output circuit 11
The output state of 0 is a high impedance state (Hi-Z).

On the other hand, as shown in FIG. 6, when the control signal / HZ = H level, the data / DATA
== H level, the output of the NOR circuit 127 = L level.

As a result, the pMOS transistor 133 =
ON, the nMOS transistor 135 = OFF, the output of the inverter 131 = H level, and the pMOS transistor 137 = OFF.

The output of the NAND circuit 129 = L level, the pMOS transistor 134 = ON, the nMOS transistor 136 = OFF, the output of the inverter 132 = H.
The level becomes nMOS transistor 138 = ON.

Therefore, in this case, the output circuit 11
The signal output from 0 becomes DQ0 = L level.

Further, as shown in FIG. 7, the control signal / HZ
= H level, when the data / DATA = L level, the output of the NOR circuit 127 becomes H level.

As a result, the pMOS transistor 133 =
OFF, nMOS transistor 135 = ON, output of inverter 131 = L level, and pMOS transistor 137 = ON.

The output of the NAND circuit 129 = H level, the pMOS transistor 134 = OFF, the nMOS transistor 136 = ON, the output of the inverter 132 = L.
The level becomes nMOS transistor 138 = OFF.

Therefore, in this case, the output circuit 11
The signal output from 0 becomes DQ0 = H level.

In the first embodiment, the SDR
AM91-94 are connected to the bus line at equal intervals,
Only the bus line is provided between the microprocessor 90 and the SDRAM 91.

Therefore, when the characteristic impedance of the bus line 115 is Z0, the SDR is compared with the characteristic impedance of the portion where the SDRAMs 91 to 94 are not connected.
Bus line 11 of the part where AM91-94 are connected at equal intervals
The effective characteristic impedance of 5 is small.

In general, the characteristic impedance Z0 of the bus line 115 can be expressed by Z0 = (L / C) ^1/2 . However, L is the wiring inductance per unit length, C
Is the wiring capacity per unit length.

For example, L = 250 nH / m, C = 10
A typical value is 0 pF, in which case Z0 = (2
50 × 10 ⁻⁹ / 100 × 10 ⁻¹² ) ^1/2 = 50Ω.

On the other hand, when the SDRAMs 91 to 94 are connected, their load capacity (specifically, the input / output terminal 96
Capacity of ~ 99) is added, for example, load capacity 3.75
When pF SDRAMs 91 to 94 are connected to the bus line 115 every 6.25 mm, 160 pieces are connected per 1 m, and if the capacity per unit length is CL, CL =
It is 3.75 pF × 160 = 600 pF / m.

In this case, the effective characteristic impedance ZL of the bus line 115 is represented by ZL = [L / (C + CL)] ^1/2 , and in the above example, ZL = [250 × 10 ^-9
/ (100 × 10 ^-12 + 600 × 10 ^-12 )] ^1/2 = 18.
9Ω, characteristic impedance Z0 when there is no load
= 50Ω, it is considerably smaller.

Therefore, in order to strictly match the impedance and avoid the reflection of the transmission signal, the terminating resistor 11 is used.
The resistance value of 6 and 117 should be 18.9Ω which is the same value as the effective characteristic impedance ZL.

However, when the resistance value of the terminating resistors 116 and 117 is set to 18.9Ω, the load resistance seen from the driving side is 9.4.
5Ω, and the output circuits 110 to 114 are at least
If there is no current drive capacity of about 20 mA, the input circuit 105
It is impossible to obtain an amplitude that allows ~ 109 to operate stably.

Therefore, in the first embodiment, the SDRAM is
The value of the terminating resistor 117 on the side where 91 to 94 are concentrated is removed from the strict matching condition, is made larger than the effective characteristic impedance ZL, and the characteristic impedance Z0 of the bus line 115 when there is no load is set as a limit. Is 30Ω
I am trying.

On the other hand, on the microprocessor 90 side, since the load connected is small, the value of the terminating resistor 116 is set to 50Ω, which is the same value as the characteristic impedance Z0 of the bus line 115 when there is no load.

As a result, the load resistance seen from the driving side is 30.
The parallel value of Ω and 50Ω is 18.75Ω, which is 30Ω.
Since the load resistance can be made larger than that when simply using both sides (load resistance = 15Ω), the output circuits 110-1
Even if the current driving capability of 14 is relatively small, the signal amplitude can be increased.

In the first embodiment, the output circuit 110 of the microprocessor 90 and the SDRAMs 91 to 94 is used.
˜114 are composed of CMOS push-pull type whose power supply voltage is VCCQ, and the termination voltage VTT.
Is set to VCCQ / 2, it is possible to transmit a signal whose intermediate voltage is the termination voltage VTT.

Here, for example, when the output circuit 110 outputs the L level, the voltage generating circuit 85 → termination voltage line 89 → termination resistors 116 and 117 → bus line 115 →
A current flows through a closed circuit composed of the output circuit 110 (nMOS transistor 138) → ground → voltage generation circuit 85.

When the output circuit 110 outputs the H level, the voltage generation circuit 84 → VCCQ power supply line 8
8 → output circuit 110 (pMOS transistor 137) →
A current flows through the closed circuit including the bus line 115, the terminating resistors 116 and 117, and the voltage generating circuit 84.

As described above, according to the first embodiment, since the voltage generating circuit 83 is configured by connecting the voltage generating circuits 84 and 85 in series, when the current is output from the voltage output terminal 87. , The voltage of the voltage output terminal 87 can be maintained at V5 = 1.0V even when a current is input, and the stability of the termination voltage VTT = V5 = 1.0V is ensured. be able to.

Further, in the first embodiment, when the bus line 115 is not transmitting a signal, the terminating resistor 11
Since no current flows through 6, 117, power consumption can be reduced.

Further, in the first embodiment, the output control circuit and the output circuits 110 to 114 have the power supply voltage VCCQ = 2.0V which is lower than the power supply voltage VCC = 3.3V for driving the main circuit. I am trying to drive it,
From this point as well, the power consumption can be reduced.

Further, in the first embodiment, the termination voltage VTT is set to the microprocessor 90 and the SDRAM 91.
Since it is used as the reference voltage Vref required for ~ 94, the reference voltage Vref and the termination voltage VTT are made to coincide with each other so that an offset voltage is not generated in the input signal and a sufficient operation margin of the input signal is obtained. Can be secured.

Further, according to the first embodiment, as the power supply voltage of the output drive circuit for driving the output circuits 110 to 114, the power supply voltage VCCQ is the same as that of the output circuits 110 to 114.
Are supplied, the pMOS transistor that forms the pull-up element and the nMO that forms the pull-down element.
It is possible to drive the S-transistor with good balance.

In the microprocessor 90,
The output control circuit 126, the output drive circuit 130, and the output circuit 110 can be configured as shown in the circuit diagram of FIG. The same applies to the SDRAMs 91 to 94.

In FIG. 8, in the output control circuit 126, 1
41 is a NAND circuit, 142 is an inverter, and 143 is N.
It is an OR circuit.

In the output drive circuit 130, 14
Reference numeral 4 is a CMOS type inverter supplied with the power supply voltage VCC, 145 is an enhancement type pMOS transistor, and 146 is an enhancement type nMOS transistor.

In the output circuit 110, 147 is a depletion type nMOS transistor which forms a pull-up element, and 148 is an enhancement type nMOS transistor which forms a pull-down element. This output circuit 110 drives the pull-up element. It is an attempt to improve the ability.

In this case, a depletion type nMOS
In order to cut off the transistor 147, if the L level voltage of the data signal DQ0 is V _OL ,
Threshold voltage V of nMOS transistor 147
_THD needs to be set to -V _OL ≤V _THD .

For example, when the termination voltage VTT = 1.0V and the signal DQ0 = ± 0.25V (driving current 10 mA), V _OL = 1−0.25 = 0.75V, and therefore in this case , V _THD may be set to -0.75V or higher.

Here, as shown in FIG. 9, the control signal / H
When Z = H level, the output of the inverter 142 = L level, the output of the NAND circuit 141 = H level, the pMOS transistor 145 = OFF, the nMOS transistor 14
6 = ON, output of inverter 144 = L level, nMO
The S transistor 147 = OFF.

Further, the output of the NOR circuit 143 = L level and the nMOS transistor 148 = OFF. In this case, the output state of the output circuit 110 becomes a high impedance state.

On the other hand, as shown in FIG. 10, when control signal / HZ = L level, data / DAT
When A = H level, the output of the NAND circuit 141 =
L level, pMOS transistor 145 = ON, nMO
The S transistor 146 = OFF, the output of the inverter 144 = H level, and the nMOS transistor 147 = ON.

Further, the output of the NOR circuit 143 = L level, the nMOS transistor 148 = OFF, and in this case, the signal DQ0 = output from the output circuit 110 =
It becomes H level.

Further, as shown in FIG. 11, the control signal / H
When Z / L level and data / DATA = L level, output of NAND circuit 141 = H level, pMOS transistor 145 = OFF, nMOS transistor 146 = ON, output of inverter 144 = L
Level, nMOS transistor 147 = OFF.

Further, the output of the NOR circuit 143 = H level, the nMOS transistor 148 = ON, and in this case, the signal DQ0 = L output from the output circuit 110.
It becomes a level.

The nMOS transistor 147 can also be configured by an enhancement type nMOS transistor, but in this case, the threshold voltage of this enhancement type nMOS transistor is nM.
Unless it is set lower than the threshold voltage of the OS transistor 148, there is no point in increasing the driving capability due to the decrease in the threshold voltage.

Second Embodiment FIG. 12 to FIG. 16 FIG. 12 is a circuit diagram showing the essential parts of the second embodiment of the present invention. In the second embodiment, a voltage generating circuit 150 having an output voltage different from that of the voltage generating circuit 83 shown in FIG. 3 is provided.

In this voltage generating circuit 150, 15
Reference numerals 1 and 152 are voltage generating circuits for generating a voltage V6 (1.65 V), and 153 and 154 are voltage output terminals.

That is, the voltage generating circuit 150
The voltage generation circuits 151 and 152 for generating 6 are connected in series, the voltage 2 × V6 = 3.3V is output to the voltage output terminal 153 as the power supply voltage VCCQ, and the voltage V6 = 1 is output to the voltage output terminal 154 as the termination voltage VTT. It outputs .65V.

Further, 155 to 159 are branch paths of the bus line 115, so-called stubs, and 160 to 164 are bus lines 11
A resistor connected between the branch point 5 and the stubs 160 to 165.

In the second embodiment, the VCC
The power supply voltage VCCQ supplied by the Q power supply line 88 is supplied to the VCC power supply terminal and the VCCQ power supply terminal of the microprocessor 90 and the SDRAMs 91 to 94.

Therefore, in the microprocessor 90 and the SDRAMs 91 to 94, the VCC power supply terminal is externally connected to the VCCQ power supply terminal.
FIG. 13 shows the case of the microprocessor 90.

That is, in the second embodiment, as shown in FIG.
As representatively shown in the case of the microprocessor 90, not only the main body circuit 125 and the output control circuit 126 but also the output drive circuit 130 and the output circuit 110 are driven by the power supply voltage VCCQ = 3.3V.

In this case, the nMOS transistor 13
Since the power supply voltage VCCQ = 3.3V is also supplied to the gate of 8, the internal resistance of the nMOS transistor 138 becomes low and an excessive current flows to the output.

Therefore, in this second embodiment,
A resistor 16 is provided between the branch point of the bus line 115 and the stub 155.
0 is connected and the internal resistance of the output circuit 110 is set to an appropriate value so that the drive current for the terminating resistors 116 and 117 does not change.

Similarly, resistors 161 to 164 are also connected between the branch point of the bus line 115 and the stubs 156 to 159.

14 and 15 are views for explaining a method of determining the resistance values of the resistors 160 to 164.
Is an nMOS of the output circuit 110 of the microprocessor 90.
FIG. 15 shows the static characteristics of the transistor 138, and FIG.
It is a figure which shows a part of.

That is, in the second embodiment, nMO
The S transistor 138 is configured to have static characteristics as shown in FIG.

Then, when VCCQ = 3.3V, when nMOS transistor 138 = ON, V
The _GS = 3.3V, but, in this case, the drain-to-source voltage V _DS = 0.2V.

Here, the drive current of the nMOS transistor 138 is 10 mA, and the resistance value of the termination resistors 116 and 117 =
If the resistance is 50Ω, the load resistance value is 25Ω, and the voltage drop across the terminating resistors 116 and 117 is as shown in FIG.
It becomes 0.25V.

As a result, the voltage of the bus line 115 = 1.4V
Therefore, the resistance value of the resistor 160 is (1.4-0.
2) It will be sufficient to select / 10 × 10 ⁻³ = 120Ω. The same applies to the resistors 161 to 164.

By thus connecting the resistors 160 to 164 between the bus line 115 and the stubs 155 to 159, the influence of signal reflection occurring in the stubs 155 to 159 on the bus line 115 is minimized. can do.

In this case, the characteristic impedance of the stubs 155 to 159 can be determined as follows.

That is, first, the resistances of the resistors 160 to 164 are set to 120Ω in consideration of the driving force of the output circuit. However, since the characteristic impedance of the bus line 115 is 50Ω, the resistance of the bus line 115 is changed from the branch point. When I saw it, 50Ω was 2
Since they appear to be in parallel, the load looks like a characteristic impedance of 25Ω.

On the other hand, the resistance 1 having a resistance value of 120Ω
When 60 to 164 are connected, looking at the bus line 115 from the stubs 155 to 160, 120Ω + 25Ω = 145Ω
Looks like an impedance.

Therefore, the characteristic impedance of the stubs 155 to 159 is preferably 145Ω. However, it has been confirmed by simulation that this value does not hinder practically even if it changes by about ± 50%.

In this way, when a signal enters the stubs 155 to 159 from the bus line 115, the input / output terminal 95
Since ~ 99 is not terminated, it is 100% reflected, but when this reflection is transmitted to the resistors 160 to 164, reflection does not occur because it is impedance-matched.

That is, since this signal is absorbed by the terminating resistors 116 and 117 after entering the bus line 115, the resonance phenomenon in the stubs 155 to 159 does not occur thereafter, and good signal transmission can be performed. it can.

As in the case of the first embodiment, VCC
In the case of Q = 2.0V, V _GS = 2.0V when the nMOS transistor 138 = ON, but in this case, the drain-source voltage V _DS = 0.75V.

Here, the drive current of the nMOS transistor 138 = 10 mA, the resistance value of the terminating resistors 116 and 117 =
Since 50Ω and load resistance = 25Ω, the voltage drop of the terminating resistors 116 and 117 is 0.25V as shown in FIG. 16, and in this case, the resistor 160 is not necessary.

In this case, if the power supply voltage VCCQ is lowered,
Since the resistors 160 to 164 are unnecessary, there is an advantage that the number of parts can be reduced.

However, as described above, the stubs 155 to 159 are used.
Since it is not possible to obtain the effect of suppressing the resonance of 1 by impedance matching, the length of the stubs 155 to 159 must be as short as possible.

In the second embodiment, the output circuit 110 of the microprocessor 90 and the SDRAMs 91 to 94 is used.
˜114 are composed of CMOS push-pull type whose power supply voltage is VCCQ, and the termination voltage VTT.
Is set to VCCQ / 2, it is possible to transmit a small-amplitude signal whose intermediate voltage is the termination voltage VTT.

Here, for example, when output circuit 110 outputs L level, voltage generation circuit 152 → termination voltage line 89 → termination resistors 116 and 117 → bus line 115.
→ output circuit 110 (nMOS transistor 138) → ground → current flows through a closed circuit consisting of voltage generation circuit 152.

When the output circuit 110 outputs the H level, the voltage generation circuit 151 → VCCQ power supply line 88 → output circuit 110 (pMOS transistor 137).
→ Bus line 115 → Termination resistors 116, 117 → Current flows through the closed circuit consisting of the voltage generation circuit 151.

As described above, according to the second embodiment, since the voltage generating circuit 150 is constructed by connecting the voltage generating circuits 151 and 152 in series, the voltage output terminal 154.
The voltage of the voltage output terminal 154 is V6 =
It can be maintained at 1.65V and the termination voltage VTT = V
6 = 1.65V stability can be secured.

In the second embodiment, when the bus line 115 is not transmitting a signal, the terminating resistor 11
Since no current flows through 6, 117, power consumption can be reduced.

Further, in the second embodiment, the termination voltage VTT is set to the microprocessor 90 and the SDRAM 91.
Since it is used as the reference voltage Vref required for ~ 94, the reference voltage Vref and the termination voltage VTT are made to coincide with each other so that an offset voltage is not generated in the input signal and a sufficient operation margin of the input signal is obtained. Can be secured.

Further, in the second embodiment, since the resistors 160 to 164 are connected to the branch points of the bus line 115, it is possible not only to prevent an excessive current from flowing to the output, but also the stubs 155 to 155. Even when 159 is required, when the reflected components of the signals generated at the stubs 155 to 159 flow into the bus line 115, the resistors 160 to 164 cut off the high frequency components, which distorts the transmission waveform. Has the advantage of being less likely to occur.

Therefore, this second embodiment is based on SDRA.
It can be said that it is suitable for a system in which M91 to 94 are mounted in a module (SIMM) and are connected to the bus line 115 of the board through the connector of the module.

On the other hand, in the structure of the first embodiment, in order to suppress the generation of the stubs 155 to 159, the SDRAM is
It can be said that it is suitable for a system in which 91 to 94 are directly connected to the bus line 115.

Third Embodiment FIG. 17 FIG. 17 is a circuit diagram showing an essential part of the third embodiment of the present invention. In the third embodiment, the bus wire 115 and the stub 156-
Connect the resistors 161 to 164 to the bus line 1
No resistor is connected between 15 and the microprocessor 90.
The configuration is similar to that of the embodiment.

Here, the SDRAMs 91 to 94 are replaced by SIMMs.
When mounted on a bus line 115 and stubs 155-1
It is easy to insert the resistors 161 to 164 between the microprocessor 90 and the resistor 59, but the microprocessor 90 uses a PGA (pin grid a).
rray) package and has a large number of pins.
There is often no place to put the resistor 160 shown in FIG.

Therefore, in the third embodiment, the resistors 161 to 161 are provided between the bus line 115 and the stubs 156 to 159.
164 to connect the bus line 115 and the microprocessor 9
The resistor 160 shown in FIG. 12 is not connected between 0 and 0.

Even if the resistor 160 shown in FIG. 12 is not used, the microprocessor 90 is connected to the end of the bus line 115 in most cases, and the terminating resistor 116 is used.
, The transmission signal distortion can be relatively reduced.

Further, in this case, if the output circuit 110 of the microprocessor 90 reduces the driving force of the transistor to have a relatively high internal resistance of about 100Ω, the resistor 160 shown in FIG. Even if it does not exist, it is configured to avoid an excessive current flow.

The internal resistance of the output circuit 110 is set to 100.
The pMOS transistor 1
There is a method of connecting a resistor in series to the output of the output circuit 110 in the vicinity of the output circuit 110, for example, on the chip or in the package, depending on the sizes of the 37 and nMOS transistor 138.

PMOS transistor 137 and nMOS
Depending on the size of the transistor 138, pMOS
The transistor 137 has a gate width of, for example, 5
The gate width of the nMOS transistor 138 may be set to 00 μm and the gate length may be set to 1 μm, for example.
For example, 200 μm, gate length, for example, 1 μm
It should be done.

On the other hand, when a resistor is connected in series to the output, the pMOS transistor 137 may have a gate width of, for example, 1000 μm and a gate length of, for example, 1 μm, and the nMOS transistor 138.
Has a gate width of 400 μm and a gate length of 1 μm, for example.

If the resistor connected in series with the output circuit 110 has a negative temperature coefficient, the output circuit 11
Since the internal resistance of the transistor of 0 has a positive temperature characteristic, it can be offset, which is preferable.

As a concrete example, it can be formed by using an amorphous semiconductor material generally called a thermistor.

As a simple method, a so-called diffusion layer formed on the semiconductor substrate may be used. In particular, the p-type diffusion layer has a larger temperature coefficient than the n-type diffusion layer and is suitable for this purpose.

Since these have the property that the resistance value decreases at high temperature, it is possible to cancel the phenomenon that the driving force is lowered at high temperature of the transistor.

Fourth Embodiment FIG. 18 FIG. 18 is a circuit diagram showing an essential part of the fourth embodiment of the present invention. The fourth embodiment of the present invention is provided with a temperature sensor 165,
The voltage V6 generated by the voltage generating circuits 151 and 152 is controlled by the temperature sensor 165, and the other points are the same as those in the third embodiment.

Here, the bus line 115 and the stubs 156 to 1
The resistors 161 to 164 are connected to the bus line 59 and the bus line 11
5 does not connect a resistor between the microprocessor 90 and the microprocessor 90 to reduce the drive power of the transistor of the output circuit 110 of the microprocessor 90, the temperature dependence of the drive power of the output circuit 110 of the microprocessor 90. Need to be careful.

This is because the MOS transistor has a negative driving current temperature coefficient, and the driving force decreases as the operating temperature rises.

Therefore, regardless of the operating temperature, the bus line 115
In order to keep the above signal amplitude constant, the voltage generation circuit 151,
It is preferable to give the voltage V6 output from 152 a positive temperature coefficient. For example, it is preferable that the value of V6 is 1.3 V at 25 ° C. and 1.65 V at 100 ° C.

The power supply voltage of the input / output circuit may depend on the temperature, and the power supply voltage of the main circuit may be constant, or the power supply voltage of the input / output circuit and the main circuit may depend on the temperature.

Further, such temperature compensation is performed by the bus line 11
It can be applied with or without a resistor connected to 5.

Fifth Embodiment FIG. 19 to FIG. 22 FIG. 19 is a circuit diagram showing an essential part of the fifth embodiment of the present invention. In the fifth embodiment, a termination voltage generating circuit 166 is provided instead of the voltage generating circuit 83 shown in FIG.

Correspondingly, the termination voltage generating circuit 166
To the terminal voltage generation circuit 166 and the VCCQ power supply line 167 that supplies the power supply voltage VCCQ = 2.0V to the
A VSSQ power supply line 168 for supplying Q is provided.

Further, in the fifth embodiment, the microprocessor 90 and the SDRAMs 91 to 94 are constructed so that the power supply voltage VCCQ is supplied from the VCCQ power supply line 167. Is configured similarly to the first embodiment shown in FIG.

In the termination voltage generation circuit 166, 171 is an operational amplifier, and 172 and 173 are voltage dividing resistors having the same resistance value.

In this termination voltage generating circuit 166, the power supply voltage VCCQ is divided by the voltage dividing resistors 172 and 173 into VCCQ / 2 =.
The voltage is divided into 1.0 V and supplied to the positive-phase input terminal (non-inverting input terminal) of the operational amplifier 171, and the output of the operational amplifier 171 is fed back to the negative-phase input terminal (inverting input terminal) of the operational amplifier 171. Operational amplifier 171
Of the terminal voltage VTT is obtained as the terminal voltage VTT.

Here, in the fifth embodiment, the termination voltage generating circuit 166, the voltage dividing resistors 172 and 173, and the data D.
The terminating resistor 117 for the bus line 115 provided corresponding to Q0 and the terminating resistor for the bus line provided corresponding to the data DQ1 to DQ7 are integrated into one chip,
SDRAM as the termination module (termination device) 174
It is packaged in the same size as 91-94.

FIG. 20 is a diagram schematically showing the termination module 174, in which 175 is the termination module body and 1 is the termination module body.
76 to 181 are terminating resistors for bus lines provided corresponding to the data DQ1 to DQ7, 182 to 200 are external terminals, and these external terminals 182 to 200 are SDRA.
It is provided at the same position as the corresponding external terminal of M91-94.

Therefore, in the fifth embodiment, as shown in FIG.
As shown in FIG. 1, the SDRAMs 91 to 94 and the termination module 174 are integrated as a memory stack 201 and mounted on the circuit board 202.

Therefore, in this fifth embodiment,
Supply of the power supply voltage VCCQ from the VCCQ power supply line 167 to the SDRAMs 91 to 94 is performed by the memory stack 20.
1 is performed.

In FIG. 21, 203 and 204 are vertical sub boards, and 205 and 206 are data DQ1 and DQ.
Bus lines provided corresponding to Q7, 207, 20
Reference numerals 8 and 209 denote connector parts.

In this case, the assembling cost can be reduced, the bus line can be made short, and the bus line can be made suitable for high-speed signal transmission.
Since the termination voltage VTT is generated near to 94, it is possible to prevent the reference voltage Vref from changing due to noise or the like.

The terminating resistors 116, 117, 176 ...
181 is the termination module, and the termination voltage generation circuit 1
It is also possible to make it separate from 66.

Further, in the fifth embodiment, the termination voltage generating circuit 166 is constructed as shown in FIG.

In the figure, reference numeral 211 is a VCCQ power supply line, 212 is a VSSQ power supply line, 213 and 214 are differential amplifier circuits, and in the differential amplifier circuit 213, 215 and 216 are enhancements forming a current mirror circuit serving as a load. Shape pMOS transistor.

Reference numerals 217 and 218 are enhancement type nMOS transistors which form drive transistors, and 2
19 is an enhancement type nMO that functions as a resistor.
It is an S transistor.

In the differential amplifier circuit 214, 22
0 is an enhancement type pMOS that functions as a resistor
Transistors 221, 222 are enhancement type pMOS transistors which form drive transistors, 22
3, 224 are enhancement type nMOSs that form a load.
It is a transistor.

Reference numeral 225 is an output circuit, 226 is an enhancement type pMOS transistor which forms a pull-up element, and 227 is an enhancement type nMOS transistor which forms a pull-down element.

When the terminating voltage generating circuit 166 is constructed in this manner, a stable terminating voltage VTT with a constant voltage can be obtained even if the power supply voltage VCCQ fluctuates.

In the fifth embodiment, the output circuit 110 of the microprocessor 90 and the SDRAMs 91 to 94 is used.
~ 114 is a CMO whose power supply voltage is VCCQ = 2.0V
Since it is configured as an S-type push-pull type and the termination voltage VTT is set to VCCQ / 2 = 1.0V, it is possible to transmit a signal whose intermediate voltage is the termination voltage VTT.

Here, for example, when the output circuit 110 outputs the L level, the termination voltage generating circuit 166.
→ Termination voltage line 89 → Termination resistors 116 and 117 → Bus line 1
15 → output circuit 110 (nMOS transistor 138)
→ ground → power supply voltage generating circuit (not shown) for generating power supply voltage VCCQ → VCCQ power supply line 167 → current flows through a closed circuit consisting of termination voltage generation circuit 166.

On the other hand, when the output circuit 110 outputs the H level, the VCCQ power supply line 167 → the output circuit 110 (pMOS transistor 137) → the bus line 1
15 → Termination resistors 116, 117 → Termination voltage generation circuit 16
6 → VSSQ power supply line 168 → power supply voltage generation circuit (not shown) for generating power supply voltage VCCQ → VCCQ power supply line 16
A current flows in a closed circuit of 7.

As described above, in the fifth embodiment,
The termination voltage generation circuit 166 uses the operational amplifier 171 to output the output voltage of the operational amplifier 171, that is, the termination voltage VT.
Since T is feedback-controlled, even when a current is output from the termination voltage generation circuit 166 to the termination voltage line 89 side, a current is output from the termination voltage line 89 side to the termination voltage generation circuit 166. Even when input, the stability of the termination voltage VTT = VCCQ / 2 = 1.0V can be ensured.

Further, in the fifth embodiment, when the bus line 115 is not transmitting a signal, the terminating resistor 11
Since no current flows through 6, 117, power consumption can be reduced.

In this fifth embodiment, the input / output circuit section is constructed in the same way as in the first embodiment, and the output drive circuit and the output circuits 110 to 114 are the power supply voltage for driving the main circuit. Since the power supply voltage VCCQ is 2.0 V, which is lower than VCC = 3.3 V, the power consumption can be reduced also from this point.

Further, in the fifth embodiment, the termination voltage VTT is set to the microprocessor 90 and the SDRAM 91.
Since it is used as the reference voltage Vref required for ~ 94, the reference voltage Vref and the termination voltage VTT are made to coincide with each other so that an offset voltage is not generated in the input signal and a sufficient operation margin of the input signal is obtained. Can be secured.

Further, according to the fifth embodiment, the input / output circuit section is constructed in the same way as in the first embodiment, and the output voltage is output as the power supply voltage of the output drive circuit for driving the output circuits 110-114. Power supply voltage VC as in circuits 110-114
Since CQ is supplied, a pMOS transistor that forms a pull-up element and an n-type that forms a pull-down element.
It is possible to drive the MOS transistor with good balance.

Sixth Embodiment FIG. 23, FIG. 24 FIG. 23 is a circuit diagram showing an essential part of a sixth embodiment of the present invention. In the figure, 228 is a VCC power supply line for supplying a power supply voltage VCC = 3.3V, and 229 is a power supply voltage VCCQ = 1.2V.
Is a VCCQ power supply line for supplying the power.

Further, 230 is a microprocessor, 231 is a signal input / output terminal for inputting / outputting signals,
Reference numeral 232 is a VCC power supply terminal for taking in the power supply voltage VCC, and 233 is a VCCQ power supply line for taking in the power supply voltage VCCQ = 1.2V.

Reference numeral 234 indicates a VCC power supply line for supplying the power supply voltage VCC to the internal circuit, and reference numeral 235 indicates the power supply voltage V.
VCCQ power supply line for supplying CCQ to an internal circuit,
Reference numeral 236 is a push-pull type output circuit.

In this push-pull type output circuit 236, 237 is a pMOS transistor which is a pull-up element, and 238 is an nMOS transistor which is a pull-down element.

Further, 240 is a bus line for transmitting signals, 241 is a terminal portion, 242, 243 are diodes for setting the forward voltage to 0.65V, and 244, 245 are resistors for setting the resistance value to 15Ω. is there.

Since the added value of the forward voltage of the diodes 242 and 243 is 1.3 V, the bus line 240
In the state where no signal is transmitted, the current does not flow in the terminal end 241.

246 is an SDRAM, and 247
Is a signal input / output terminal for inputting / outputting signals, 248 is a reference voltage input terminal to which 0.65 V is supplied as a reference voltage Vref, 249 is a VCC power supply terminal to which a power supply voltage VCC is supplied, and 250 is an input circuit. .

FIG. 24 is a diagram showing the characteristics of the terminal portion 241, where the horizontal axis shows the voltage of the bus line 240, and the positive side of the vertical axis shows the pMOS transistor 237 = ON, nMOS.
When the transistor 238 = OFF, VCCQ
The current value of the current i ₅ flowing from the power supply line 235 to the pMOS transistor 237 → bus line 240 → resistance 245 → diode 243 → ground is shown.

On the negative side of the vertical axis, pMOS transistor 237 = OFF and nMOS transistor 238 = ON.
In this case, the current i ₆ flows from the VCCQ power supply line 229 to the diode 242 → the resistor 244 → the bus line 240 → the nMOS transistor 238 → ground.

That is, in the sixth embodiment, pMO
S transistor 237 = ON, nMOS transistor 2
When 38 = OFF, the current i ₅ flows from the VCCQ power supply line 235 to the bus line 240 via the pMOS transistor 237, and the voltage of the bus line 240 starts to rise.

After that, when the voltage of the bus line 240 exceeds 0.65V which is the forward voltage of the diode 243, the diode 243 is turned on, and the current i ₅ also flows through the resistor 245 and the diode 243.

The voltage of the bus line 240 is 0.65V.
(Forward voltage of diode 243) + 15Ω (resistance 24
5 resistance) x 0.01 mA (pMOS transistor 2
Drive current of 37) = 0.8V.

On the other hand, the pMOS transistor 23
When 7 = OFF and nMOS transistor 238 = ON, the nMOS transistor 238 is transferred from the bus line 240.
The current i ₆ flows to the ground through the line, and the voltage of the bus line 240 drops.

Thereafter, when the voltage of the bus line 240 becomes lower than 0.65V which is the forward voltage of the diode 242, the diode 242 is turned on and the diode 242 is turned on.
And the current i ₆ also flows through the resistor 244.

The voltage of the bus line 240 is 1.2-
0.65V (forward voltage of diode 242) + 15Ω
(Resistance value of resistor 244) × 0.01 mA (driving current of nMOS transistor 238) = 0.4V.

As described above, according to the sixth embodiment, no current flows into the VCCQ power supply line 229 side even when the H level is output from the output circuit 236. Therefore, the termination voltage VTT = The stability of VCCQ = 1.2V can be secured.

Since the diodes 242 and 243 are in the non-conducting state at the time when the signal is input / output from the output circuit 236, the reflection of the transmission signal may occur until the diode 242 or the diode 243 is in the conducting state. However, since this reflection is minute, it does not substantially affect the signal transmission.

In addition, in the sixth embodiment, when the bus line 240 is not transmitting a signal, the termination unit 241 is used.
Since no current flows through the device, power consumption can be reduced.

In the sixth embodiment, the output circuit 236 has the power supply voltage VCC = 3.
Since the power source voltage VCCQ = 1.2V, which is lower than 3V, is used for driving, the power consumption can be reduced also from this point.

Further, in the sixth embodiment, when the signal is input / output, the terminal portion 241 is open as viewed from the output circuit 236, so that the voltage of the bus line 240 changes rapidly,
After that, the termination will be added.

As a result, when a large amount of load is connected to the bus line 240 and the effective characteristic impedance of the bus line 240 is small, the resistance values of the resistors 243 and 244 are made small in order to match this. Also,
A signal of sufficient amplitude can be obtained.

25. FIG. 25 is a circuit diagram showing an essential part of the seventh embodiment of the present invention. The seventh embodiment of the present invention is the terminal portion 241 shown in FIG.
The terminal part 252 having a different circuit configuration is provided, and the other parts are configured similarly to the sixth embodiment shown in FIG.

The terminal portion 252 is connected to the VCCQ power supply line 22.
9 and the bus line 240, the diode 2 shown in FIG.
A diode-connected enhancement type nMOS transistor 253 is connected instead of the diode 42 and the resistor 244, and a diode-connected nMOS transistor is connected between the bus line 240 and the ground instead of the diode 243 and the resistor 245 shown in FIG. 254 is connected.

Here, an nMOS having a diode connection is formed.
In the transistors 253 and 254, the relation between the voltage V applied between the drain and the source and the current I flowing between the drain and the source is I = β when the gain constant is β.
(V-VTH) becomes a ^2/2.

Therefore, the H level voltage of the transmission signal is set to 0.8.
If the V and L level voltages are set to 0.4V, the voltage V applied between the drain and source of the nMOS transistors 253 and 254 becomes 0.8V.

Therefore, the pMOS transistor 237
And the driving current of the nMOS transistor 238 is 10 mA.
Then, from 10 × 10 ⁻³ = β (0.8−0.65) ² , β = 0.44.

Here, β can be expressed by β = μC _OX W / L. Where μ is the effective mobility of electrons,
About 400 cm / V _S , C _OX is the gate capacitance per unit area.

Therefore, nMOS transistors 253, 2
54, the gate oxide film has a thickness of 10 nm and W / L = 33.
If it is 00, the characteristics of the terminal portion 252 can be set as shown in FIG.

In FIG. 26, the horizontal axis indicates the bus line 24.
The voltage i is 0, and on the positive side of the vertical axis, when the pMOS transistor 237 = ON and the nMOS transistor 238 = OFF, the current i flowing from the VCCQ power supply line 235 to the pMOS transistor 237 → bus line 240 → nMOS transistor 254. ₇ shows the current value.

On the negative side of the vertical axis, pMOS transistor 237 = OFF and nMOS transistor 238 = ON.
In this case, the current i ₈ flowing from the VCCQ power supply line 229 to the nMOS transistor 253 → bus line 240 → nMOS transistor 238 is shown.

That is, in the seventh embodiment, pMO
S transistor 237 = ON, nMOS transistor 2
When 38 = OFF, the current i ₇ flows from the VCCQ power supply line 235 to the bus line 240 via the pMOS transistor 237, and the voltage of the bus line 240 rises.

Thereafter, the voltage of the bus line 240 changes to the threshold voltage VTH = 0.6 of the nMOS transistor 254.
When the voltage exceeds 5V, the nMOS transistor 254 is turned on, and the current i ₇ flows through the nMOS transistor 254.

After that, the voltage of the bus line 240 is
ON resistance of nMOS transistor 254 × 0.01 mA
(Current drive capability of pMOS transistor 237) = 0.
It rises to 8V.

On the other hand, the pMOS transistor 23
When 7 = OFF and nMOS transistor 238 = ON, the nMOS transistor 238 is transferred from the bus line 240.
A current i ₈ flows to the ground via the, and the voltage of the bus line 240 drops.

Thereafter, the voltage of the bus line 240 changes to the threshold voltage VTH of the nMOS transistor 253 = 0.6.
When it becomes lower than 5V, the nMOS transistor 253 is turned on, and the current i ₈ flows through the nMOS transistor 253.

The voltage of the bus line 240 is 1.2-
ON resistance of nMOS transistor 253 × 0.01 mA
(Current drive capability of nMOS transistor 238) = 0.
It goes down to 4V.

As described above, according to the seventh embodiment, no current flows into the VCCQ power supply line 229 side even when the H level is output from the output circuit 236. Therefore, the termination voltage VTT = The stability of VCCQ = 1.2V can be secured.

Since the nMOS transistors 253 and 254 are in the non-conducting state at the time when the signal is input / output from the output circuit 236, the transmission signal is reflected until the nMOS transistor 253 or the nMOS transistor 254 becomes the conducting state. However, since the reflection is so small, it does not substantially affect the signal transmission.

In addition, in the seventh embodiment, when the bus line 240 is not transmitting a signal, the terminating unit 252 is used.
Since no current flows through the device, power consumption can be reduced.

Further, in the seventh embodiment, the output circuit 236 has the power supply voltage VCC = 3.
Since the power source voltage VCCQ = 1.2V, which is lower than 3V, is used for driving, the power consumption can be reduced also from this point.

Further, in the seventh embodiment, when the signal is input / output, the terminal portion 252 is opened as seen from the output circuit 236, so that the voltage of the bus line 240 changes rapidly,
After that, the termination will be added.

As a result, even if a large load is connected to the bus line 240 and the effective characteristic impedance of the bus line 240 is small, a signal with sufficient amplitude can be obtained.

According to the seventh embodiment, the nMOS
Since the internal resistances of the transistors 253 and 254 are larger than the resistance of the diode, the resistances 244 and 24 shown in FIG.
5 is unnecessary, and the circuit configuration can be simplified accordingly.

When the terminating unit 252 is applied as the terminating unit of the bus line connected to the SDRAM for inputting / outputting 8-bit data, it is integrated into a terminating module as shown in FIG. Modularization is preferred.

Numeral 255 is a terminal module body, 25
Reference numerals 6 and 257 are resistors for obtaining the reference voltage Vref.

Eighth Embodiment FIG. 28 to FIG. 32 FIG. 28 is a circuit diagram showing an essential part of the eighth embodiment of the present invention. In the eighth embodiment of the present invention, a termination unit 259 having a circuit configuration different from that of the termination unit 241 shown in FIG. 23 is provided.

This terminating portion 259 is connected to the VCCQ power supply line 22.
9 and the bus line 240, the diode 2 shown in FIG.
42 and the resistor 244, instead of the enhancement follower type nMOS transistor 26 forming a source follower circuit.
In addition to connecting 0, an enhancement type pMOS transistor 261 forming a source follower circuit is connected between the bus line 240 and the ground instead of the diode 243 and the resistor 245 shown in FIG.

That is, this terminal unit 259 is connected to these nMOs.
S transistor 260 and pMOS transistor 261
Comprised of a complementary source follower circuit.

Further, in the eighth embodiment, a bias voltage generating circuit 262 for supplying the bias voltages VN and VP to the terminal portion 259 is provided, and the other parts are the sixth embodiment shown in FIG. Is configured similarly to.

The bias voltages VN and VP and nMO
The threshold voltage V _{TH-n of the} S transistor 260,
Threshold voltage V of pMOS transistor 261
The relationship with _TH-p is VN-VP <V _TH-n + | V _TH-p |.

That is, when the bus line 240 is not transmitting a signal, the nMOS transistor 260 and the pMOS are connected.
The transistor 261 is set to be non-conductive.

Bias voltage generating circuit 262 is constructed as shown in FIG. In the figure, 264 is a VCC power supply line that supplies a power supply voltage VCC, and 265 is a VSS power supply line that supplies a power supply voltage VSS.

266 is an nMOS transistor 26
An operational amplifier 267 for generating a bias voltage VN for supplying 0 to the zero is an operational amplifier for generating a bias voltage VP for supplying to the pMOS transistor 261.

Further, 268 to 271 are operational amplifiers 266.
The reference voltage Vref ₂₆₆ to be supplied to a resistor for generating a reference voltage Vref ₂₆₇ to be supplied to the reference voltage Vref and the operational amplifier 267 is supplied to the input circuit 250.

Here, the operational amplifier 266 is constructed as shown in FIG. In the figure, reference numerals 272 and 273 denote differential amplifier circuits.
Reference numerals 4 and 275 denote enhancement type pMOS transistors that form a current mirror circuit that forms a load.

Reference numerals 276 and 277 are enhancement type nMOS transistors which form driving transistors.
78 is an enhancement type nMO that functions as a resistor.
It is an S transistor.

In the differential amplifier circuit 273, 27
9 is an enhancement type pMOS that functions as a resistor.
Transistors 280 and 281 are enhancement type pMOS transistors which form drive transistors, and
2, 283 are enhancement type nMOSs that form a load.
It is a transistor.

Reference numeral 284 is an output circuit, 285 is an enhancement type pMOS transistor which forms a pull-up element, and 286 is an enhancement type nMOS transistor which forms a pull-down element.

When the operational amplifier 266 is configured in this way, a stable bias voltage VN having a constant voltage can be obtained even with the voltage fluctuation of the power supply voltage VCC.

Further, the operational amplifier 267 is constructed as shown in FIG. In the figure, 287 and 288 are differential amplifier circuits, and in the differential amplifier circuit 287, 289,
Reference numeral 290 is an enhancement type pMOS transistor which constitutes a load current mirror circuit.

Further, 291 and 292 are enhancement type nMOS transistors which form drive transistors and 2
93 is an enhancement type nMO that functions as a resistor.
It is an S transistor.

In the differential amplifier circuit 288, 29
4 is an enhancement type pMOS that functions as a resistor
Transistors 295 and 296 are enhancement type pMOS transistors which form drive transistors, and
7 and 298 are enhancement type nMOSs that form a load
It is a transistor.

Reference numeral 299 is an output circuit, 300 is an enhancement type pMOS transistor which forms a pull-up element, and 301 is an enhancement type nMOS transistor which forms a pull-down element.

When the operational amplifier 267 is constructed in this way, it is possible to obtain a stable bias voltage VP with a constant voltage even when the power supply voltage VCC varies.

FIG. 32 is a diagram showing the characteristics of the terminal portion 259, in which the horizontal axis shows the voltage of the bus line 240, and the positive side of the vertical axis shows the pMOS transistor 237 = ON, nMO.
When S-transistor 238 = OFF, VCC
A current i flowing from the Q power supply line 235 to the pMOS transistor 237 → the bus line 240 → the pMOS transistor 261.
₉ shows the current value.

On the negative side of the vertical axis, pMOS transistor 237 = OFF and nMOS transistor 238 = ON.
In this case, the current i ₁₀ flows from the VCCQ power supply line 229 to the nMOS transistor 260 → bus line 240 → nMOS transistor 238.

That is, in the eighth embodiment, pMO
S transistor 237 = ON, nMOS transistor 2
When 38 = OFF, the current i ₉ flows from the VCCQ power supply line 235 to the bus line 240 via the pMOS transistor 237, and the voltage of the bus line 240 rises.

After that, the voltage of the bus line 240 is changed to VP-V _TH.
-When _P is exceeded, the pMOS transistor 261 turns on, and the current starts to flow in the pMOS transistor.
The voltage of the bus line 240 is an H level voltage, for example, 0.8.
Rises to V.

On the other hand, the pMOS transistor 23
When 7 = OFF and nMOS transistor 238 = ON, the nMOS transistor 238 is transferred from the bus line 240.
A current i ₁₀ flows to the ground via the, and the voltage of the bus line 240 drops.

After that, the voltage of the bus line 240 is VN-V.
_{When it} becomes lower than _TH-n , the nMOS transistor 260 is turned on, a current starts to flow through the nMOS transistor 260, and the voltage of the bus line 240 becomes the L level voltage,
For example, it drops to 0.4V.

As described above, according to the eighth embodiment, even when the H level is output from the output circuit 236, no current flows into the VCCQ power supply line 229, so that the termination voltage VTT = The stability of VCCQ = 1.2V can be secured.

At the time when a signal is input / output from the output circuit 236, the nMOS transistor 260 and the pMO
Since the S transistor 261 is in a non-conducting state, nMO
S transistor 260 or pMOS transistor 261
The reflection of the transmission signal may occur until the signal becomes conductive, but since the reflection is minute, it does not substantially affect the transmission of the signal.

In addition, in the eighth embodiment, when the bus line 240 is not transmitting a signal, the terminating unit 259 is used.
Since no current flows through the device, power consumption can be reduced.

The nMOS transistors 260 and p
Bias voltage V supplied to the MOS transistor 261
A bias voltage generating circuit 2 including a differential amplifier circuit is used so that N and VP are not generated by a voltage generating circuit by resistance division.
62 is provided because when a current is drawn from the source side,
This is to avoid that the gate voltage is modulated by the parasitic capacitance between the gate and the source and the source-follower function is lost.

33. Ninth Embodiment FIG. 33 is a circuit diagram showing an essential part of a ninth embodiment of the present invention. In the figure, 303 is an input circuit of the microprocessor, and 304 is a VC for supplying a power supply voltage VCC = 3.3V.
C power line.

Further, 305 is an output circuit of the microprocessor, 306 is a VCCQ power supply line for supplying a power supply voltage VCCQ = 1.2V, 307 is a depletion type nMOS transistor forming a pull-up element, and 308 is a pull-down element. Is an enhancement type nMOS transistor.

Reference numeral 309 is an input circuit of the SDRAM, 310 and 311 are enhancement type pMOS transistors which serve as loads, and 312 and 313 are enhancement type nMOS transistors which form a current mirror circuit.

Reference numeral 314 is a waveform shaping inverter, 315 is an enhancement type pMOS transistor, and 316 is an enhancement type nMOS transistor.

Reference numeral 317 is an output circuit, 318 is a depletion type nMOS transistor which forms a pull-up element, and 319 is an enhancement type nMOS transistor which forms a pull-down element.

Further, 320 is a VCCQ power supply line, 321 is a bus line which forms a signal transmission line, 322 and 323 are termination sections which terminate the bus line, and 324 to 327 are diodes which set the forward voltage to 0.65V, Reference numerals 328 to 331 are resistors having a resistance value of 15Ω.

Reference numeral 332 is a reference voltage generating circuit for generating a reference voltage Vref, and 333, 334 are diodes for setting the forward voltage to 0.65V, and 335, 336 are resistors.

In the ninth embodiment, pMOS transistor 311 → nMOS transistor 313 → resistor 3
A current iref flows from 36 → diode 334 → ground, and the voltage of the node 337, that is, the reference voltage Vref, is set to 0.65V which is the forward voltage of the diode 334.

As a result, when the bus line 321 is not transmitting a signal, the pMOS transistor 310 → nMO
S transistor 312 → bus line 321 → resistors 329, 3
31 → diodes 325, 327 → current i _IN flows to ground, and the voltage of the bus line 321 is also the same as the reference voltage Vref.
It is set to 0.65V.

For example, in the output circuit 305, when the nMOS transistor 307 = OFF and the nMOS transistor 308 = ON, the VCCQ power supply line 320 → diodes 324, 326 → resistor 328,
330 → bus line 321 → nMOS transistor 308 →
A current flows to the ground, and the voltage of the bus line 321 is, for example,
It drops to 0.4V.

As a result, the drain level of the nMOS transistor 312 becomes L level, and the output of the inverter 314 becomes H level.

On the other hand, for example, the output circuit 305
, NMOS transistor 307 = ON, nMO
When the S transistor 308 is turned off, VC
CQ power supply line 306 → nMOS transistor 307 → bus line 321 → resistors 329, 331 → diodes 325, 3
A current flows from 27 to ground, and the voltage of the bus line 321 rises to 0.8V, for example.

As a result, the drain level of the nMOS transistor 312 becomes H level and the output of the inverter 314 becomes L level.

In the ninth embodiment, the reference voltage Vre
Since f = 0.65V is set, when the L level signal is transmitted, it is longer than the time until the bus line 321 rises to 0.8V when the H level signal is transmitted.
It may take a long time for 1 to drop to 0.4V, but this is due to the fact that nM is the pull-down element of the output circuit.
This can be avoided by increasing the driving capability of the OS transistors 308 and 319.

As described above, according to the ninth embodiment, even when the H level is output from the output circuits 305 and 317, the current does not flow into the VCCQ power supply line 320 side, so that the termination voltage. It is possible to ensure the stability of VTT = VCCQ = 1.2V.

Since the diodes 324 to 327 are in the non-conducting state at the time when a signal is input / output from the output circuits 305 and 317, the transmission is performed until the diode 324, 325 or the diodes 326, 327 becomes the conducting state. Although signal reflection may occur, the reflection is so small that it does not substantially affect the signal transmission.

Further, in the ninth embodiment, the output circuits 305, 317 have the power supply voltage VCCQ = 1.3.0 which is lower than the power supply voltage VCC = 3.3V for driving the input circuits 303, 309 and the main circuit. Since it is driven at 2V, it is possible to reduce power consumption.

[0287]

According to the first aspect of the present invention, two voltage generating circuits are connected in series, and the voltage obtained by adding the voltages of these two voltage generating circuits is supplied to the output circuit.
Since the voltage at the connection point of these two voltage generating circuits is supplied to the terminating resistor as the terminating voltage, even if a current flows from the bus line to the terminating voltage line through the terminating resistor, The termination voltage can be maintained at a constant voltage value and the stability of the termination voltage can be ensured.

Further, according to the first invention, when the bus line is not transmitting a signal, no current flows through the terminating resistor, so that the power consumption can be reduced and at the same time,
Since the terminating voltage can be used as the reference voltage, the reference voltage and the terminating voltage can be matched, an offset voltage is not generated in the input signal, and a sufficient operation margin of the input signal can be secured.

According to the second aspect of the present invention, since the voltage generating circuit for outputting the termination voltage is configured to feedback control the termination voltage using the operational amplifier, the termination from the bus line is terminated. Even when the current flows through the resistance to the termination voltage line, the termination voltage can be maintained at a constant voltage value and the stability of the termination voltage can be ensured.

Further, according to the second invention, when the bus line is not transmitting a signal, no current flows through the terminating resistor, so that the power consumption can be reduced and at the same time,
Since the terminating voltage can be used as the reference voltage, the reference voltage and the terminating voltage can be matched, an offset voltage is not generated in the input signal, and a sufficient operation margin of the input signal can be secured.

[Brief description of drawings]

FIG. 1 is a principle explanatory diagram of an electronic device according to a first aspect of the invention.

FIG. 2 is a principle explanatory diagram of an electronic device according to a second aspect of the invention.

FIG. 3 is a circuit diagram showing a main part of the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a part of a microprocessor provided in the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing an operation of a part of the microprocessor provided in the first embodiment of the present invention.

FIG. 6 is a circuit diagram showing an operation of a part of the microprocessor provided in the first embodiment of the present invention.

FIG. 7 is a circuit diagram showing an operation of a part of the microprocessor provided in the first embodiment of the present invention.

FIG. 8 is a circuit diagram showing another example of an output control circuit, an output drive circuit, and an output circuit which constitute the microprocessor provided in the first embodiment of the present invention.

FIG. 9 is a circuit diagram showing the operation of another example of the output control circuit, the output drive circuit, and the output circuit that constitute the microprocessor provided in the first embodiment of the present invention.

FIG. 10 is a circuit diagram showing the operation of another example of the output control circuit, the output drive circuit, and the output circuit which form the microprocessor provided in the first embodiment of the present invention.

FIG. 11 is a circuit diagram showing operations of another example of the output control circuit, the output drive circuit, and the output circuit which constitute the microprocessor provided in the first embodiment of the present invention.

FIG. 12 is a circuit diagram showing a main part of a second embodiment of the present invention.

FIG. 13 is a circuit diagram showing a microprocessor provided in a second embodiment of the present invention.

FIG. 14 is a diagram showing static characteristics of an nMOS transistor forming an output circuit of a microprocessor provided in a second embodiment of the present invention.

FIG. 15 is a circuit diagram showing a part of the second embodiment.

FIG. 16 is a circuit diagram showing a part of the first embodiment.

FIG. 17 is a circuit diagram showing a main part of a third embodiment of the present invention.

FIG. 18 is a circuit diagram showing a main part of a fourth embodiment of the present invention.

FIG. 19 is a circuit diagram showing a main part of a fifth embodiment of the present invention.

FIG. 20 is a diagram schematically showing a termination module provided in a fifth embodiment of the present invention.

FIG. 21 is a schematic perspective view showing a main part of a fifth embodiment of the present invention.

FIG. 22 is a circuit diagram showing a termination voltage generating circuit provided in a fifth embodiment of the present invention.

FIG. 23 is a circuit diagram showing a main part of a sixth embodiment of the present invention.

FIG. 24 is a diagram showing characteristics of the terminal end portion provided in the sixth embodiment of the present invention.

FIG. 25 is a circuit diagram showing an essential part of a seventh embodiment of the present invention.

FIG. 26 is a diagram showing characteristics of a terminal end portion provided in the seventh embodiment of the present invention.

FIG. 27 is a diagram schematically showing a termination module obtained by packaging a termination unit provided in the seventh embodiment of the present invention.

FIG. 28 is a circuit diagram showing an essential part of an eighth embodiment of the present invention.

FIG. 29 is a circuit diagram showing a bias voltage generating circuit provided in an eighth embodiment of the present invention.

FIG. 30 is an nM of a terminating portion of the operational amplifier included in the bias voltage generating circuit provided in the eighth embodiment of the present invention.
FIG. 6 is a circuit diagram showing an operational amplifier that generates a bias voltage of an OS transistor.

FIG. 31 is a pM of a terminating portion of the operational amplifier included in the bias voltage generating circuit provided in the eighth embodiment of the present invention.
FIG. 6 is a circuit diagram showing an operational amplifier that generates a bias voltage of an OS transistor.

FIG. 32 is a diagram showing characteristics of a terminal end portion provided in the eighth embodiment of the present invention.

FIG. 33 is a circuit diagram showing a main part of a ninth embodiment of the present invention.

FIG. 34 is a circuit diagram showing an example of an electronic device in which a small amplitude signal is transmitted.

FIG. 35 is a circuit diagram showing an example of an interface circuit and a bus system applied to an electronic device that transmits a small amplitude signal.

FIG. 36 is a circuit diagram showing another example of an interface circuit and a bus system applied to an electronic device that transmits a small amplitude signal.

[Explanation of symbols]

 (Fig. 1) 43 termination voltage line 48 output circuit 51 bus line 52 termination resistor 56 input circuit (Fig. 2) 63 operational amplifier 67 termination voltage line 72 output circuit 75 bus line 76 termination resistor 80 input circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location 8839-5J H03K 19/00 101 Q

Claims (63)

[Claims] 1. A push-pull type output circuit is provided,
An electronic device comprising: a plurality of integrated circuits for inputting and outputting signals; and a bus line having both ends terminated by terminating resistors and shared by the plurality of integrated circuits. A first voltage generation circuit and a second voltage generation circuit that generates a second voltage are connected in series so that the first voltage can be added to the second voltage, and the first voltage and the first voltage An electronic device configured to supply a voltage obtained by adding the voltage of 2 as a power supply voltage to the output circuit and supply the second voltage as a termination voltage to the termination resistor. 2. A push-pull type output circuit is provided,
An electronic device comprising: a plurality of integrated circuits for inputting and outputting signals; and a bus line having both ends terminated by terminating resistors and shared by the plurality of integrated circuits. A first voltage generation circuit, and the first
Is supplied as a power supply voltage, a voltage obtained by dividing the first voltage is supplied to a first input terminal, an output terminal is connected to a second input terminal, and the first terminal is connected to the first output terminal.
A second voltage generating circuit having an operational amplifier adapted to obtain a second voltage having the same voltage as a voltage obtained by dividing the voltage of the output circuit, and the output circuit using the first voltage as a power supply voltage. And an electric device configured to supply the second voltage as a termination voltage to the termination resistor. 3. The electronic device according to claim 1, wherein the plurality of integrated circuits are connected to the bus line via a resistor connected to a branch point of the bus line. 4. The resistor has a resistance value capable of obtaining the same drive current as the drive current of the output circuit when there is no resistor when the power supply voltage supplied to the output circuit is increased. The electronic device according to claim 3, wherein the electronic device is provided. 5. The plurality of integrated circuits are connected to the bus line without a resistor, and are connected to the bus line via a resistor connected to a branch point of the bus line. The electronic device according to claim 1 or 2, characterized in that there is a thing. 6. A drive current value as seen from the bus line side of an output circuit of an integrated circuit connected to the bus line without passing through the resistor and a resistor connected to a branch point of the bus line. The electronic device according to claim 5, wherein the output current of the integrated circuit connected to the bus line is the same or substantially the same as the drive current value viewed from the bus line side. 7. The value of the characteristic impedance of the wiring connecting the integrated circuit connected to the bus line through the resistor and the resistor is equal to the resistance value of the resistor divided by two of the characteristic impedance of the bus line. 7. The electronic device according to claim 3, 4, 5 or 6, wherein the value is within a value obtained by adding the value of 1. 8. The integrated circuit connected to the bus line without passing through the resistor is adapted to take out an output through a resistor arranged near the output circuit. The electronic device according to 5, 6, or 7. 9. A resistor arranged near the output circuit is
9. The electronic device according to claim 8, which has a negative temperature coefficient. 10. The electronic device according to claim 8, wherein the resistor arranged near the output circuit is arranged in a package forming an integrated circuit. 11. A first voltage generated by the first voltage generating circuit.
3. The voltage of 1 changes depending on the operating temperature of some or all of the output circuits of the plurality of integrated circuits, and has a positive temperature coefficient. 3,
The electronic device of 4, 5, 6, 7, 8, 9 or 10. 12. A second voltage generated by the second voltage generating circuit.
12. The electronic device according to claim 11, wherein the voltage of V changes depending on operating temperatures of some or all of output circuits of the plurality of integrated circuits, and has a positive temperature coefficient. apparatus. 13. The first voltage generating circuit is controlled by a temperature detecting device attached to a part or all of the plurality of integrated circuits to control a part or all of the output circuits of the plurality of integrated circuits. 6. The first voltage having a positive temperature coefficient that changes the voltage value depending on the operating temperature is configured to generate the first voltage.
The electronic device according to 6, 7, 8, 9 or 10. 14. The second voltage generating circuit is controlled by a temperature detecting device attached to a part or all of the plurality of integrated circuits to control a part or all of output circuits of the plurality of integrated circuits. 14. The electronic device according to claim 13, wherein the electronic device is configured to generate a second voltage having a positive temperature coefficient that changes a voltage value depending on an operating temperature. 15. A first voltage generated by the first voltage generating circuit.
Voltage changes depending on the operating temperature of a part or all of the output circuit of the integrated circuit connected to the bus line without passing through the resistor, and has a positive temperature coefficient. The electronic device according to claim 5, 6, 7, 8, 9 or 10. 16. A second voltage generated by the second voltage generating circuit.
Voltage changes depending on the operating temperature of a part or all of the output circuit of the integrated circuit connected to the bus line without passing through the resistor, and has a positive temperature coefficient. The electronic device according to claim 15, wherein: 17. The first voltage generating circuit is controlled by a temperature detecting device attached to an integrated circuit connected to the bus line without passing through the resistor, and the first voltage generating circuit is connected to the bus line without passing through the resistor. 6. A first voltage having a positive temperature coefficient that changes the voltage value depending on the operating temperature of the output circuit of the connected integrated circuit. The electronic device according to 5, 6, 7, 8, 9 or 10. 18. The second voltage generating circuit is controlled by a temperature detecting device attached to an integrated circuit connected to the bus line without passing through the resistor, and the second voltage generating circuit is connected to the bus line without passing through the resistor. 7. A second voltage having a positive temperature coefficient that changes the voltage value depending on the operating temperature of the output circuit of the connected integrated circuit. 17. The electronic device according to 17. 19. The output circuit according to claim 1, wherein the p-channel insulated gate field effect transistor is a pull-up element and the n-channel insulated gate field effect transistor is a pull-down element.
3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1
The electronic device according to 3, 14, 15, 16, 17 or 18. 20. A complementary first inverter comprising an insulated gate field effect transistor for driving the p-channel insulated gate field effect transistor, and an insulated gate electric field for driving the n channel insulated gate field effect transistor. A complementary second inverter composed of an effect transistor is provided, and a power supply voltage of the same voltage as the power supply voltage supplied to the output circuit is supplied to these first and second inverters. 20. The electronic device according to claim 19, wherein the electronic device is provided. 21. The output circuit comprises a first n-channel insulated gate field effect transistor as a pull-up element and a second n-channel insulated gate field effect transistor.
Is configured as a pull-down element, and the threshold voltage of the first n-channel insulated gate field effect transistor is equal to or higher than the low level voltage of the signal output from the output circuit, and The voltage is set to be lower than the threshold voltage of the second n-channel insulated gate field effect transistor.
6, 7, 8, 9, 10, 11, 12, 13, 14, 1
The electronic device according to 5, 16, 17 or 18. 22. The output circuit comprises a depletion type first n-channel insulated gate field effect transistor as a pull-up element and an enhancement type second n-channel insulated gate field effect transistor as a pull-down element. The threshold voltage of the first n-channel insulated gate field effect transistor is equal to or higher than the low level voltage of the signal output from the output circuit. 5, 6,
7, 8, 9, 10, 11, 12, 13, 14, 15, 1
The electronic device according to 6, 17, or 18. 23. A terminating device having a plurality of terminating resistors packaged therein.
3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1
3, 14, 15, 16, 17, 18, 19, 20, 21
22. The electronic device according to item 22. 24. A terminating device formed by packaging a plurality of terminating resistors and a plurality of integrated circuits which are hierarchically arranged and integrated using a substrate. Claims 1, 2, 3, 4, 5, 6, 7, 8, 9,
10, 11, 12, 13, 14, 15, 16, 17, 1
The electronic device according to 8, 19, 20, 21 or 22. 25. The electronic device according to claim 23, wherein the terminating device has a reference voltage output terminal for outputting a terminating voltage as a reference voltage. 26. A terminating device formed by packaging a plurality of terminating resistors and the second voltage generating circuit in a package. 8,
9, 10, 11, 12, 13, 14, 15, 16, 1
The electronic device according to 7, 18, 19, 20, 21 or 22. 27. A terminating device in which a plurality of terminating resistors and the second voltage generating circuit are packaged, and a plurality of integrated circuits for inputting / outputting signals are hierarchically arranged using a substrate. It has what was integrated, and it is characterized by including 2, 3, 4, 5, 6, 7, 8, 9, 10, 1.
1, 12, 13, 14, 15, 16, 17, 18, 1
The electronic device according to 9, 20, 21 or 22. 28. The termination device comprises a reference voltage output terminal for outputting the second voltage output by the second voltage generating circuit as a reference voltage.
Alternatively, the electronic device according to 27. 29. A first differential amplifier circuit, wherein the operational amplifier is supplied with the first voltage as a power supply voltage, and uses first and second n-channel insulated gate field effect transistors as drive transistors, A first voltage is supplied as a power supply voltage, a second differential amplifier circuit having first and second p-channel insulated gate field effect transistors as drive transistors, and the first voltage is supplied as a power supply voltage. , A third p-channel insulated gate field effect transistor forming a pull-up element driven by the first differential amplifier circuit, and a third n forming a pull-down element driven by the second differential amplifier circuit. An output circuit comprising a channel-insulated gate type field effect transistor,
The connection point between the gate of the channel-insulated gate type field effect transistor and the gate of the first p-channel insulated gate type field effect transistor is connected to the first input terminal and the second
The connection point between the gate of the n-channel insulated gate field effect transistor and the gate of the second p-channel insulated gate field effect transistor is configured as the second input terminal, and the output end of the output circuit is configured as the output terminal. Claims 2, 3, 4, 5, 6, 7, 8,
9, 10, 11, 12, 13, 14, 15, 16, 1
7, 18, 19, 20, 21, 22, 23, 24, 2
The electronic device according to 5, 26, 27 or 28. 30. Of the terminating resistors at both ends of the bus wire,
The resistance value of one of the terminating resistors is set to be larger than the value of the effective characteristic impedance of the bus line and smaller than the value of the characteristic impedance of the bus line when there is no load. 1, 2, 3, 4, 5, 6,
7, 8, 9, 10, 11, 12, 13, 14, 15, 1
6, 17, 18, 19, 20, 21, 22, 23, 2
The electronic device according to 4, 25, 26, 27, 28 or 29. 31. First, second, and third input / output of signals
..Nth integrated circuits in this order, and the second and third integrated circuits
... Connecting to the bus line so that the nth integrated circuit is connected at a relatively narrow interval, and at the first integrated circuit side and the nth integrated circuit side of the bus line, first and second In the electronic device formed by connecting two terminating resistors, the second terminating resistor has a resistance value larger than the value of the effective characteristic impedance of the bus line and the characteristic impedance of the bus line when there is no load. An electronic device having a value smaller than the value. 32. An output circuit using the first p-channel insulated gate field effect transistor as a pull-up element and the first n-channel insulated gate field effect transistor as a pull-down element, and a second p-channel insulated gate field effect transistor. The effect transistor is a pull-up element, the second n-channel insulated gate field effect transistor is a pull-down element, and a first inverter for driving the first p-channel insulated gate field effect transistor, and a third p-channel insulated A gate type field effect transistor as a pull-up element, a third n-channel insulated gate field effect transistor as a pull-down element, and a second inverter for driving the first n-channel insulated gate field effect transistor, The output circuit is supplied to the first and second inverters. Integrated circuit power supply voltage source voltage and the same voltage, characterized in that it is configured to be supplied. 33. The power supply voltage to be supplied to the output circuit is supplied as a back bias voltage of the second and third p-channel insulated gate field effect transistors. Item 32. The integrated circuit according to Item 32. 34. An output circuit using the first n-channel insulated gate field effect transistor as a pull-up element and the second n-channel insulated gate field effect transistor as a pull-down element, wherein the first n-channel isolated transistor is provided. The threshold voltage of the gate type field effect transistor is set to a voltage that is equal to or higher than the low level voltage of the signal output from the output circuit and lower than the threshold voltage of the second n-channel insulated gate type field effect transistor. An integrated circuit characterized by. 35. A depletion type first n-channel insulated gate field effect transistor is used as a pull-up element,
An output circuit having the enhancement-type second n-channel insulated gate field effect transistor as a pull-down element is provided, and the threshold voltage of the first n-channel insulated gate field effect transistor is a signal output from the output circuit. An integrated circuit characterized by having a low level voltage or higher. 36. A terminating device which is packaged including a plurality of terminating resistors. 37. A terminating device which is packaged including a plurality of terminating resistors and a terminating voltage generating circuit. 38. The termination device according to claim 36, further comprising a reference voltage output terminal for outputting a reference voltage. 39. The termination device according to claim 36, 37 or 38 and a plurality of integrated circuits for inputting and outputting a signal, which are hierarchically arranged and integrated using a substrate. Electronic device to do. 40. An electronic device comprising a plurality of integrated circuits for inputting and outputting signals and a bus line shared by the plurality of integrated circuits, wherein a push-pull type output circuit is provided. Between the terminal voltage line supplying the voltage and the bus line,
The first non-linear element having the rising characteristic is connected in the forward direction, and the second non-linear element having the rising characteristic is connected in the forward direction between the bus line and the voltage line supplying a voltage lower than the termination voltage. And an end portion that is connected to the bus line to prevent current from flowing in the absence of a signal on the bus line. 41. The electronic device according to claim 40, wherein the first and second nonlinear elements are diodes. 42. The electronic device according to claim 40, wherein the first and second nonlinear elements are formed of a series circuit of a diode and a resistor. 43. The electronic device according to claim 40, wherein the first and second nonlinear elements are diode-connected insulated gate field effect transistors. 44. An n-channel isolation circuit, wherein the first non-linear element has a drain connected to a termination voltage line supplying a termination voltage, a source connected to the bus line, and a gate supplied with a first bias voltage. A gate type field effect transistor, wherein the second non-linear element has a source connected to the bus line, a drain connected to a voltage line supplying a voltage lower than the termination voltage, and a gate connected to a second bias voltage. 41. The electronic device of claim 40, wherein the electronic device is a p-channel insulated gate field effect transistor to which is supplied. 45. The value obtained by subtracting the second bias voltage from the first bias voltage is a threshold voltage of the first n-channel insulated gate field effect transistor and the second p-channel insulated gate field effect transistor. 45. The electronic device according to claim 44, wherein the electronic device is made smaller than a value added to the absolute value of the threshold voltage of the effect transistor. 46. A first differential amplifier circuit using first and second n-channel insulated gate field effect transistors as drive transistors, and first and second p-channel insulated gate field effect transistors as drive transistors. A second differential amplifier circuit, a third p-channel insulated gate field effect transistor forming a pull-up element driven by the first differential amplifier circuit, and the second differential amplifier circuit. And a first output circuit including a third n-channel insulated gate field effect transistor forming a pull-down element, the gate of the first n-channel insulated gate field effect transistor and the first p-channel insulation The connection point with the gate of the gate type field effect transistor is the first input terminal,
A connection point between the gate of the second n-channel insulated gate field effect transistor and the gate of the second p-channel insulated gate field effect transistor is a second input terminal,
A first operational amplifier having an output terminal of the first output circuit as an output terminal is provided, and an output terminal of the first operational amplifier is connected to a first input terminal, and a second operational amplifier of the first operational amplifier is connected. A first bias voltage generating circuit having a reference voltage supplied to an input terminal thereof, the first bias voltage generating circuit adapted to obtain the first bias voltage at an output terminal of the second operational amplifier, and fourth and fifth n-channel insulated gate type A third differential amplifier circuit using a field effect transistor as a drive transistor, a fourth differential amplifier circuit using fourth and fifth p-channel insulated gate field effect transistors as a drive transistor, and the third difference Sixth p-channel insulated gate field effect transistor forming a pull-up element driven by the dynamic amplification circuit and sixth n-channel insulation forming a pull-down element driven by the fourth differential amplification circuit A second output circuit formed of a gate type field effect transistor, and a connection point between the gate of the fourth n-channel insulated gate field effect transistor and the gate of the fourth p-channel insulated gate field effect transistor. The first input terminal,
A connection point between the gate of the fifth n-channel insulated gate field effect transistor and the gate of the fifth p-channel insulated gate field effect transistor is a second input terminal,
A second operational amplifier having an output terminal of the second output circuit as an output terminal is provided, and an output terminal of the second operational amplifier is connected to a first input terminal of the second operational amplifier. A reference voltage is supplied to an input terminal, and a bias voltage generation circuit including a second bias voltage generation circuit adapted to obtain the second bias voltage is provided at an output terminal of the second operational amplifier. 46. The electronic device according to claim 44 or 45. 47. A terminating device having the first and second nonlinear elements integrated therein, as claimed in claim 40, 41, 42, 43, 44, 45 or 46. Electronic device. 48. A terminating device comprising the first and second nonlinear elements and a terminating voltage generating circuit integrated with each other, 40, 41, 42, 43,
44. The electronic device according to 44, 45 or 46. 49. The electronic device according to claim 47, wherein the terminating device has a reference voltage output terminal for outputting the reference voltage. 50. A terminal device according to claim 47, 48 or 49, and a plurality of integrated circuits for inputting and outputting a signal, which are hierarchically arranged and integrated using a substrate. 40, 41, 42, 4 characterized in that
The electronic device according to 3, 44, 45, or 46. 51. A third nonlinear element having a rising characteristic is connected in a forward direction between a terminal voltage line supplying a terminal voltage and the bus line, and a voltage lower than the bus line and the terminal voltage. A fourth non-linear element having a rising characteristic is connected in the forward direction between the voltage line for supplying the voltage and the reference voltage necessary for the input circuit at the connection point between the third non-linear element and the fourth non-linear element. 40. 41, 42, 43, 4 configured to obtain a voltage.
The electronic device according to 4, 45, 46, 47, 48, 49 or 50. 52. The input circuits of the plurality of integrated circuits have first and second loads each having one end connected to a power supply line for supplying a power supply voltage, and a drain connected to the other end of the first load. ,
A first n-channel insulated gate field effect transistor having a gate connected to a source and a source connected to a reference voltage input terminal; a drain connected to the other end of the second load; and a gate connected to the first load. 7. A second n-channel insulated gate field effect transistor connected to the gate of an n-channel insulated gate field effect transistor and having a source connected to a signal input / output terminal. 40, 41, 42, 43, 44, 45,
The electronic device according to 46, 47, 48, 49, 50 or 51. 53. The electronic device according to claim 51, wherein the third and fourth nonlinear elements are diodes. 54. The electronic device according to claim 51, wherein the third and fourth nonlinear elements are formed by a series circuit of a diode and a resistor. 55. The electronic device according to claim 51, wherein the third and fourth nonlinear elements are diode-connected insulated gate field effect transistors. 56. A first non-linear element having a rising characteristic to be connected in a forward direction between a terminal voltage line supplying a terminal voltage and a bus line, and supplying a voltage lower than the bus line and the terminal voltage. And a second non-linear element having a rising characteristic that should be connected in the forward direction between the terminal device and the voltage line. 57. A first non-linear element having a rising characteristic to be connected in a forward direction between a termination voltage line for supplying a termination voltage and a bus line, and a voltage lower than the bus line and the termination voltage is supplied. A terminating device comprising a terminating voltage generating circuit and a second non-linear element having a rising characteristic that should be connected in the forward direction between the terminating voltage generating circuit and the terminating voltage generating circuit. 58. The termination device according to claim 56, wherein the first and second nonlinear elements are diodes. 59. The termination device according to claim 56, wherein the first and second nonlinear elements are formed of a series circuit of a diode and a resistor. 60. The termination device according to claim 56, wherein the first and second nonlinear elements are diode-connected insulated gate field effect transistors. 61. The first non-linear element should have its drain connected to a termination voltage line supplying a termination voltage,
An n-channel insulated gate field effect transistor whose source should be connected to the bus line and whose gate should be supplied with a first bias voltage; P-channel insulated gate type, which should be connected to a line, its drain should be connected to a voltage line supplying a voltage lower than said termination voltage, and its gate should be supplied with a second bias voltage 58. A termination device according to claim 56 or 57, which is a field effect transistor. 62. A reference voltage output terminal for outputting a reference voltage according to claim 56, 57, 58,
Termination device according to 59, 60 or 61. 63. 56, 57, 58, 59, 60,
An electronic device in which the terminating device described in 61 or 62 and a plurality of integrated circuits for inputting and outputting signals are integrated by arranging them hierarchically using a substrate.