JPH0724379B2 - Power-on reset circuit - Google Patents

Description

Detailed Description [Table of Contents] Outline Industrial field of application Conventional technology (Figs. 5 and 6) Problem to be solved by the invention Means for solving the problem Action Example 1st Example of the present invention (FIGS. 1 to 3) Second embodiment of the present invention (FIG. 4) Effect of the invention [Overview] Regarding a power-on reset circuit, a power capable of qualitatively controlling a voltage range to which power-on reset is applied. A power-on reset circuit having an inverter circuit that includes a first transistor on the high potential side and a second transistor on the low potential side and that inverts and outputs an input signal for the purpose of providing an on-reset circuit. A third transistor is provided in parallel with the first transistor, and a bias obtained by dividing a predetermined power source with a predetermined impedance element is provided at a gate of the third transistor. It applied to, configured to the transistors of the third on / off to control the voltage across the reset based on the threshold of the third transistor to which the bias is applied.

[Industrial application field]

The present invention relates to a power-on reset circuit, and more particularly to a power-on reset circuit capable of qualitatively controlling a reset voltage.

In RS latches and various flip-flops, assuming that the S and R terminals are at "L" level immediately after power is turned on,
It is unknown whether the output Q will be "H" or "L". According to the truth table, when S terminal and R terminal are "L"
Although it is Qn (holds the previous state), it is because there is no previous state immediately after turning on the power. Therefore, when actually using the RS latch or flip-flop, it is necessary to work to determine the output state of the IC immediately after the power is turned on. This is generally called initialization. This initialization generates a pulse of several ms (there is no time restriction, until the power supply voltage stabilizes) after turning on the power, adds it to the reset (R) terminal, and outputs the RS latch or flip-flop. Q is set to "L", and initial reset
Also known as power-on reset.

[Conventional technology]

A conventional power-on / reset circuit of this type is, for example, that shown in FIG. In FIG. 5, 1
Is a power-on reset circuit, and the power-on reset circuit 1 is a resistor R, a capacitor C and a diode D.
An integrator circuit 2 and an inverter 3 for waveform shaping,
It is composed by.

The power-on reset circuit 1 utilizes that the high input impedance of the C-MOSIC, an integrating circuit 2 is provided in the large time constant to the input circuit, the power supply as shown in Figure 6 V _DD
Delay time at the rising edge of the
I take it out as a signal). Although the inverter 3 has one stage here, this is for shaping the waveform, and if necessary, a plurality of stages (for example, 3 stages).
Step)

[Problems to be Solved by the Invention]

However, in such a conventional power-on reset circuit, since the voltage range to be reset is controlled by the CR integrating circuit 2, the voltage range depends on the charging / discharging time by the capacitance C. Therefore, there is a limit to the stability. Specifically, when mounted on a chip, the POR signal width also varies due to variations in R and C during the manufacturing process. Therefore, there is a problem that the reset voltage cannot be stably controlled.

Therefore, an object of the present invention is to provide a power-on reset circuit capable of qualitatively controlling the voltage range to which power-on reset is applied.

[Means for Solving the Problems]

In order to achieve the above object, a power-on reset circuit according to the present invention includes a first transistor on the high potential side and a second transistor on the low potential side, and an inverter circuit for inverting and outputting an input signal. An on-reset circuit, wherein a third transistor is provided in parallel with the first transistor, and a bias obtained by dividing a predetermined power supply by a predetermined impedance element is applied to the gate of the third transistor, Based on the threshold value of the biased third transistor, the third transistor is turned on / off to control the reset voltage.

[Action]

According to the present invention, a third transistor is provided in parallel with the first transistor of the inverter including the first transistor and the second transistor, and a predetermined impedance element is provided between the predetermined power sources at the gate of the third transistor. A divided bias potential is applied. Therefore, even if there are variations in the manufacturing process, the bias potential applied to the gate of the third transistor is determined by the voltage division ratio of the impedance element, and thus is hardly affected by the variations in the manufacturing process.

Therefore, when the divided bias potential is smaller than the threshold value of the third transistor, the third transistor is turned off and outputs the "L" level in the reset state, and the bias potential is the threshold value of the third transistor. When it is larger, the third transistor is turned on, a through current flows through the third transistor, and outputs "H" level in the non-reset state.
As a result, a desired reset voltage can be obtained accurately.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

1 to 3 are diagrams showing a first embodiment of a power-on reset circuit according to the present invention, which is an example constituted by CMOS transistors.

First, the configuration will be described. In FIG. 1, 11 is a power-on reset circuit, and the power-on reset circuit 11
Is a P-channel MO that receives the input signal at each gate
S-transistor Tr1 and N-channel MOS transistor Tr2
Composed of an inverter 12 and a P-channel MOS transistor Tr3 to which the output of the inverter 12 is input and which are connected in parallel,
N-channel MOS transistor Tr5 connected in series with Tr4
And a reset voltage control circuit 13 including resistors R _{1 to} R ₃ ,
A P-channel MOS transistor Tr6 and an N-channel MOS transistor whose gates receive the output of the reset voltage control circuit 13 respectively.
Inverter 14 consisting of transistor Tr7 and P channel M
OS transistor Tr8 and N-channel MOS transistor Tr
And an inverter 15 which outputs the output as an output signal of the power-on reset circuit 11 to the outside. That is, the reset voltage control circuit 13
Is a P-channel MOS transistor Tr4 in parallel with a high-potential-side transistor Tr3 of a normal inverter composed of a P-channel MOS transistor Tr3 (first transistor) and an N-channel MOS transistor Tr5 (second transistor).
Together with (a third transistor) provided, the resistance R ₃ provided in the transistor Tr5 of the low potential side, and the transistor Tr4
There is a resistor between the high potential side power source and the low potential side power source at the gate of
A voltage (bias) divided by R ₁ and R ₂ (predetermined impedance element) is applied. Here, in the present embodiment, the resistors R ₁ and R ₂ are used as the predetermined impedance elements, but the present invention is not limited to this, and a level shift diode may be used, for example.

In addition, V _DD is a high potential side power source, V _SS is a low potential side power source,
In this embodiment, V _SS is the ground potential (GND).

In the above configuration, the potentials at the points in FIG. If the voltage divided by resistor R ₁ and resistor R ₂ is smaller than the threshold of transistor Tr 4,
Reset voltage control circuit 1 with transistor Tr4 off
The output of 3 is “L” in the reset state. Then, when the potential of rises above the threshold T _{TH of the} transistor Tr4, the transistor Tr4 turns on, and the transistor Tr4 and the transistor Tr4
A through current flows between 5 and the resistor R ₃ . In this case, the potential due to the voltage drop of the resistor R ₃ rises, and the output of the reset voltage control circuit 13 becomes “H”. That is, as shown in the waveform diagram of the power supply voltage in FIG.
Then, the reset operation is performed from 0 to V1, and the reset operation is not performed from V1 to V _DD .

Hereinafter, an example in which the power-on / reset circuit 11 is specifically designed will be described.

When designing reset voltage at 2.3V R ₁ = 200KΩ, R ₂ = 260KΩ, R ₃ = 300KΩ, Tr4 threshold V
_{If TH} −1.0V (Pch), the output is “L” when V _DD is less than 2.3V and the output is “H” when V _DD is greater than 2.3V. The voltage waveform diagram of each part at this time is shown in Fig. 3. Be done. In the figure, the thick solid line is the voltage waveform of the output representing the power-on reset operation of the power-on reset circuit 11, the solid line is the voltage waveform of V _DD , and the broken line is the waveform representing the potential of.

The reset voltage value can be easily changed by changing R ₁ and R ₂ . In addition, a chip can be actually produced by the power-on reset circuit 11 to obtain a desired reset operation.

As described above, in this embodiment, the transistor Tr
3, the transistor Tr3 of the inverter consisting Tr5 transistor Tr4 provided in parallel, the gates of the Tr4 applies a bias voltage by a resistance division of R ₁ and R _2. Therefore,
Depending on the magnitude relationship between the bias applied to Tr4 and its threshold value, Tr4 is turned on / off and reset voltage control circuit 13
Output level is limited to an appropriate level of "H" or "L", and a desired reset voltage can be obtained. In this case, the bias potential applied to the gate of even if there are variations transistor Tr4 in the production process the resistance R _1, R ₂
Since it is determined by the voltage division ratio of, the voltage applied to the reset can be stably controlled without being affected by the variation in the manufacturing process.

Also, in the conventional power-on reset circuit that used CR as shown in FIG. 5, tr, tf, tw, etc. are subject to considerable rules. Since it responds, the circuit operation becomes stable.

The first embodiment described above is an example in which the input is connected to GND and the power-on reset circuit 11 is used for the power-on reset operation which is the original purpose.
The reason why the reset circuit 11 is provided with the transistor Tr3 that is not directly involved in the circuit operation is as follows.

FIG. 4 is a second diagram of the power-on reset circuit according to the present invention.
It is a figure which shows an Example, and the circuit structure itself is the same structure as what is shown in FIG. The input on the V _DD side is added to the input of the power-on reset circuit 11 shown in FIG. Therefore, by setting the input to V _DD side, the forced reset can be controlled within the range of V _DD > reset voltage.
Simulation enables confirmation of reset operation and non-reset operation. Thus transistor Tr3
If the forced reset can be controlled by providing the above, the evaluation becomes convenient when the system is evaluated.

〔The invention's effect〕

According to the present invention, the voltage range for power-on reset can be qualitatively controlled, and the control accuracy of the circuit can be improved.

[Brief description of drawings]

1 to 3 are diagrams showing a first embodiment of a power-on reset circuit according to the present invention. FIG. 1 is its circuit diagram, FIG. 2 is its timing chart, and FIG. 3 is its power-on reset circuit. FIG. 4 is a voltage waveform diagram showing a reset operation, and FIG. 4 is a second diagram of the power-on reset circuit according to the present invention.
FIG. 5 is a circuit diagram showing a conventional power-on / reset circuit, FIG. 5 is a circuit diagram thereof, and FIG. 6 is a timing chart thereof. 11 …… Power-on reset circuit, 12, 14, 15 …… Inverter, 13 …… Reset voltage control circuit, Tr1, Tr6, Tr8 …… P-channel MOS transistor, Tr2, Tr7, Tr9 …… N-channel MOS transistor, Tr3 ...... P-channel MOS transistor (first transistor), Tr4 ...... P-channel MOS transistor (third transistor), Tr5 ...... N-channel MOS transistor (second transistor), R _1, R ₂ ...... resistance (Predetermined impedance element), R ₃ ... resistance, V _DD ... high potential side power supply, V _SS ... low potential side power supply.

Claims (1)

[Claims] 1. A power-on reset circuit comprising a first transistor on the high potential side and a second transistor on the low potential side, and having an inverter circuit for inverting and outputting an input signal, A third transistor is provided in parallel with the first transistor, and a bias obtained by dividing a predetermined power source by a predetermined impedance element is applied to the gate of the third transistor, and the bias is applied to the third transistor. The power-on reset circuit is characterized in that the voltage applied to the reset is controlled by turning on / off the third transistor on the basis of the threshold value.