JPH07249632A - Electronic component connection structure and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Object] To provide a connection structure for an electronic component, which has a small stress generated inside the solder bump 3, has a simple structure, and is easy to manufacture. [Structure] The pads 5 of the semiconductor chip 1 and the pads 6 of the substrate 2 are connected by solder bumps 3. The solder bumps 3 are in the shape of a lump. Inside the solder bump 3, a metal core member 4 is provided. Core member 4
Is composed of a circular bottom portion 41 and a cylindrical pin portion 42. The core member 4 is attached to the pad 5 of the semiconductor chip 1 with the solder 7
Mounted by.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connection structure for electronic parts, and more particularly to a connection structure for electronic parts using solder bumps.

[0002]

2. Description of the Related Art In a method of connecting electronic components using solder bumps, a large number of connection terminals can be connected at one time. Therefore, this connecting method is suitable for connecting electronic components having a large number of connecting terminals. For example, in the connection of bare chips having several hundreds of connection terminals, this method has been widely adopted. Here, the bare chip refers to a bare integrated circuit chip that is not enclosed in a package.

However, when the bare chip and the substrate are connected by solder bumps, a failure of the connecting portion often occurs. The cause of this failure is that the coefficient of thermal expansion differs between the LSI chip and the substrate on which it is mounted. When operating, L
SI chips generate heat. This heat causes the LSI chip and the substrate to expand. However, the thermal expansion coefficient differs between the LSI chip and the substrate. Therefore, L
The SI chip and the substrate have different expansion lengths. As a result, stress is generated inside the solder bumps that connect the LSI chip and the substrate. This stress is generated when the LSI chip is in operation, and disappears when the LSI chip is at rest. Therefore, stress is repeatedly generated inside the solder bump. The repeated stress causes fatigue of the solder bump. The fatigued solder bumps will eventually be destroyed. As a result, a failure occurs at the connecting portion between the LSI chip and the substrate.

An example of the technique for preventing the above-mentioned failure of the connection structure is described in "MEL Chip, Interconnection Technology, B.L.S.C." by N. Matsui, S. Sasaki and T. Osaki.
"Stucd Solder Bumps" Proceeding I E E 37th Electronic Components Conference Page 573-578 (N.Matsui, S.Sasaki, T.Ohsaki "VLSI Chip
Interconnection Technology Using StackedSolder Bum
ps, "Proc. IEEE 37th Electronic Components Conf.,
pp.573-578, May 1987.). In this technique, stress inside the solder bumps is reduced by stacking a plurality of solder bumps.

[0005]

However, in this technique, the structure of the solder bump is extremely complicated. Also, the manufacture of solder bumps is complicated and difficult.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to provide a connection structure for electronic parts, which has less stress inside the solder bumps, has a simple structure, and is easy to manufacture.

To achieve this object, in the connection structure for electronic parts of the present invention, a metal core member is provided in the solder bump.

Further, in another embodiment of the present invention, a metallic core member is provided inside the solder bumps formed in a zigzag shape.

In another embodiment of the present invention, the shape of the core member is variously modified depending on the application.

In another embodiment of the present invention, a first step of attaching the core member to the pad of the first electronic component and a second step of applying a predetermined amount of solder paste onto the pad of the second electronic component. A method for connecting electronic components, which includes a step, a third step of inserting the core member into the solder paste, and a fourth step of heating and melting the solder paste, and then cooling and solidifying the solder paste. Provided. In this method of connecting electronic components, the amount of the solder paste applied is an amount that takes on a zigzag shape due to surface tension when melted in the fourth step.

In another embodiment of the present invention, the first step of attaching the core member to the pad of the first electronic component, the second step of inserting the annular solder into the core member, and the core member A third step of positioning the first electronic component on the second electronic component so that it is located on the pad of the second electronic component, and heating and melting the annular solder, and then cooling. And a fourth step of solidifying the electronic component are provided. In this method of connecting electronic components, the amount of solder that forms the annular solder is an amount that forms a looped shape due to surface tension when melted in the fourth step.

Furthermore, the semiconductor device used in the connection structure for electronic parts of the present invention includes a bare chip and a core member attached to the pad of the bare chip. Also,
To the core member of this semiconductor device, solder is attached in an amount sufficient to form a solder bump having a staggered shape during reflow soldering.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1, in the connection structure for electronic components of this embodiment, a semiconductor chip 1 and a substrate 2 are connected by solder bumps 3.

The semiconductor chip 1 is a bare chip. A plurality of pads 5 are provided on one surface of the semiconductor chip 1. The pads 5 are arranged in a matrix.
The pad 5 is composed of laminated metal layers. The pad 5 has a circular shape with a diameter of 1 mm.

The substrate 2 has a ceramic substrate 9 containing alumina as a base material, and an organic insulating layer 8 provided on the ceramic substrate 9. The organic insulating layer 8 is formed on the surface of the ceramic substrate 9 facing the semiconductor chip 1. A plurality of pads 6 are provided on the organic insulating layer 8. The pads 6 are arranged in a matrix. Each pad 6 faces the corresponding pad 5. Pad 6
It is composed of stacked metal layers. Pad 6
Is a circle having a diameter of 1 mm.

The solder bumps 3 electrically and mechanically connect the pads 5 of the semiconductor chip 1 and the pads 6 of the substrate 2. The solder bumps 3 are formed in a zigzag shape.

A core member 4 is provided inside the solder bump 3. The core member 4 is attached to the pad 5 of the semiconductor chip 1 by the solder 7. Solder 7
Connects the pad 5 of the semiconductor chip 1 and the core member 4 electrically and mechanically. The melting point of the solder 7 is higher than that of the solder 10 forming the solder bump 3. Next, details of the shapes of the solder bumps 3 and the core member 4 will be described.

Referring to FIG. 2A, the core member 4 is composed of a circular bottom portion 41 and a columnar pin portion 42. The bottom portion 41 and the pin portion 42 are integrally formed. The diameter L1 of the bottom portion 41 is 1.0 mm. Bottom 4
The thickness L2 of 1 is 0.015 mm. The height L3 of the pin portion 42 is 0.0875 mm. The diameter L4 of the pin portion 42 is 0.047 mm. Bottom 41 and pin 4
The cross-sectional shape of the part connecting 2 with radius R = 0.01 m
It is an arc of m.

Referring to FIG. 2B, the solder bump 3
The diameter L8 of the upper end and the lower end is 1.0 mm. The diameter L5 of the central portion of the solder bump 3 is 0.074 mm. The height L6 of the solder bump 3 is 0.1 mm.

Referring to FIG. 2C, the distance L7 between the lower end of the pin portion 42 and the pad 6 is 0.0125 mm.

The dimensions of the respective portions of the core member 4 shown above can be changed within an appropriate range. The height L3 of the pin portion 42 can be changed within the range of 0.05 mm to 0.1 mm. The diameter L4 of the pin portion 42 is 0.02 m
It can be changed within the range of m to 0.08 mm. The distance L7 between the lower end of the pin portion 42 and the upper surface of the pad 6 is 0.
It can be changed within the range of 01 mm to 0.02 mm. The size of each part of the core member 4 needs to be set to be suitable for forming the solder bumps 3. More specifically, the dimensions of each part of the core member 4 must be determined so that the solder bumps 3 naturally form a staggered shape due to the surface tension of the solder. Therefore, the size of each portion of the core member 4 changes depending on the type of solder forming the solder bump 3.

Next, the material of each member shown in FIG. 1 will be described in detail.

The material of the pads 5 and 6 is gold or copper.

An example of the material of the solder 7 is gold tin solder. The solder 7 is the solder 1 that constitutes the solder bump 3.
It must have a melting point higher than zero.

The material of the core member 4 preferably satisfies the following two conditions. The first condition is that the coefficient of thermal expansion is smaller than that of the solder 10 forming the solder bump 3. The second condition is that the Young's modulus should be as large as possible. The first condition has priority over the second condition. That is, among the materials having a smaller coefficient of thermal expansion than the solder 10, a material having a Young's modulus as large as possible may be selected. It has been found as a result of simulation that the stress applied to the connecting portion is reduced when a material satisfying these conditions is used. Materials that satisfy these conditions include gold, silver, copper alloys and kovar.

An example of the material of the solder 10 forming the solder bump 3 is eutectic solder of tin and lead. Solder 10
Must have a melting point lower than that of solder 7. Next, a suitable combination of materials will be described.

When the material of the pad 5 is gold, the solder 7
Gold tin solder is a good material. This is because the wettability of the solder 7 is good in this combination.

When the material of the core member 4 is gold or silver, the material of the solder 10 constituting the solder bump 3 is preferably tin-lead eutectic solder. This is because the coefficient of thermal expansion of the core member 4 is smaller than that of the solder bump 3.

When the material of the core member 4 is gold or silver and the material of the solder 10 is a eutectic solder of tin-lead, the core member 4 is preferably plated. This is to prevent gold and silver from diffusing into the solder 10. Copper can be mentioned as a suitable plating material. Next, a method of forming the connection structure of FIG. 1 will be described with reference to the drawings.

Referring to FIG. 3, in the first step, the core member 4 is attached to the pad 5 of the semiconductor chip 1. If necessary, the core member 4 is plated in advance. The core member 4 is attached by reflow soldering the solder 7 applied on the pad 5.
Reflow soldering is preferably performed without using flux. Since the flux is not used, it is possible to prevent the semiconductor chip 1 from being damaged by the flux. In order to perform the reflow soldering without using the flux, the operation may be performed in a gas such as nitrogen and argon.

Referring to FIG. 4A, in a second step, the solder 10 is applied on the pads 6 of the substrate 2. The solder 10 is applied by a screen printing method. Solder 10
Is adjusted so that the solder bumps 3 are formed in a zigzag shape.

The optimum amount of the solder 10 depends on the size of each part of the core member 4 and the material of the solder 10. In particular, the surface tension of the solder 10 is a major factor in determining the optimum amount of the solder 10. It is extremely difficult to theoretically predict the optimum amount of the solder 10. The optimum amount of solder 10 is determined by experiment. When the amount of the solder 10 is large, the solder bump 3 has a shape in which the central portion is swollen. Solder 10
If the amount of is small, the upper part of the solder bump 3 becomes small. Qualitatively, the diameter L of the pin portion 42 of the core member 4
When 4 is large, a large amount of solder 10 is required.
When the diameter L4 of the pin portion 42 of the core member 4 is small, a small amount of solder 10 is sufficient.

Referring to FIG. 4B, the core member 4 is inserted into the solder 10 in the third step. Core member 4
The position of the semiconductor chip 1 is adjusted so that the lower end of the pin portion 42 and the upper surface of the pad 6 have a predetermined distance.

Referring to FIG. 4C, the solder 10 is reflow-soldered in a fourth step. First,
The solder 10 is heated. During heating, the semiconductor chip 1 and the substrate 2 are fixed horizontally. The heated solder 10 melts. The melted solder 10 is pulled upward by the effect of surface tension. Lifted solder 1
0 has a jagged shape due to the effect of surface tension. After this, the solder 10 is cooled. The cooled solder 10 solidifies. The solidified solder 10 has a staggered shape.

Next, the result of the simulation for verifying the effectiveness of this embodiment will be described.

With reference to FIG. 5A, in this simulation, the stress characteristics of a single solder bump 3 were simulated. The position of the solder bump 3 is the outermost periphery of the substrate 2. The characteristics of each member were set to those shown in FIG. The constraint condition that the stress in the solder bump 3 is 0 at a temperature of 23 ° C. was imposed. Under this constraint, the stress inside the solder bump 3 at a temperature of 125 ° C. was simulated. The simulation method is the finite element method. In order to compare the characteristics, the stress characteristics of the connection structure having a shape different from that of the solder bump 3 were also simulated. Specifically, (i) a shape with a bulged center, (ii) a staggered shape without the core member 4, (iii) a shape with only the core member 4,
(Iv) Four types of structures of the solder bump 3 of this embodiment were simulated. The result is shown in FIG.

In FIG. 5 (c), the portion indicated by Max is the portion where the maximum principal stress is maximum. The stress in this portion is called the maximum stress. The ratio of the maximum stress of each structure is the stress ratio. Regarding the stress ratio, the stress of the structure (i) was set to 1. As a result, the stress ratio of the structure (ii) is 0.6
It was 2. The stress ratio of the structure (iii) was 0.63. The stress ratio of the solder bump 3 of this embodiment is 0.51.
Met. That is, it was verified that the solder bump 3 of the present embodiment has a smaller stress that acts when the temperature rises, as compared with the other structures.

As described above, in this embodiment, the core member 4 is provided in the solder bump 3. With such a structure, the effect that the internal stress generated when the temperature rises can be reduced is achieved. Further, the electronic component connection structure of this embodiment is simple in structure. Furthermore, the electronic component connection structure of this embodiment is easy to manufacture.

Next, a second embodiment of the present invention will be described with reference to the drawings. The feature of this embodiment lies in the structure of the core member 4.

6 (a) to 6 (f) show the structure of the core member 4 of six types.

The structure shown in FIG. 6A is the core member 4 of the first embodiment.

In the structure shown in FIG. 6B, the pin portion 4
2 is sharp.

In the structure shown in FIG. 6C, the pin portion 4
The cross section of 2 is elliptical. This structure is effective when the distance between the pads 5 and 6 is minute.

In the structure shown in FIG. 6D, the pin portion 4
A hole 425 is provided inside the No. 2. In this structure,
Since the solder 10 enters the inside of the hole 425, as shown in FIG.
A stronger connection can be realized than the structure of.

In the structure shown in FIG. 6E, the pin portion 4
2 is composed of a pin portion 421 and a pin portion 422. A gap is provided between the pin portion 421 and the pin portion 422. In this structure, the solder 10 enters the gap between the pin portions 421 and 422, so that a stronger connection can be realized than in the structure of FIG. 6A.

In the structure shown in FIG. 6F, the pin portion 4
2 is composed of four parts, a pin part 421, a pin part 422, a pin part 423 and a pin part 424. A gap is provided between the pin portions 421 to 424.
In this structure, the solder 10 enters the gap between the pin portions 421 to 424, so that a stronger connection can be realized than in the structure of FIG. 6A.

As described above, in this embodiment, the core member 4 is formed in various structures. Each structure should be chosen according to the circumstances in which it will be used. Further, the features of each structure may be combined to form another structure. For example, by combining the structural features of FIG. 6 (b) with the structural features of FIG. 6 (e), two pointed pin portions 4
21 and the pin portion 422, a structure in which the pin portion 42 is formed is obtained.

Next, a third embodiment of the present invention will be described with reference to the drawings. This embodiment relates to a method of forming the solder bump 3. With respect to other structures, the structure of this embodiment is the same as that of the first embodiment.

The first step of this embodiment is the same as that of the first embodiment.

Referring to FIG. 7A, the second embodiment
In the step of, the soldering 11 is inserted into the pin portion 42 of the core member 4. The solder ring 11 is an annular solder. A hole 111 is provided in the center of the solder ring 11. The hole 111 is inserted into the pin portion 42. The solder ring 11 is composed of an amount of solder suitable for forming the solder bumps 3 having a staggered shape.

Referring to FIG. 7B, in the third step, the semiconductor chip 1 is positioned on the substrate 2. The position of the semiconductor chip 1 is adjusted so that a predetermined gap is provided between the tip of the pin portion 42 and the upper surface of the pad 6.

Referring to FIG. 7C, in the fourth step, the soldering 11 is reflow-soldered. This step is the same as the fourth step of the first embodiment. After the completion of the fourth step, the solder bumps 3 formed in a zigzag shape are obtained.

In this embodiment, the solder ring 11 is inserted into the pin portion 42. The solder ring 11 is composed of a proper amount of solder. Therefore, it is not necessary to adjust the amount of solder applied to the pad 6. Further, the structure of FIG. 7A can be shipped as a product. In this case, the user who purchases this does not need to adjust the amount of solder.

Next, a fourth embodiment of the present invention will be described with reference to the drawings. The feature of this embodiment lies in the structure of the substrate 2. In this embodiment, the core member 4 is the pad 6 of the substrate 2.
It is provided in.

Referring to FIG. 8, the substrate 2 of this embodiment is
It is composed of only the ceramic substrate 9. Pads 6 are provided on the upper surface of the ceramic substrate 9. The core member 4 is mounted on the pad 6. The core member 4 is
It is attached by solder 7. The structure and material of the pad 6, the solder 7 and the core member 4 are the same as those of the first embodiment.

With reference to FIG. 9, in a state where the semiconductor chip 1 and the substrate 2 are connected, the pads 5 and 6 are connected by the solder bumps 3. The solder bump 3 has a staggered shape.

In this embodiment, the core member 4 is provided on the substrate 2. In this embodiment, the same effect as that of the first embodiment is achieved.

Next, another embodiment of the present invention will be described.

The first feature of the present invention is to provide the core member 4 inside the solder bump 3. A second feature of the present invention is that the core member 4 is provided inside the solder bump 3 having a staggered shape.
Is to be provided. A third feature of the present invention is that the solder bumps 3 are formed in a staggered shape by utilizing surface tension. The fourth feature of the present invention is that
The purpose is to change the shape of the core member 4 in various ways. The fifth feature of the present invention is to insert the solder ring 11 into the pin portion 42. The sixth feature of the present invention is to provide the core member 4 on the substrate 2.

The gist of the present invention lies in these characteristics and can be variously implemented other than the above-mentioned embodiments. For example, the features of the first to fourth embodiments can be combined with each other. The connection structure of the present invention can also be used for connections other than bare chips.

In the present invention, the amount of solder that forms the solder bumps 3 and the shape of the core member 4 should be appropriately changed according to the application situation.

[0063]

As described above, in the present invention, the core member 4 is provided in the solder bump 3. With such a structure, the effect that the internal stress generated when the temperature rises can be reduced is achieved. This effect can be further enhanced by forming the solder bumps 3 into a zigzag shape.

Further, the connection structure of the electronic parts of this embodiment is as follows.
The structure is simple. Furthermore, the electronic component connection structure of this embodiment is easy to manufacture.

[Brief description of drawings]

FIG. 1 is a diagram showing a connection structure of an electronic component according to a first embodiment of the present invention.

FIG. 2 is a view showing a detailed structure of a core member 4.

FIG. 3 is a diagram showing a method for manufacturing a connection structure for electronic components according to the first embodiment.

FIG. 4 is a diagram showing a method for manufacturing a connection structure for electronic components according to the first embodiment.

5A and 5B are diagrams showing setting conditions of a simulation for verifying the effectiveness of the connection structure of the electronic component of the first embodiment. (C) is a figure which shows the result of the simulation which verifies the effectiveness of the connection structure of the electronic component of 1st Example.

FIG. 6 is a diagram showing a structure of a core member 4 according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a method of manufacturing a connection structure for electronic components according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a part of a connection structure of an electronic component according to a fourth embodiment of the present invention.

FIG. 9 is a diagram showing a connection structure of an electronic component according to a fourth embodiment of the present invention.

[Explanation of symbols]

 1 semiconductor chip 2 substrate 3 solder bump 4 core member 41 bottom part 42 pin part 421 pin part 422 pin part 423 pin part 424 pin part 425 hole 5 pad 6 pad 7 solder 8 organic insulating layer 9 ceramic substrate 10 solder 11 soldering 111 hole

Claims (16)

[Claims] 1. A connection of electronic parts, comprising: a solder bump connecting the first electronic part and the second electronic part; and a metal core member provided in the solder bump. Construction. 2. The connection structure for an electronic component according to claim 1, wherein the solder bump is formed in a zigzag shape. 3. The connection structure for an electronic component according to claim 1, wherein the first electronic component is a bare chip, and the second electronic component is a substrate. 4. The connection structure for an electronic component according to claim 3, wherein the core member is provided on the bare chip. 5. The electronic component connection structure according to claim 3, wherein the core member is provided on the substrate. 6. The electronic component connection structure according to claim 1, wherein the core member has a pin portion. 7. The connection structure for an electronic component according to claim 6, wherein the pin portion of the core member is sharp. 8. The connection structure for an electronic component according to claim 6, wherein the pin portion of the core member has an elliptical cross section. 9. The connecting structure for electronic parts according to claim 6, wherein a hole is provided inside the pin portion of the core member, and the hole communicates with a tip of the pin portion. 10. The connection structure for an electronic component according to claim 6, wherein the core member has a plurality of pin portions. 11. A first step of attaching a core member to a pad of a first electronic component, a second step of applying a predetermined amount of solder paste on a pad of the second electronic component, and inside the solder paste. And a fourth step of forming a solder bump by heating and melting the solder paste and then cooling the solder paste. 12. The amount of the solder paste applied is an amount that presents a zigzag shape due to surface tension when melted in the fourth step.
The connection structure of the described electronic components. 13. A first step of attaching a core member to a pad of a first electronic component, a second step of inserting annular solder into the core member, and a pad of the second electronic component in which the core member is a second pad. A third step of positioning the first electronic component on the second electronic component so as to be positioned above, and a fourth step of forming solder bumps by heating and melting the annular solder and then cooling it. And a step of connecting electronic components. 14. The amount of solder that constitutes the annular solder is an amount that takes on a zigzag shape due to surface tension when melted in the fourth step. Connection structure for electronic components. 15. A semiconductor device including a bare chip and a core member attached to a pad of the bare chip. 16. The semiconductor device according to claim 15, wherein the core member is attached with an amount of solder enough to form a solder bump having a slug shape when reflow soldering is performed.