JPH07249762A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device having an insulating film excellent in electric characteristics without causing any damage on the steep impurity distribution and iGe/Si heterojunction by depositing an oxide, containing a semiconductor substrate as once component, on the semiconductor substrate including an impurity layer having specified impurity distribution in an oxygen atmosphere containing steam. CONSTITUTION:A gate oxide 15 is deposited by 5nm through wet oxidation on an n-type Si layer 14 embedded with a B layer 13 at a depth of 50nm from the surface. More specifically, boron 13 is adsorbed selectively to the exposed part of Si on a P-type Si substrate 11 isolated by an oxide 12 using B2H6 gas. Subsequently, an Si layer 14 doped with boron by 5X10<16>/cm<3> is grown selectively by 50nm at the expose part of Si using silane and diborane. An SiO2 gate oxide 15 is then deposited by 5nm by wet oxidation. This method allows deposition of gate oxide of 5nm thick or less by highly reliable thermal oxidation without causing any damage on the impurity distribution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing an ultrafine field effect transistor using Si and SiGe / Si heterostructures having a steep doping profile as a substrate.

[0002]

2. Description of the Related Art In Si integrated circuits, high integration and low power consumption are progressing due to miniaturization. A metal-oxide film-semiconductor field effect transistor (MetalOxide Semiconductor Feild Efect Transistor) with a simple structure is required for high integration.
r; MOSFET) is suitable for low power consumption.
A complementary MOSFET in which an n-channel MOSFET and a p-channel MOSFET are mounted together is suitable.

Here, in a MOSFET having a gate length of deep submicron level, punch-through, etc., in which a current flows between the source and the drain except in the channel,
Suppression of the short channel effect is a major issue. Therefore, at present, a method of forming a punch-through stopper layer by ion-implanting an impurity of the same conductivity type as that of the substrate just below the channel is adopted. It is necessary to reduce the depth of the punch-through stopper layer as the element is miniaturized, but since the spread of the impurity distribution cannot be suppressed to 10 nm or less by the ion implantation method, the impurity concentration on the substrate surface becomes high, There is a problem that carrier mobility decreases.

Therefore, using the epitaxial growth method,
The technique of forming a lightly-doped layer on a heavily-doped substrate is described by IDM Technical Digest (1
993) p.909 (IEDM Technical Digest p.909 (1993))
Has been reported in.

[0005]

By using the method described above, it is possible to form a steep impurity distribution that cannot be realized by the ion implantation method, and as a result, it is possible to normally operate a MOSFET having a very small gate size. Becomes However, further miniaturization of the device results in thinning of the lightly doped layer. As a result, the thermal diffusion of impurities from the high-concentration layer, which causes the increase of the surface impurity concentration, cannot be ignored. Therefore, low concentration layer formation,
And, it became necessary to lower the temperature of the subsequent process.

As a typical technique for forming an insulating film at a low temperature without destroying the profile, there is a vapor phase growth method using plasma (plasma CVD method). However, this method has a drawback that the level density of the SiO ₂ / Si interface is higher than that of the thermal oxidation method, and the thermal oxidation method must be used in order to form a high quality gate oxide film.

However, as shown in FIG. 2, the diffusion of boron is faster in the heat treatment in the oxidizing atmosphere than in the non-oxidizing atmosphere, and in the wet oxidation than in the dry oxidation (the diffusion coefficient is 1). .5 times). Thus, even if an impurity layer having a steep profile is formed inside the Si substrate,
There is a problem that boron is largely diffused by the oxidation treatment.

[0008]

However, compared with the comparison of the SiO ₂ film thicknesses in the wet oxidation and dry oxidation shown in FIG. 3, the former has a higher oxidation rate than the latter, and an oxide film of the same thickness has a higher oxidation rate. It can be manufactured in a shorter time. From this, for example, when the film thickness is 5 nm,
Five times the time is enough. Therefore, diffusion distance [√ (diffusion coefficient ×
Oxidation time)] is shorter in wet oxidation.

As shown in FIG. 1, a thickness of 5 is formed on an n-type Si layer 14 in which a B layer 13 is embedded at a position 50 nm from the surface.
When the gate oxide film 15 of nm is formed by wet oxidation,
The surface concentration can be 5 × 10 ¹⁶ / cm ³ or less.

On the other hand, the low temperature insulating layer can be formed by, but by plasma or thermal CVD method has SiO ₂ / Si interface problem state density is high, it is SiO ₂ deposited immediately prior to silane (SiH ₄₎ Fluorine (F ₂ The problem can be solved by etching Si with a mixed gas of) and terminating the interface with fluorine and hydrogen.

[0011]

As a result, the gate oxide film or the nitride film of 5 nm or less required for the ultra-fine MOSFET can be formed by a highly reliable thermal oxidation method without impairing the steep impurity distribution. Insulating films (oxide film and nitride film) at low temperature
Also in the CVD method capable of forming Si, by etching Si immediately before deposition of SiO ₂ , Si having a low interface state density can be obtained.
An O ₂ / Si interface can be created.

[0012]

【Example】

Example 1 A layer having an initial impurity distribution of 10 nm or less (δ
N-type MOSF using the doped layer as a punch-through stopper
An example of producing an ET will be described (Fig. 1).

A p-type Si substrate 11 separated by an oxide film 12
Then, boron 13 was selectively adsorbed only on the exposed Si portion by using B ₂ H ₆ gas (a). Next, silane and diborane (B ₂
A Si layer 14 doped with boron at 5 × 10 ¹⁶ / cm ³ was selectively grown to a thickness of 50 nm on the exposed Si portion by H ₆ ) (b). Next, a 5 nm thick SiO ₂ gate oxide film 15 was formed by wet oxidation at 800 ° C. for 5 minutes (c).

FIG. 4 shows the depth profile of boron after the gate oxide is formed. The figure also shows the results of dry oxidation at the same oxide thickness of 800 ° C. for 25 minutes. From the figure, it was found that the diffusion of boron was suppressed in the wet oxidation. At this time, the surface boron concentration is 5 × 10 ¹⁶ /
It was below cm ³ . As shown in FIG. 2 and FIG. 3, the wet oxidation is faster in both diffusion rate and oxidation rate, but the oxidation rate is 5 under the condition of forming SiO ₂ with a film thickness of 5 nm at 800 ° C.
It is considered that the diffusion distance [√ (diffusion coefficient × oxidation time)] was shortened.

Next, heavily doped n-type polycrystalline Si was deposited on the oxide film to process the gate electrode 16. Further, a sidewall nitride film 17 was formed (d). Finally, As or P
Source 1 by ion implantation or thermal diffusion
8 and the drain 19 were formed (e).

As a result, the surface impurity concentration when the gate oxide film was formed by wet oxidation was lower than that of dry oxidation, and the carrier mobility was 1.5 times higher than that of dry oxidation. It should be noted that it is difficult to make the oxide film thickness uniform due to the high oxidation rate in wet oxidation. Therefore, in order to make the wafer temperature uniform, heat treatment is performed in nitrogen at the same temperature and time as in oxidation, and then oxidation is performed, but since there is no accelerated diffusion in a nitrogen atmosphere, there is little influence on the change in profile.

(Embodiment 2) According to FIG. 5, antimony (S
b) An example in which an n-type MOSFET having a δ-doped layer as a channel is manufactured will be described.

A p-type Si substrate 11 separated by an oxide film 12
Then, using the molecular beam epitaxy method, antimony (S
b) 21 was selectively adsorbed only on the 1 × 10 ¹³ / cm ² Si exposed portion 11 to form the δ-doped layer 21 (a). A non-doped Si layer 22 is formed thereon at a substrate temperature of 150 ° C. for 30 n.
m epitaxially grown (b). By such low temperature growth, surface segregation of Sb can be suppressed. Next, the Si layer 22 on the element isolation oxide film 12 was removed (c). Thickness 4 nm
The gate oxide film 23 is made of 100% SiH ₄ and 100% O.
_It was deposited at a substrate temperature of 400 ° C. by utilizing an oxidation reaction with ₂ (d). Next, by performing heat treatment at 900 ° C. for 10 seconds in a dry oxygen atmosphere, the crystallinity of the Si epitaxial growth layer 22 and the breakdown voltage of the gate oxide film 22 could be improved. Further, the diffusion of Sb in the δ-doped layer 21 was suppressed. The gate electrode 24 was processed on the oxide film 23 to form the sidewall nitride film 25 (e). Finally, a source and a drain were formed by ion implantation or thermal diffusion of As or P (f).

As a result, when the gate length is 0.1 μm, the mutual conductance is 800 mS / mm, which is the MO of the conventional structure.
Higher transconductance was obtained compared to SFET.

Example 3 According to FIG. 6, Si / Si _0.7 G
An example of manufacturing a p-channel MOSFET having an e _0.3 / Si heterostructure will be described.

An ultra high vacuum chemical vapor deposition method (UHV-CVD method) was used for the preparation of the sample. First, phosphorus is deposited on the n-type Si (100) substrate 31 separated by the oxide film 12.
× 10 ¹⁶ / cm ³ doped n-type Si _0.7 Ge _0.3 layer 32 and n-type Si layer 33 were both applied at a substrate temperature of 550 ° C.
nm selective epitaxial growth (a). The gate oxide film 34 was produced by the low pressure CVD apparatus as follows (b).

First, 10 sccm of 100% SiH ₄ and 10 sccm of 5% F ₂ diluted with N ₂ were reacted at a pressure of 0.1 Torr.
If the substrate temperature is set to 400 ° C. under this condition, Si can be etched at 0.1 nm / sec as shown in FIG. Under this condition, 1.0 nm Si is etched and F ₂ gas is stopped.
Subsequently, 10 sccm of 100% O _{2 was} introduced into the reaction chamber, and SiO ₂ was added.
Deposit.

As described above, the etching of Si is changed to SiO ₂
It was possible to remove the SiO ₂ / Si ₂ interface impurities and terminate the interface dangling bond with fluorine by continuously shifting to the deposition of 1 to reduce the interface state density.

When a nitride film is formed, Si is used.
It was produced by mixing H ₄ , F ₂ and ammonia gas NH ₃ . A gate electrode 35 and a sidewall nitride film 36 were formed (c). Source 37, drain 38 boron 5 ×
It was formed by ion implantation at 10 ¹⁴ / cm ³ and 25 keV and heat treatment at 750 ° C. for 30 minutes in a nitrogen atmosphere (d).

The p-channel MOSFET is 300K,
The hole mobility was 200 cm ² / v · s, and higher carrier mobility was obtained compared to the Sip channel MOSFET under the same conditions.

[0026]

According to the present invention, a steep impurity distribution and S
An ultrafine field effect transistor having an insulating film with excellent electrical characteristics can be manufactured without damaging the iGe / Si hetero interface.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a characteristic diagram of heat treatment temperature dependence of a diffusion coefficient of B.

FIG. 3 is a characteristic diagram showing the relationship between the oxidation time and the oxide film thickness of dry oxidation and wet oxidation at 800 ° C.

FIG. 4 is a distribution characteristic diagram of B in the depth direction.

FIG. 5 is an explanatory diagram of a manufacturing process of an n-channel δ-doped MOSFET.

FIG. 6 is an explanatory diagram of a manufacturing process of a p-channel Si / Si _0.7 Ge _0.3 / Si heterojunction MOSFET.

FIG. 7 is a characteristic diagram showing the relationship between the deposition rate of Si and the substrate temperature in a mixed gas system of SiH ₄ and F ₂ .

[Explanation of symbols]

11 ... P-type Si substrate, 12 ... Element isolation oxide film, 13 ... Boron atom, 14 ... P-type Si layer, 15 ... Gate oxide film, 1
6 ... Gate electrode, 17 ... Side wall nitride film, 18 ... Source, 1
9 ... Drain.

Claims (2)

[Claims] 1. An apparatus for inducing electrons or holes at an interface between the semiconductor substrate and the gate insulating film by changing a voltage of a gate electrode in contact with a gate insulating film formed on the semiconductor substrate, thereby performing switching. In the manufacturing method of 1., a step of forming an oxide film having the semiconductor substrate as one of its components in an oxygen atmosphere containing water vapor is formed on the semiconductor substrate having an impurity layer whose impurity distribution spread is 50 nm or less. A method of manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein S is formed on the semiconductor substrate and the Si / SiGe / Si thin film containing a SiGe mixed crystal.
A method of manufacturing a semiconductor device, comprising a step of continuously performing etching of i and deposition of an oxide film or a nitride film having the semiconductor substrate as one of its components at the same substrate temperature.