JPH0727490B2 - Cache memory - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory in a cache memory that stores instruction block data responding to an instruction fetch and operand block data responding to an operand fetch.

[Conventional technology]

Conventionally, the cache memory adopts a set associative method, etc., registers block data in the cache memory with a certain fixed block size, and further adopts a separated cache memory configuration consisting of an operand cache memory and an instruction cache memory. Or, a common cache memory configuration was used that stores both operands and instructions. Generally, in a program, the instruction word has continuity in the storage area, but the operand data is
It is known that there is often a tendency to have uneven distribution or discontinuity.

In the former separated cache memory configuration, the block size of the operand block data in the operand cache memory is generally a block size that is well balanced in performance for accesses by continuous addresses and jump addresses. The block size of the instruction block data in the cache memory is a block size that is good in terms of performance for access by consecutive addresses, and the block size in each cache memory is often different. In the cache memory configuration, the block size of the operand block data and the block size of the instruction block data are the same.

[Problems to be Solved by the Invention]

However, in the above-mentioned conventional cache memory configuration, if the former separated cache memory configuration is adopted, it is necessary to configure two operand cache memories and two instruction cache memories independently, which requires twice the hardware amount. In the latter shared cache memory configuration, the block size is the same for both operands and instructions, the characteristics of each block data cannot be utilized, and an instruction buffer is provided above the cache memory. When the lower cache memory has a separated cache memory configuration, the block size that makes use of each characteristic can be selected, but with the shared cache memory configuration, the block size of the instruction buffer is the same as the block size on the cache memory. And each characteristic There is a disadvantage that can not dregs that.

In view of the above-mentioned drawbacks, the technical problem of the present invention is to eliminate the need for doubling the amount of hardware as in the case of the separate cache memory configuration and to make each block size the same as in the shared cache memory configuration. , It is to provide an information processing device capable of setting an optimum block size.

[Means for Solving the Problems]

According to the present invention, there is provided a set associative cache memory which is connected between a data processing device and a main memory device and which stores a part of a large number of operand block data and instruction block data stored in the main memory device. , Having a plurality of storage areas having a storage capacity equal to the block size of the operand block data,
Buffer means in which the plurality of storage areas are divided into groups of 2n so as to correspond to the block size of the instruction block data, and the storage means respectively correspond to the plurality of storage areas,
Valid information storage means for storing valid / invalid information of data stored in each storage area, and data stored in the storage area belonging to each set, which corresponds to each set, is the operand block data. Block information storage means for storing block information indicating whether the instruction block data is the operand block data or the instruction block data output from the data processing device. When the operand block data is to be read based on the request block information indicating whether the data is data,
When reading from the buffer means and registration in the buffer means are performed in units of the storage area, and the instruction block data is to be read, the reading from the buffer means and the registration in the buffer means are performed in the group. A cache memory is obtained which is characterized in that it can be performed in units.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

In the description, the configuration shown in FIG. 3 will be taken as an example.

First, the operations of normal operand fetch and instruction fetch will be described.

An operand fetch is issued from the data processing device 1 to the cache memory 3 (shared cache memory) via the operand fetch request line 101, and if there is operand block data including the corresponding data in the cache memory 3, the operand fetch The corresponding data is returned to the data processing device 1 via the data line 302. On the contrary, when there is no operand block data including the corresponding data, an operand block load request is issued to the main memory device 4 via the main memory access line 303 and read from the main memory device 4. The corresponding block data that has been issued is registered in the cache memory 3 via the data line 401.

Next, regarding instruction fetch, in the instruction fetch, first, an instruction fetch request from the data processing device 1 is sent to the instruction buffer 2 via the instruction fetch request line 102.
The instruction buffer 2 which has received the instruction fetch request receives the instruction data line 20 if the corresponding instruction block data exists.
An instruction word is fetched to the data processing device 1 via 1. If the relevant instruction block data does not exist in the instruction buffer 2, an instruction block data fetch request is issued from the instruction buffer 2 to the cache memory 3 via the instruction block fetch request line 202.

If the instruction block data corresponding to the instruction block fetch request exists in the cache memory 3, the instruction block data is returned and registered in the instruction buffer 2 via the instruction block data line 301. If the corresponding instruction block data does not exist in the cache memory 3 either, an instruction block load request is issued from the cache memory 3 to the main memory device 4 via the main memory access line 303, The relevant instruction block data read from the device 4 is registered in the cache memory 3 via the data line 401, and the instruction block data is also transferred to and registered in the instruction buffer 2.

In the present invention, the above-mentioned operand block data and instruction block data have different block sizes, which are registered and managed in the same cache memory 3, and the point will be described subsequently.

As an example, the block size of instruction block data is 4N bytes and the block size of operand block data is N.
We will use the case of byte.

As shown in FIG. 1, the cache memory 3 has a data buffer.
31, an address tag storage unit 32, a valid information storage unit 33, and a block information storage unit 34 are provided.

The data buffer 31 is composed of an N-byte data block (operand block data) as a basic block,
The address tag storage unit 32 has an upper address part in a one-to-one correspondence with the basic blocks, and the valid information storage unit 33 has one valid bit for each basic block, which is the block size of the instruction block data. folding each (2 ^double operand block data), they 1
The block information storage unit 34 stores information such that it can be read and written each time, and the block information storage unit 34 has 1-bit information in the instruction block data unit and distinguishes between the instruction block data and the operand block data. Can be read and written in the same manner as the valid bit described above.

By having such information, for example, when there is an operand access (a) in the storage area D ₁ of the data buffer 31 as shown in FIG. 2, the valid bit corresponding to the operand access (a) is set to the valid information storage section. From 33,
The block information is read from the block information storage unit 34, the upper address portion is read from the address tag storage unit 32, and is read from the access address upper portion and the address tag storage unit 32 by the address compare circuit 35 as shown in FIG. The address upper part is compared, a match is found in the compare circuit 35, the valid information read from the valid information memory 33 is “1” (valid), AND is taken by the AND gate 37, and further block information is obtained. The block information read from the storage unit 34 is "0", which indicates that the block information is operand block data.
(“Operand access” = “0”) and compare circuit 38
When the AND gate 39 performs the AND operation, it means that there is block data including the corresponding data. Conversely, the valid bit is “0” or the block information is “(instruction block) =“ If it is 1 "), it means that there is no block data including the corresponding data.

Similarly, as shown in FIG. 2, the data buffer
When there is an instruction access (b) in the memory area D _{5 of} 31, as described above, when the valid bit is “1” and the block information is “1”, the corresponding instruction block data exists, Valid bit is "0" or block information is "0"
If so, it means that the corresponding instruction block data does not exist.

In the case shown in FIG. 2, in the state shown in, there is an instruction access (b) in the entry in the cache memory 3 in which the operand block data exists, and as described above, the block information in the compare circuit 38 matches. Therefore, the instruction block data on the cache memory 3 is absent, and the instruction block data (4 N bytes) read from the main storage device 4 includes the instruction block size boundary (including the storage area D ₁ where the instruction access (b) was made ( Storage area D ₁ , D ₂ ,
D _3, and registers the information to the set) consisting of D _4, and 1 valid information with 4 bits, and "1" from "0" to the block information.

In the case shown in FIG. 2, in the state shown in, there is an operand access to the entry in the cache memory 3 where the instruction block data exists. As described above, the operand block data does not exist in the cache memory and the main memory device The operand block data (N bytes) read from 4 is registered in the storage area D ₅ where the operand was accessed, and the valid information is set to 1 in the bit corresponding to the registered block data, and the valid information of the other 3 blocks is set to 3 Set bit “0” (invalidation) and block information from “1” to “0”.

By doing so, it becomes possible to process block data of different sizes independently on the same cache memory 3.

〔The invention's effect〕

As described above, according to the present invention, the block data of two kinds of block sizes can be registered in the cache memory, so that the hardware amount is not required twice as in the separated cache memory configuration, and the shared cache memory configuration is provided. By making it possible to set the optimum block size for each without having to make the block sizes the same, it is possible to provide a cache memory with excellent performance.

[Brief description of drawings]

FIG. 1 is an embodiment of the present invention, FIGS. 2 to are concrete examples showing the mode of the block sizes of the two types of block data in FIG. 1, and FIG. 3 is an example of the configuration of this embodiment. is there. 1 ... Data processing device, 2 ... Instruction buffer, 3 ... Cache memory, 4 ... Main memory device, 11 ... Address register,
12 …… Block information, 31 …… Data buffer, 32 …… Address tag storage, 33 …… Valid information storage, 34 …… Block information storage, 35,38 …… Compare circuit, 37,39 …… AND Gate, 36 …… Selector, 101 …… Operand fetch request line,
102 …… Instruction fetch request line, 201 …… Instruction data line, 202
…… Instruction block fetch request line, 301 …… Instruction block data line, 302 …… Operand data line, 303 …… Main memory access line, 401 …… Data line.

Claims (1)

[Claims] 1. A set associative cache memory, which is connected between a data processing device and a main memory device and stores a part of a large number of operand block data and instruction block data stored in the main memory device, Buffer means having a plurality of storage areas each having a storage capacity equal to the block size of the operand block data, and the plurality of storage areas being divided into 2n groups so as to correspond to the block size of the instruction block data; Corresponding to the plurality of storage areas, respectively corresponding to the valid information storage means for storing valid / invalid information of the data stored in each storage area, respectively,
A block information storage unit that stores block information indicating whether the data stored in the storage area belonging to each set is the operand block data or the instruction block data, and is output from the data processing device. When the operand block data is to be read out based on request block information indicating whether the data to be read is the operand block data or the instruction block data, the buffer means is used. When the instruction block data is to be read out and registered in the buffer means in units of the storage area, the reading out from the buffer means and the registration in the buffer means can be performed in the group unit. A cache memory characterized in that