JPH0727556B2 - Bus access method - Google Patents

Description

DETAILED DESCRIPTION [Overview] When a processor on the option board writes and displays data in a screen memory on the main body side, the bus access method that can improve the display speed is described. To improve the screen memory, the system processor that accesses the screen memory, the option board that has the processor and operates with its own software, the system bus that connects these, and the system bus from the option board. In a device equipped with a bus arbitration circuit that grants permission to use the system bus in response to a request for use, the option board sequentially reads the same local screen memory as the screen memory and the address for accessing the screen memory, and then reads the address on the system bus. Data to be written to the screen memory while being sent out A FIFO buffer memory for reading and sending to the system bus is provided, and when the processor writes data to the screen memory, the data is written to the local screen memory and the FIFO
By writing the address and data of the screen memory to the buffer memory, the FIFO buffer memory is made to write the data to the screen memory each time the bus arbitration circuit gives the right to use the system bus, and the data is read from the screen memory. When outputting, the data is read from the local screen memory.

[Industrial application field]

The present invention relates to a computer which is mounted with a processor and operates by attaching an option board which operates by its own software. In particular, the processor on the option board side stores data in a screen memory for storing display data provided in the computer. The present invention relates to a bus access method capable of improving the display speed when writing and displaying.

In workstations, personal computers, etc., a system processor, a main memory, a screen memory, etc. are connected via a system bus, and the data written in this screen memory is displayed on the display unit, and a processor is installed to make it unique. There is a configuration in which an option board operated by software is connected to the system bus and jobs can be performed by different software.

The processor of the option board connected to the system bus of the workstation or personal computer configured in this way writes data to the screen memory provided on the main body side via this system bus, and on the display unit of the main body side, The data written in this screen memory is displayed, but this display speed must be fast.

[Conventional technology]

 FIG. 2 is a block diagram illustrating an example of a conventional technique.

The system processor 10 on the main body side accesses the main memory 11 or the screen memory 12 via the system bus 9 to execute the job. Then, the data written in the screen memory 12 is read by the display control circuit 13 and displayed on the display unit 14.

The option board 1 is optionally connected to the system bus 9. When the processor 2 of the option board 1 needs to access the screen memory 12, the processor 2 of the option board 1 sends the address of the screen memory 12 to the bus 7. When writing data, the write data is sent to the bus 7 at the same time. .

When the decoder 3 decodes the address of the screen memory 12, it activates the bus request circuit 4. Therefore, the bus request circuit 4 asks the bus arbitration circuit 8 for permission to use the system bus 9 in order to acquire the right to use the system bus 9.

Bus arbitration circuit 8 requested to use the system bus 9
Acquires the right to use the system bus 9 of the option board 1 by a known system bus acquisition procedure,
A signal for permitting use of the system bus 9 is sent to the bus request circuit 4.

The bus request circuit 4 which has received the use permission signal of the system bus 9 permits the address conversion circuit 5 to transmit the address. Therefore, the address conversion circuit 5 uses the address of the screen memory 12 transmitted by the processor 2 on the main body side. It is converted to an address to be transmitted and sent to the system bus 9.

Further, since the bus request circuit 4 opens the gate of the gate circuit 6, the gate circuit 6 sends the data sent by the processor 2 to the bus 7 to the system bus 9 for writing, and the gate circuit 6 sends the address for reading. The data read from the screen memory 12 to the system bus 9 is transferred to the processor 2 according to the address sent by the conversion circuit 5.

Therefore, at the time of writing, the data sent from the gate circuit 6 is written in the screen memory 12 by the address sent by the address conversion circuit 5, and in the case of reading, the data sent by the address conversion circuit 5 is written from the screen memory 12 by the address sent by the address conversion circuit 5. The read data is transferred to the processor 2 via the gate circuit 6.

The data written by the processor 2 in the screen memory 12 is
Similar to the above, it is displayed on the display unit 14.

[Problems to be Solved by the Invention]

As described above, the processor 2 of the option board 1 is conventionally used.
When the user accesses the screen memory 12, the screen memory 12 can be accessed only after the usage right of the system bus 9 is acquired by the arbitration of the bus arbitration circuit 8 each time the address of the screen memory 12 is transmitted. Absent.

Therefore, the access efficiency of the processor 2 to the screen memory 12 depends on the performance of the system bus 9 because it depends on how fast the processor 2 can acquire the right to use the system bus 9 after the address of the screen memory 12 is transmitted. Therefore, there is a problem that the screen display speed becomes slow.

In particular, scrolling of a graphic image is frequently used because the processor 2 continuously transfers data in a certain area of the screen memory 12 to another area of the screen memory 12. Therefore, there is a problem that the operating performance of the system bus 9 directly affects the screen display speed.

In view of these problems, the present invention aims to reduce the influence of the operating performance of the system bus 9 and improve the screen display speed.

[Means for Solving the Problems]

As shown in FIG. 1, the purpose is to store a screen memory 12 for storing at least data to be displayed on the display unit 14,
System processor 10 for accessing the screen memory 12
An option board 15 equipped with the processor 2 and operated by its own software; a system bus 9 connecting the screen memory 12, the system processor 10 and the option board 15; and a system bus used from the option board 15. In a device provided with a bus arbitration circuit 8 which acquires a use right of the system bus 9 and gives a use permission in response to a request, the option board 15 has the same screen memory 12 (that is, the same memory capacity and the same number of planes). ) Local screen memory 17 and addresses for accessing the screen memory 12 are sequentially read out in the stored order and sent to the system bus 9, and data to be written in the screen memory 12 are read out in the stored order. FIFO to be sent to the system bus 9
A buffer memory 16 is provided, and the processor 2 of the option board 15 is provided with the screen memory.
When writing data to 12, the local screen memory 17 is sequentially written with the data and the FIFO buffer memory 16
On the other hand, by sequentially writing the address and the data to be sent to the screen memory 12, the FIFO buffer memory 16 is read from the FIFO buffer memory 16 each time the bus arbitration circuit 8 gives the system bus use right. The data read from the FIFO buffer memory 16 is written to the screen memory 12 via the system bus 9 based on the address
When the processor 2 reads the data from the screen memory 12, it is achieved by reading the data from the local screen memory 17 instead of accessing the screen memory 12.

[Action]

With the above configuration, when reading data from the screen memory 12, the local screen memory 17 in which the same data as the screen memory 12 is stored is used.
Since 12 is not accessed, it is not necessary to acquire the right to use the system bus 9, so the operating performance of the system bus 9 is not affected.

When writing data to the screen memory 12, the processor 2
Writes the address and data to the FIFO buffer memory 16,
After that, to make the FIFO buffer memory 16 write data to the screen memory 12, the FIFO buffer memory 16
While acquiring the right to use the system bus 9 and writing data, the processor 2 can execute other processing.

Therefore, when the processor 2 continuously transfers the data in one area of the screen memory 12 to another area of the screen memory 12, like the scrolling of the graphic image, the FIFO buffer memory 16 stores the data for the screen memory 12. The processor 2 can read data from the local screen memory 17 during writing, and the system buffer 9 is acquired by the FIFO buffer memory 16 while the processor 2 is reading the next data. When the data writing is completed, the influence of the operating performance of the system bus 9 disappears, but in reality, the operating performance of the system bus 9 is slow, so that the operating performance of the system bus 9 is affected.

However, at least the read cycle is completely unaffected by the operating performance of the system bus 9, so that it is possible to obtain a performance improvement of about twice that of the conventional one.

〔Example〕

FIG. 1 is a block diagram of a circuit showing the principle and one embodiment of the present invention.

The same reference numerals as those in FIG. 2 indicate the same functions. The option board 15 is optionally connected to the system bus 9. When the processor 2 of the option board 15 writes the data to the screen memory 12, the local screen memory
The write signal is sent to 17, the address of the screen memory 12 is sent to the bus 7, and the write data is sent to the bus 7.

When the decoder 18 decodes the address of the screen memory 12, it outputs a storage signal to the FIFO buffer memory 16. Therefore, the FIFO buffer memory 16 stores an address obtained by converting the address of the screen memory 12 sent by the processor 2 into an address used by the address conversion circuit 5 on the main body side, and also stores the data sent to the bus 7.

The FIFO buffer memory 16 has, for example, a two-stage configuration, and when addresses and data are stored in one or more stages, the bus request circuit 4
To start. Therefore, the bus request circuit 4 is connected to the system bus 9
To obtain the right to use the system bus 9, the bus arbitration circuit 8 is requested to use the system bus 9.

Bus arbitration circuit 8 requested to use the system bus 9
Acquires the right to use the option board 15 for the system bus 9 by a known system bus acquisition procedure,
A signal for permitting use of the system bus 9 is sent to the bus request circuit 4.

The bus request circuit 4 which has received the use permission signal of the system bus 9 permits the FIFO buffer memory 16 to send out the address and the data. Therefore, the FIFO buffer memory 16 stores the address and the data stored in the first stage in the system bus 9. The data is transmitted, and the address and data stored in the second row are moved to the first row.

Therefore, when the processor 2 writes, data is written in the local screen memory 17 at the address sent by the processor 2, and data is written in the screen memory 12 at the address sent by the FIFO buffer memory 16 to the system bus 9. Is written.

When the FIFO buffer memory 16 finishes storing the data sent by the processor 2, it notifies the processor 2 of the completion of writing the data, and the local screen memory 17 informs the processor 2 when it finishes storing the data sent by the processor 2. Notify that data writing is complete. Therefore, when the processor 2 receives the write completion notification of both, it sends the next address and data, but the decoder 18 uses the FIFO buffer memory.
When the data of 16 stages is still stored in two stages, the processor 2 waits for the FIFO buffer memory 16 to have a space in order to instruct the processor 2 to hold the next address and data.

When the processor 2 reads data, the decoder 18
And a read signal is sent to the local screen memory 17, an address is sent to the local screen memory 17, and necessary data is read. At this time, since the decoder 18 is a read signal, it does not send the stored signal to the FIFO buffer memory 16.

In this embodiment, the screen memory 12 is described as one plane, but the same applies when a plurality of planes are used.

〔The invention's effect〕

As described above, according to the present invention, when a processor is mounted on an option board such as a workstation or a personal computer to operate software separate from the main body side and the main body side screen memory is directly used, It is possible to perform high-speed display that is less affected by the operating performance of the bus.

[Brief description of drawings]

FIG. 1 is a block diagram of a circuit showing the principle and one embodiment of the present invention, and FIG. 2 is a block diagram explaining an example of a conventional technique. In the figure, 1 and 15 are option boards, 2 are processors, 3 and 18 are decoders, 4 is a bus request circuit, 5 is an address conversion circuit, 6 is a gate circuit, 7 is a bus, 8 is a bus arbitration circuit, and 9 is a system. Bus, 10 system processor, 11 main memory, 12 screen memory, 13 display control circuit, 14 display unit, 16 FIFO
A buffer memory, and 17 is a local screen memory.

Claims (1)

[Claims] 1. A screen memory for storing at least data to be displayed on a display unit, a system processor for accessing the screen memory, an option board equipped with the processor and operated by its own software, the screen memory and the system processor. And an option board, and a bus arbitration circuit which acquires a use right of the system bus and gives a use permission in response to a request for use of the system bus from the option board. A local screen memory that is the same as the screen memory on the board, and addresses for accessing the screen memory are sequentially read in the order in which they are stored and sent to the system bus, and data to be written in the screen memory is stored in the order in which they were stored. FIFO buffer memory that sequentially reads and sends to the system bus When the processor of the option board writes data to the screen memory, the data is sequentially written to the local screen memory, and the address and data to be sent to the screen memory are sent to the FIFO buffer memory. By sequentially writing and, the data read from the FIFO buffer memory is written based on the address read from the FIFO buffer memory every time the system bus use right is given to the FIFO buffer memory from the bus arbitration circuit. A bus characterized in that when writing to the screen memory via the system bus and the processor reads data from the screen memory, the data is read from the local screen memory instead of accessing the screen memory. Access method.