JPH0727925B2 - Electronic equipment - Google Patents

Description

The present invention relates to an electronic device device, and more particularly to an electronic device device in which an LSI chip is flip-chip mounted on a substrate.

[Conventional technology]

As a technique for flip-chip mounting an LSI chip on a mounting substrate formed by processing a conventional silicon wafer,
HJLevinstein, etc.
et al) is the ISSC Digest (ISSC)
C Digest), 1987, pp. 224-225, Multi-Chip Packaging Technology for VRS based system (Multic-Chip Packa
ging Technology for VLSI-Based System).

[Problems to be Solved by the Invention]

The above-described conventional technique of flip-chip mounting an LSI chip on a mounting substrate formed by processing a silicon wafer has the following problems.

(1) Since the size of the silicon wafer is limited, the system does not always fit on one board when mounting a large-scale system. In that case, wire bonding etc. is performed from the edge of the mounting board. Since the output terminals must be pulled out, the mounting density cannot be improved.

(2) Since the input / output terminals must be arranged at the end of the mounting board, it is necessary to lay the wiring up to that point.
Inevitably, the wiring length becomes long, and the extension time of the signal becomes long accordingly.

[Means for Solving the Problems]

The electronic device of the present invention is a through-hole provided in a silicon wafer, an insulating film provided on the surface of the silicon wafer including an inner wall of the through-hole, and the insulating film formed by being embedded in the through-hole. By the embedded wiring insulated from the silicon wafer by, the mounting wiring connected to the upper surface of the embedded wiring and extending on the insulating film, the interlayer insulating film formed on the surface including the mounting wiring, A mounting board provided with an embedded via layer formed to be embedded in an opening formed in an interlayer insulating film and connected to the mounting wiring, and an electrode connected to an upper surface of the embedded via layer; A multilayer wiring board electrically connected to the exposed lower surface of the embedded wiring via a solder ball, and flip-chip bonded to the electrode exposed on the upper surface of the mounting board for mounting.
It is configured to include an LSI chip.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1 (a) to 1 (h) are cross-sectional views showing the order of steps for explaining a manufacturing method according to an embodiment of the present invention.

First, as shown in FIG. 1A, a first host resist layer 2 is formed on a silicon wafer 1 having a (110) plane as a main surface.
Is formed, and the first photoresist layer 2 is used as a mask to immerse in a liquid such as hydrazine or KOH to perform etching to form a buried groove 3. Since the etching proceeds in the direction of the (110) plane in these liquids, anisotropic etching becomes possible. The size of the embedding groove 3 of this embodiment is 300 μm in diameter.
m and the depth is 300 μm.

Next, as shown in FIG. 1 (b), after peeling off the first host resist layer 2, the silicon wafer 1 is heated at 1200 ° C. for 10
Thermal oxidation is performed for a time to form a thermal oxide film 4 of about 3 μm. Next, titanium and copper are continuously sputtered to form the first barrier metal layer 5. Next, the second photoresist layer 6 is formed, and nickel is electroplated using the second photoresist layer 6 as a mask to form the embedded wiring 7 in the portion of the embedded groove 3. Here, an aqueous solution of NiSO ₄ : NiCl ₂ : H ₃ BO ₃ = 10: 1: 1 was used as the nickel plating solution. The embedded wiring 7 can also be formed by baking after dropping the silver paste.

Next, as shown in FIG. 1C, after peeling off the second photoresist layer 6, the first barrier metal layer 5 is partially etched by immersing it in dilute sulfuric acid and hydrogen fluoride aqueous solution. next,
Titanium and copper are continuously sputtered to form the second barrier metal layer 8. Next, the third photoresist layer 9 is formed, and the first mounting wiring 10 is formed by electroplating copper in a copper sulfate aqueous solution using the third photoresist layer 9 as a mask.

Next, as shown in FIG. 1 (d), after peeling off the third photoresist layer 9, the second barrier metal layer 8 is partly etched by dipping it in dilute sulfuric acid and hydrogen fluoride aqueous solution, and then exposed. A first interlayer insulating film 11 is formed by applying a photosensitive polyimide and exposing and developing it. Negative type for photosensitive polyimide,
There are both types of positive type, but it is possible to use either type. Alternatively, a non-photosensitive polyimide may be used to form a photoresist pattern on it, and the pattern may be formed by etching in hydrazine or the like. Next, electroless plating is performed in a nickel plating solution using the first interlayer insulating film 11 as a mask to form a first buried via layer 12.

Next, as shown in FIG. 1E, titanium and copper are continuously sputtered to form a third barrier metal layer 13. Next is the fourth
The photoresist layer 14 is formed, and the second mounting wiring 15 is formed by electroplating in an aqueous solution of copper sulfate using the photoresist layer 14 as a mask.

Next, as shown in FIG. 1 (f), after the fourth photoresist layer 14 is peeled off and removed, a part of the third barrier metal layer 13 is etched in dilute sulfuric acid and hydrogen fluoride aqueous solution. Next, a second interlayer insulating film 16 is formed by applying photosensitive polyimide and exposing and developing it. Next, electroless plating of nickel is performed using the second interlayer insulating film 16 as a mask,
A second buried via layer 17 is formed. Next, titanium, copper,
Gold is continuously sputtered to form the electrode metal layer 18. Next, a fifth photoresist layer 19 is formed.

Next, as shown in FIG. 1 (g), the fifth photoresist layer 19 is used as a mask and immersed in an aqueous solution of iodine / ammonium iodide, dilute sulfuric acid and hydrogen fluoride to form an electrode metal layer.
Etch a portion of 18. Next, the 5th Hotrezito layer
After peeling off 19, the back surface of the silicon wafer 1 is ground with a scrubber, etc.
So that it is exposed from the back side of. The mounting board 20 is completed through the above steps.

Next, as shown in FIG. 1 (h), a low thermal expansion glass having a ground layer, a power source layer, and a signal line layer embedded therein, AlN,
Solder balls 22 are formed on a multilayer ceramic substrate 21 made of a material such as alumina, and the solder balls 22 are connected to the mounting substrate 20.
At this time, the embedded wiring 7 in the mounting substrate 20 and the solder balls 22 on the multilayer ceramic substrate 21 are connected. Further, a printed circuit board made of glass epoxy or polyimide can be used instead of the multilayer ceramic substrate 21. next,
By connecting the solder bumps 24 formed on the LSI chip 23 by the plating method and the electrodes 18 on the mounting substrate 20, the LS
The I chip 23 is flip-chip mounted on the mounting substrate 20.

2 (a) to 2 (c) are sectional views showing the order of steps for explaining the manufacturing method according to the second embodiment of the present invention.

First, as shown in FIG. 2 (a), a silicon wafer 1
Irradiating infrared laser to the through hole with a diameter of about 200 μm 3
Open 3

Next, as shown in FIG. 2B, the thermal oxide film 4 and the first barrier metal layer 5 are provided by using the same method as in the first embodiment, and the photoresist layer 6 is used as a mask to remove the gold. Electroplating is performed to fill the through holes 33 and form the embedded wiring 7a.

Next, as shown in FIG. 2C, the second barrier metal layer 8 and the first mounting wiring are formed by using the same method as in the first embodiment.
10, first interlayer insulating film 11, first buried via layer 12, third barrier metal layer 13, second mounting wiring 15, second interlayer insulating film 16, second buried via layer 17, electrode A metal layer 18 is provided. The subsequent steps are performed in the same manner as in the first embodiment. In this way, the electronic device shown in FIG. 1 (h) is obtained.

〔The invention's effect〕

As described above, the present invention forms the embedded wiring penetrating the front and back surfaces in the mounting substrate formed by processing the silicon wafer and uses it as the wiring. Therefore, there are the following effects.

(1) Mounting density is improved.

In the prior art, it was necessary to take the input / output terminal on the side surface of the mounting board, but in the present invention, the mounting density is improved because the input / output terminal can be formed on the back surface side of the mounting board.

(2) The wiring length is shortened and the system can be speeded up.

In the prior art, the wiring is extended from the input / output terminal arranged at the end of the mounting board, which inevitably increases the wiring length. However, in the present invention, since the wiring can be perpendicular to the board, the wiring length is shortened and the system speed is increased. Is made.

[Brief description of drawings]

1 (a) to (h) and 2 (a) to (c) are cross-sectional views showing the order of steps for explaining the manufacturing method of the first and second embodiments of the present invention, respectively. . 1 ... Silicon wafer, 2 ... First photoresist layer, 3 ... Buried groove, 4 ... Thermal oxide film, 5 ... First barrier metal layer, 6 ... Second photoresist layer, 7, 7a ...... Buried wiring, 8 ...... Second barrier metal layer, 9 ...... Third photoresist layer, 10 ...... First mounting wiring, 11 ...... First interlayer insulating film, 12 ...... First Buried via layer, 13 ... third barrier metal layer, 14 ... fourth photoresist layer, 15 ... second
Mounting wiring, 16 ... second interlayer insulating film, 17 ... second buried via layer, 18 ... electrode metal layer, 19 ... fifth photoresist layer, 20 ... mounting substrate, 21 ... multilayer Ceramic substrate, 22 …… solder ball, 23 …… LSI chip, 24 …… solder bump, 33 …… through hole.

Claims (1)

[Claims] 1. A through-hole provided in a silicon wafer, an insulating film provided on the surface of the silicon wafer including an inner wall of the through-hole, and a silicon film formed by being embedded in the through-hole. Embedded wiring insulated from the wafer, mounting wiring connected to the upper surface of the embedded wiring and extending on the insulating film, an interlayer insulating film formed on the surface including the mounting wiring, and the interlayer insulating film. A mounting substrate having an embedded via layer formed to be embedded in the opening formed in and connected to the mounting wiring; and an electrode connected to an upper surface of the embedded via layer, and a substrate exposed on the back surface of the mounting substrate. A multilayer wiring board electrically connected to the lower surface of the embedded wiring via a solder ball; and an LSI chip mounted by flip-chip bonding on the electrode exposed on the upper surface of the mounting board. That electronic apparatus.