JPH0727993B2 - Semiconductor chip carrier and semiconductor device - Google Patents
Semiconductor chip carrier and semiconductor deviceInfo
- Publication number
- JPH0727993B2 JPH0727993B2 JP1247098A JP24709889A JPH0727993B2 JP H0727993 B2 JPH0727993 B2 JP H0727993B2 JP 1247098 A JP1247098 A JP 1247098A JP 24709889 A JP24709889 A JP 24709889A JP H0727993 B2 JPH0727993 B2 JP H0727993B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- chip carrier
- conductive pattern
- printed wiring
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体搭載用に用いられる半導体チップキ
ャリアに関するものであり、特に表面実装用の半導体チ
ップキャリアに関するものである。Description: TECHNICAL FIELD The present invention relates to a semiconductor chip carrier used for mounting a semiconductor, and more particularly to a surface mounting semiconductor chip carrier.
プリント配線板からなる半導体チップキャリアとして第
5図に示すようなものが知られている。この半導体チッ
プキャリアCは絶縁層1の表面に導電パターン2を配設
したプリント配線板の周縁部において、導電パターン2
と外部端子3とが接合されたものである。この半導体チ
ップキャリアCは半導体チップ7をその中央部に搭載し
ワイヤー8で導電パターン2と接続組立し、半導体チッ
プ7を保護するために樹脂封止層9が構成された半導体
装置としてマザーボード6に実装される。しかしなが
ら、この半導体装置の外部端子3を半田付けでマザーボ
ード6に実装する時、前記導電パターン2と外部端子3
とを一般に行われる半田付けで接合した半導体チップキ
ャリアCでは、半田付け部分4が同時に溶融し、外部端
子3と導電パターン2の接続が破断されるという問題が
ある。この現象は、絶縁層から垂直にピンを外部端子と
して備えた半導体装置をマザーボードに設けられたスル
ホールに挿入して半田付けする従来の挿入実装の場合、
半導体装置を搭載した表側と反対側で加えられる半田付
けの熱がマザーボードと言う一種の断熱材で遮断される
のに比べ、表面実装の場合には半田付けの熱が半導体装
置と同じ側から加えられるので前記導電パターンと外部
端子とを半田付けで接続固着した接合部分の半田が融け
ると言う問題がより大きくなるのである。したがって、
表面実装に供される半導体装置において外部端子を導電
パターンに接続固着した接合部分の溶融を回避する必要
があった。As a semiconductor chip carrier composed of a printed wiring board, one shown in FIG. 5 is known. The semiconductor chip carrier C has a conductive pattern 2 at the peripheral portion of a printed wiring board in which the conductive pattern 2 is provided on the surface of the insulating layer 1.
And the external terminal 3 are joined together. This semiconductor chip carrier C has a semiconductor chip 7 mounted on the central portion thereof, is connected and assembled with the conductive pattern 2 by a wire 8, and is mounted on a mother board 6 as a semiconductor device having a resin sealing layer 9 for protecting the semiconductor chip 7. To be implemented. However, when the external terminal 3 of this semiconductor device is mounted on the mother board 6 by soldering, the conductive pattern 2 and the external terminal 3 are
In the semiconductor chip carrier C, which is joined by commonly used soldering, there is a problem that the soldered portion 4 is melted at the same time and the connection between the external terminal 3 and the conductive pattern 2 is broken. This phenomenon occurs in the case of the conventional insertion mounting in which a semiconductor device having pins vertically as an external terminal from an insulating layer is inserted into a through hole provided on a mother board and soldered.
Compared to the fact that the heat of soldering applied on the side opposite to the side on which the semiconductor device is mounted is blocked by a kind of heat insulating material called a motherboard, in the case of surface mounting the heat of soldering is applied from the same side as the semiconductor device. Therefore, the problem that the solder at the joint portion where the conductive pattern and the external terminal are connected and fixed by soldering is melted becomes more serious. Therefore,
In a semiconductor device used for surface mounting, it is necessary to avoid melting of the joint portion where the external terminal is connected and fixed to the conductive pattern.
半導体チップキャリアのプリント配線板の表面の導体パ
ターンと外部端子の接合部分が強固で、この半導体チッ
プキャリアからなる半導体装置をマザーボードに半田付
けで表面実装が可能な半導体チップキャリアを提供する
ことにある。It is an object of the present invention to provide a semiconductor chip carrier in which a conductor pattern on a surface of a printed wiring board of a semiconductor chip carrier and an external terminal are firmly joined to each other, and a semiconductor device including the semiconductor chip carrier can be surface-mounted by soldering to a motherboard. .
本発明は前記課題を解決するために、絶縁層の表面に導
電パターンを配設したプリント配線板の周縁部におい
て、導電パターンと接合された外部端子とこの接合部分
を覆いプリント配線板の周縁部に形成された絶縁帯とを
有することを特徴とする半導体チップキャリアを提供す
ることにある。In order to solve the above-mentioned problems, the present invention provides a peripheral portion of a printed wiring board in which a conductive pattern is provided on the surface of an insulating layer, and an external terminal joined to the conductive pattern and the joint portion are covered. Another object of the present invention is to provide a semiconductor chip carrier characterized by having an insulating band formed on the.
以下図面に基づいて詳しく説明する。第1図は本発明の
一実施例に係る半導体チップキャリアの斜視図で半導体
チップを搭載してワイヤーボンドしたものであり、第2
図は第1図の半導体チップキャリアに半導体チップを保
護するために樹脂で封止を施した構成の半導体装置をマ
ザーボードに表面実装した使用状態を第1図のX−Y断
面図で示したものである。本発明の一実施例に係る第2
図の半導体チップキャリアAは、絶縁層1とその表面に
配設した導電パターン2とからなるプリント配線板の周
縁部において、導電パターン2と外部端子3とを接合す
る部分4が形成され、この接合部分4を包み覆うように
プリント配線板の周縁部に流動性を有する接着材が硬化
した絶縁帯5が形成されたものである。好ましくは、こ
の絶縁帯5がプリント配線板の周縁部に堰堤状に形成さ
れたものであり、絶縁帯5でプリント配線板の表面に凹
部が形成されている。かかる半導体チップキャリアAの
前記凹部の内側に半導体チップ7が搭載され、ワイヤー
8で導電パターン2と接続組立され、半導体チップ7を
保護するために樹脂封止層9が形成された構成の半導体
装置を得、この半導体装置をマザーボード6に半田付け
で実装する場合に、前記導電パターン2と外部端子3と
の接合部分4が一般によく用いられる半田付けで接合さ
れていても、この接合部分4を包み覆うようにプリント
配線板の周縁部に流動性を有する接着材が硬化した絶縁
帯5が形成されているために容易に接合部分が、はずれ
ることはないのである。なお、前記絶縁帯5が熱伝導物
で形成され、しかもこの絶縁帯5の表面に熱伝導帯10が
配設された他の実施例を示す半導体チップキャリアBに
半導体チップを搭載してワイヤーボンドしたものの斜視
図が第3図であり、第4図は第3図のX−Y断面図であ
り、この第4図の半導体チップキャリアBに半導体チッ
プを保護するために樹脂で封止を施して構成した半導体
装置をマザーボードに表面実装した使用状態を示す。こ
の半導体チップキャリアBの前記堰堤状に形成された凹
部の内側に半導体チップ7が搭載され、ワイヤー8で導
電パターン2と接続組立され、半導体チップ7を保護す
るために樹脂封止層9が形成された構成の半導体装置を
得、この半導体装置をマザーボード6に半田付けで実装
する場合に、マザーボード6への半田付けの熱が外部端
子3、導電パターン2と外部端子3との接合部分4、次
に熱伝導性に優れた接着材料が硬化した絶縁帯5へと移
動し、さらに熱伝導性に優れかつプリント配線板の周縁
部に堰堤状に形成された熱伝導帯10へと移動して放熱す
る。この作用によって、導電パターン2と外部端子3と
の接合部分4が半田付けで接続固着されていても接合部
分4が溶融するまでにマザーボード6への半田付けによ
る実装を終えることができる。したがって、先に半田付
けで接続固着した外部端子3が導電パターン2から剥が
れる恐れは一層なくなるのである。A detailed description will be given below with reference to the drawings. FIG. 1 is a perspective view of a semiconductor chip carrier according to an embodiment of the present invention in which a semiconductor chip is mounted and wire-bonded.
The figure shows a state in which the semiconductor device having a structure in which the semiconductor chip carrier of FIG. 1 is sealed with a resin to protect the semiconductor chip is surface-mounted on the mother board in an X-Y sectional view of FIG. Is. Second embodiment according to the present invention
In the semiconductor chip carrier A shown in the figure, a portion 4 for joining the conductive pattern 2 and the external terminal 3 is formed in the peripheral portion of the printed wiring board consisting of the insulating layer 1 and the conductive pattern 2 provided on the surface thereof. An insulating band 5 is formed on the peripheral edge of the printed wiring board so as to cover and cover the joint portion 4, and an adhesive material having fluidity is hardened. Preferably, the insulating strip 5 is formed in a peripheral wall of the printed wiring board in the shape of a dam, and the insulating strip 5 forms a recess on the surface of the printed wiring board. A semiconductor device having a structure in which the semiconductor chip 7 is mounted inside the recess of the semiconductor chip carrier A, is connected and assembled with the conductive pattern 2 by the wire 8, and the resin sealing layer 9 is formed to protect the semiconductor chip 7. When this semiconductor device is mounted on the mother board 6 by soldering, even if the joint portion 4 between the conductive pattern 2 and the external terminal 3 is joined by soldering which is commonly used, Since the insulating band 5 formed by hardening the adhesive having fluidity is formed on the peripheral portion of the printed wiring board so as to cover the printed wiring board, the joint portion does not easily come off. It is to be noted that a semiconductor chip is mounted on a semiconductor chip carrier B showing another embodiment in which the insulating band 5 is formed of a heat conductive material, and the heat conductive band 10 is provided on the surface of the insulating band 5, and wire bonding is performed. 3 is a perspective view of FIG. 4 and FIG. 4 is a sectional view taken along the line XY of FIG. 3. The semiconductor chip carrier B of FIG. 4 is sealed with resin to protect the semiconductor chip. The semiconductor device configured as above is shown in a usage state in which the semiconductor device is surface-mounted on a motherboard. The semiconductor chip 7 is mounted inside the recess formed in the dam-like shape of the semiconductor chip carrier B, is connected and assembled with the conductive pattern 2 by the wire 8, and the resin sealing layer 9 is formed to protect the semiconductor chip 7. When the semiconductor device having the above-described configuration is obtained and the semiconductor device is mounted on the mother board 6 by soldering, the heat of the soldering on the mother board 6 causes the external terminal 3, the connecting portion 4 between the conductive pattern 2 and the external terminal 3, Next, the adhesive material having excellent thermal conductivity moves to the cured insulating band 5, and further moves to the thermal conductive band 10 which has excellent thermal conductivity and is formed like a dam in the peripheral portion of the printed wiring board. Dissipate heat. By this action, even if the joint portion 4 between the conductive pattern 2 and the external terminal 3 is connected and fixed by soldering, the mounting on the mother board 6 by soldering can be completed before the joint portion 4 melts. Therefore, the possibility that the external terminal 3 which has been connected and fixed by soldering first will be separated from the conductive pattern 2 is further reduced.
次に、本発明の半導体チップキャリアの使用材料につい
て述べる。第2図および第4図の半導体チップキャリア
を構成するプリント配線板の絶縁層1としては、基材に
樹脂を含浸乾燥して得られたプリプレグの樹脂を硬化し
た絶縁材料が用いられる。ここで絶縁層1の樹脂として
は耐熱性、耐湿性に優れかつ樹脂純度、特にイオン性不
純物の少ないものが好ましい。具体的にはエポキシ樹
脂、ポリイミド樹脂、不飽和ポリエステル樹脂、フッソ
樹脂、PPO樹脂などの樹脂が適している。なお絶縁層1
の基材としては、紙よりガラス繊維などの無機材料の方
が耐熱性、耐湿性などに優れ好ましい。Next, materials used for the semiconductor chip carrier of the present invention will be described. As the insulating layer 1 of the printed wiring board constituting the semiconductor chip carrier of FIGS. 2 and 4, an insulating material obtained by curing a resin of a prepreg obtained by impregnating a base material with a resin and drying is used. Here, as the resin of the insulating layer 1, a resin having excellent heat resistance and moisture resistance and a resin purity, particularly a small amount of ionic impurities, is preferable. Specifically, resins such as epoxy resin, polyimide resin, unsaturated polyester resin, fluorine resin, and PPO resin are suitable. Insulation layer 1
As the base material of (1), an inorganic material such as glass fiber is preferable to paper because of its excellent heat resistance and moisture resistance.
絶縁層1の表面に配設された導電パターン2としては
銅、真鍮、アルミニウム、鉄、ステンレスなどから適宜
選択して適用でき、中でも銅が導電性に優れ特に好まし
い。この導電パターン2を形成するにあたっては、アデ
ィティブ法、サブトラクティブ法などの種々の方法が用
いられる。The conductive pattern 2 provided on the surface of the insulating layer 1 can be appropriately selected and applied from copper, brass, aluminum, iron, stainless steel, etc. Among them, copper is particularly preferable because of its excellent conductivity. In forming the conductive pattern 2, various methods such as an additive method and a subtractive method are used.
外部端子3としては、銅、りん青銅、アルミニウム、
鉄、42アロイ(Ni42%のNi−Fe合金)などの金属の薄板
からプレス加工やエッチィングなどで形成したものから
適宜選択して適用でき、中でも42アロイが熱膨張係数が
小さく、強度の大きい点で優れ特に好ましい。As the external terminal 3, copper, phosphor bronze, aluminum,
Appropriately selected and applied from thin plates of metals such as iron and 42 alloy (Ni-42% Ni-Fe alloy) formed by pressing or etching. Among them, 42 alloy has a small thermal expansion coefficient and high strength. It is excellent and particularly preferable.
接合部分4は、樹脂製プリント配線板に一般に使用され
る錫−鉛系の半田によって形成できる。しかし、樹脂製
プリント配線板に損傷を与えない使用温度を有する半田
組成物であれば良く特に制限するものではない。また、
金属粉を含有する樹脂接着剤でもよく、金属粉が銀また
は、銅でバインダー樹脂がエポキシ樹脂やポリイミド樹
脂及びこれらの変性樹脂などを用いた樹脂組成物によっ
て形成することもできる。The joint portion 4 can be formed by tin-lead solder which is generally used for resin printed wiring boards. However, the solder composition is not particularly limited as long as it is a solder composition having a use temperature that does not damage the resin printed wiring board. Also,
A resin adhesive containing metal powder may be used, or the metal powder may be silver or copper, and the binder resin may be formed of a resin composition using an epoxy resin, a polyimide resin, or a modified resin thereof.
接合部分4を覆いプリント配線板の周縁部に堰堤状に形
成された絶縁帯5としては、耐熱性を有する熱硬化性樹
脂、熱可塑性樹脂をたとえば、前者ではエポキシ樹脂、
ポリイミド樹脂、不飽和ポリエステル樹脂、フェノール
樹脂など、後者ではポリイミド樹脂、ポリエーテルエー
テルケトン樹脂、ポリフェニレンサリファイド樹脂、ポ
リエーテルサルフォン樹脂などの中から適宜も用いるこ
とができる。なお、これら樹脂をバインダーとしてアル
ミナ、窒化ホウ素、窒化アルミナなどを充填材とした絶
縁性と熱伝導性に優れた接着材料が硬化した硬化物で構
成されるのがより好まし。As the insulating band 5 which covers the joint portion 4 and is formed in a dam-like shape in the peripheral portion of the printed wiring board, a thermosetting resin or a thermoplastic resin having heat resistance is used, such as an epoxy resin in the former case.
A polyimide resin, an unsaturated polyester resin, a phenol resin, or the like, and the latter can be appropriately used from among polyimide resin, polyether ether ketone resin, polyphenylene sulfide resin, polyether sulfone resin, and the like. It is more preferable that the resin is composed of a cured product obtained by curing an adhesive material having excellent insulating properties and thermal conductivity, in which alumina, boron nitride, or alumina nitride is used as a filler with these resins as a binder.
この接着材料の接着性を利用してプリント配線板の周縁
部に堰堤状に形成される熱伝導帯10は、アルミナ、窒化
ホウ素、窒化アルミナなどのセラミック、または銅、真
鍮、アルミニウム、鉄、ステンレスなどの金属から適宜
選択して適用でき、中でもアルミニウムが軽くて熱伝導
性に優れ特に好ましい。Utilizing the adhesiveness of this adhesive material, the heat conduction band 10 formed in a dam-like shape at the peripheral portion of the printed wiring board is a ceramic such as alumina, boron nitride, or alumina nitride, or copper, brass, aluminum, iron, stainless steel. Can be appropriately selected and applied from metals such as aluminum, and among them, aluminum is particularly preferable because it is light and has excellent thermal conductivity.
樹脂封止層9としては、この目的で通常用いられるエポ
キシ樹脂封止成形材料、ポリイミド樹脂封止成形材料お
よびポリフェニレンサルファイド樹脂封止成形材料など
が硬化した硬化物で構成することができ、耐湿性に優れ
る点でエポキシ樹脂封止成形材料が特に好ましい。The resin encapsulating layer 9 can be composed of a cured product obtained by curing an epoxy resin encapsulating molding material, a polyimide resin encapsulating molding material, a polyphenylene sulfide resin encapsulating molding material, or the like which is usually used for this purpose, and has a moisture resistance. An epoxy resin encapsulating molding material is particularly preferable in terms of excellent properties.
本発明は叙述の如く半導体チップキャリアにおいて、外
部端子をプリント配線板の周縁部において導電パターン
と接合し、この接合部分を包み覆う接着材料が硬化した
絶縁帯がプリント配線板の周縁部に堰堤状に形成された
ことよってプリント配線板表面に凹部が形成される。か
かる半導体チップキャリアの凹部に半導体チップを搭載
しワイヤーボンドで導電パターンと接続組立し、半導体
チップの保護のために樹脂封止層が形成された構成の半
導体装置とし、この半導体装置をマザーボードに半田付
けで表面実装する場合にも、プリント配線板の導体パタ
ーンと外部端子との接合部分が、樹脂が硬化した絶縁帯
で覆われて固定されているためにかかる接合部分がはず
れることなく半導体装置を半田付けでマザーボードに表
面実装することがができる。As described above, according to the present invention, in a semiconductor chip carrier, an external terminal is bonded to a conductive pattern at a peripheral portion of a printed wiring board, and an insulating band, which is hardened by an adhesive material and covers the bonded portion, has a dam-like shape at the peripheral portion of the printed wiring board. As a result, the concave portion is formed on the surface of the printed wiring board. A semiconductor chip is mounted in the recess of such a semiconductor chip carrier, and is connected and assembled with a conductive pattern by wire bonding to form a semiconductor device having a resin sealing layer formed for protection of the semiconductor chip, and the semiconductor device is soldered to a mother board. Even when surface mounting is performed by attaching the semiconductor device to the printed wiring board, the conductor pattern and the external terminal are fixed by being covered with the resin-cured insulating band and fixed. It can be surface-mounted on the motherboard by soldering.
第1図は本発明の一実施例を示す斜視図、第2図は第1
図のX−Yの断面図、第3図は本発明の他の実施例を示
す斜視図、第4図は第3図のX−Yの断面図、第5図は
一従来例を示す断面図である。 1…絶縁層、2…導電パターン 3…外部端子、4…接合部分 5…絶縁帯、6…マザーボード 7…半導体チップ、8…ワイヤー 9…樹脂封止層、10…熱伝導帯FIG. 1 is a perspective view showing an embodiment of the present invention, and FIG.
Fig. 3 is a sectional view taken along line XY, Fig. 3 is a perspective view showing another embodiment of the present invention, Fig. 4 is a sectional view taken along line XY in Fig. 3, and Fig. 5 is a sectional view showing a conventional example. It is a figure. DESCRIPTION OF SYMBOLS 1 ... Insulating layer, 2 ... Conductive pattern 3 ... External terminal, 4 ... Junction part 5 ... Insulating band, 6 ... Motherboard 7 ... Semiconductor chip, 8 ... Wire 9 ... Resin sealing layer, 10 ... Thermal conduction band
───────────────────────────────────────────────────── フロントページの続き (72)発明者 南 浩司 大阪府門真市大字門真1048番地 松下電工 株式会社内 (72)発明者 向井 薫 大阪府門真市大字門真1048番地 松下電工 株式会社内 (72)発明者 樋口 徹 大阪府門真市大字門真1048番地 松下電工 株式会社内 (56)参考文献 特開 昭59−168657(JP,A) 特開 昭51−90473(JP,A) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koji Minami 1048, Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Works, Ltd. (72) Kaoru Mukai 1048, Kadoma, Kadoma City, Osaka Matsushita Electric Works, Ltd. (72) Inventor Toru Higuchi 1048, Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Works, Ltd. (56) References JP 59-168657 (JP, A) JP 51-90473 (JP, A)
Claims (8)
リント配線板の周縁部において、導電パターンと接合さ
れた外部端子とこの接合部分を覆いプリント配線板の周
縁部に形成された絶縁帯とを有することを特徴とする半
導体チップキャリア。1. An insulating strip formed on a peripheral portion of a printed wiring board covering an external terminal joined to the conductive pattern and the joint portion at a peripheral portion of the printed wiring board having a conductive pattern arranged on a surface of an insulating layer. A semiconductor chip carrier having:
有することを特徴とする請求項1記載の半導体チップキ
ャリア。2. The semiconductor chip carrier according to claim 1, further comprising a heat conduction band formed on the surface of the insulating band.
を特徴とする請求項1または、2記載の半導体チップキ
ャリア。3. The semiconductor chip carrier according to claim 1, wherein the insulating band is formed of a resin composition.
とを特徴とする請求項1乃至3記載の半導体チップキャ
リア。4. The semiconductor chip carrier according to claim 1, wherein the resin composition is formed of a heat conductor.
徴とする請求項1乃至4記載の半導体チップキャリア。5. The semiconductor chip carrier according to claim 1, wherein the heat conduction band is made of metal.
とを特徴とする請求項1乃至4記載の半導体チップキャ
リア。6. The semiconductor chip carrier according to claim 1, wherein the heat conduction band is made of ceramic.
リント配線板の周縁部において、導電パターンと接合さ
れた外部端子と、この接合部分を覆いプリント配線板の
周縁部に堰堤状に形成された絶縁帯とが配設され、この
絶縁帯で形成された凹部の内側に搭載された半導体チッ
プが樹脂封止層で保護されていることを特徴とする半導
体装置。7. An outer terminal joined to a conductive pattern at a peripheral portion of a printed wiring board having a conductive pattern arranged on a surface of an insulating layer and a junction-shaped outer terminal formed in a dam-like shape at the peripheral portion of the printed wiring board. A semiconductor chip mounted inside the recess formed by the insulating band is protected by a resin sealing layer.
リント配線板の周縁部において、導電パターンと接合さ
れた外部端子と、この接合部分を覆いプリント配線板の
周縁部に堰堤状に形成された絶縁帯と、この絶縁帯の表
面に同形状で形成された熱伝導帯とが配設され、この絶
縁帯と熱伝導帯で形成された凹部の内側に搭載された半
導体チップが樹脂封止層で保護されていることを特徴と
する半導体装置。8. An outer terminal joined to a conductive pattern at a peripheral portion of a printed wiring board having a conductive pattern provided on a surface of an insulating layer, and a junction-shaped outer terminal formed in a dam-like shape at the peripheral portion of the printed wiring board. And a heat conduction band formed in the same shape on the surface of the insulation band, and the semiconductor chip mounted inside the recess formed by the insulation band and the heat conduction band is sealed with resin. A semiconductor device, which is protected by a stop layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1247098A JPH0727993B2 (en) | 1989-03-24 | 1989-09-22 | Semiconductor chip carrier and semiconductor device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1-73650 | 1989-03-24 | ||
| JP7365089 | 1989-03-24 | ||
| JP1247098A JPH0727993B2 (en) | 1989-03-24 | 1989-09-22 | Semiconductor chip carrier and semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0316161A JPH0316161A (en) | 1991-01-24 |
| JPH0727993B2 true JPH0727993B2 (en) | 1995-03-29 |
Family
ID=26414791
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1247098A Expired - Fee Related JPH0727993B2 (en) | 1989-03-24 | 1989-09-22 | Semiconductor chip carrier and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0727993B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1514633A2 (en) | 1997-10-22 | 2005-03-16 | Carl Zeiss Meditec AG | Device for shaping objects |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003526488A (en) * | 2000-03-13 | 2003-09-09 | 597990ビー.シー.リミテッド | Turntable for board binding |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5377468A (en) * | 1976-12-21 | 1978-07-08 | Seiko Instr & Electronics Ltd | Ic bonding sealing method |
| JP2652223B2 (en) * | 1988-11-16 | 1997-09-10 | イビデン株式会社 | Substrate for mounting electronic components |
-
1989
- 1989-09-22 JP JP1247098A patent/JPH0727993B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1514633A2 (en) | 1997-10-22 | 2005-03-16 | Carl Zeiss Meditec AG | Device for shaping objects |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0316161A (en) | 1991-01-24 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |