JPH0728012B2 - Semiconductor memory - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory in which regular memory cell groups are made uniform in shape and the chip size is reduced.

[Conventional technology]

Recently, semiconductor memory has become larger and larger, and with it,
The internal patterns are becoming finer and finer. As such miniaturization progresses, the exposure and etching rates are different at the end and inside of the regularly arranged memory cell group, and it is possible to form memory cells that are geometrically uniform at the end and inside of the memory cell. It has become difficult. As a result, an adverse effect such as an access difference between the end portion of the memory cell and the inside thereof occurs. Therefore, as shown in FIG. 3, a device such as a pseudo memory cell that does not function as an actual memory cell is arranged outside the regular memory cell group. By inserting this pseudo memory cell group, the peripheries of the regular memory cell groups become constant and the respective memory cells become uniform in shape, so that the access difference and the like can be minimized.

[Problems to be Solved by the Invention]

In the conventional semiconductor memory device described above, by arranging the pseudo memory cell group around the memory cell group, the regular memory cell group becomes uniform in shape, but since the pseudo memory cell group is inserted, the chip size is reduced. Has the drawback of becoming large.

[Means for Solving the Problems]

The semiconductor memory of the present invention is characterized in that, in a semiconductor memory having a redundant memory cell group, the redundant memory cell groups are arranged on four sides of the regular memory cell group so that the regular memory cell group has a uniform shape.

〔Example〕

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, 1 is a normal memory cell group, and 2 is a redundant memory cell group for relieving defective bits. The redundant memory cell group 2 is arranged in the four side directions of the normal memory cell group 1, and each memory cell of the normal memory cell group has a constant circumference, and therefore has a uniform shape. Further, by arranging the redundant memory cell group in the four side directions in this way, the regular memory cell group can have a uniform shape of the regular memory cell group without arranging the pseudo memory cell group. However, since the shape becomes non-uniform at the end of the redundant memory cell group, the characteristics may be affected when the redundant memory cell group for repairing the defective bit is used. However, the yield of the semiconductor memory is usually improved to a level where the redundant memory cell does not need to be used during the stable period of mass production, so it is considered that there is no problem even if the redundant memory cell is used as a pseudo memory cell.

FIG. 2 is a block diagram of Embodiment 2 of the present invention. In FIG. 1, the redundant memory cell group is evenly arranged around the normal memory cell group, but in FIG. 2, at least the peripheral memory cell group is surrounded by the redundant memory cell group. The arrangement of groups is uneven. This embodiment has an advantage that the number of wirings extending from the redundant memory cell activating circuit across the X decoder and the Y decoder is reduced.

〔The invention's effect〕

As described above, according to the present invention, by arranging the redundant memory cell group so as to be adjacent to the four sides of the normal memory cell group, there is no pseudo memory cell group that has been inserted until now, without increasing the chip size. There is an effect that the shape of each memory cell of the normal memory cell group can be made uniform and an adverse effect such as access difference can be prevented.

[Brief description of drawings]

1 and 2 are block diagrams of a memory cell group of the present invention. FIG. 3 is a block diagram of a conventional memory cell group. 1 ... Regular memory cell group, 2 ... Redundant memory cell group for repairing defective bit, 3 ... Pseudo memory cell group.

Claims (1)

[Claims] 1. In a semiconductor memory having a redundant memory cell group, the redundant memory cell group is arranged on four sides of the regular memory cell group so that the shape of each memory cell in the regular memory cell group is made uniform. Characteristic semiconductor memory.