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JPH0728046B2 - Semiconductor device - Google Patents
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JPH0728046B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0728046B2
JPH0728046B2 JP60129966A JP12996685A JPH0728046B2 JP H0728046 B2 JPH0728046 B2 JP H0728046B2 JP 60129966 A JP60129966 A JP 60129966A JP 12996685 A JP12996685 A JP 12996685A JP H0728046 B2 JPH0728046 B2 JP H0728046B2
Authority
JP
Japan
Prior art keywords
type
semiconductor
doped
crystal
photovoltaic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60129966A
Other languages
Japanese (ja)
Other versions
JPS61288474A (en
Inventor
真 平野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP60129966A priority Critical patent/JPH0728046B2/en
Publication of JPS61288474A publication Critical patent/JPS61288474A/en
Publication of JPH0728046B2 publication Critical patent/JPH0728046B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F30/00Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
    • H10F30/20Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
    • H10F30/21Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation
    • H10F30/22Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes
    • H10F30/222Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier being a PN heterojunction

Landscapes

  • Photovoltaic Devices (AREA)
  • Light Receiving Elements (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は製造が容易で、かつ高性能な光電地,光検出
器,N形およびP形電界効果トランジスタ,フオトトラン
ジスタおよびこれらの組み合わせによる無バイアスの光
検出器,無バイアスのフオトトランジスタ,コンプリメ
ンタリー回路,光電子回路等の半導体装置に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention is easy to manufacture and has a high performance such as a photoelectric device, a photodetector, an N-type and P-type field effect transistor, a phototransistor and a combination thereof. The present invention relates to semiconductor devices such as bias photodetectors, non-biased phototransistors, complementary circuits, and optoelectronic circuits.

(発明の概要) 本発明は基板上に形成されたPN接合を用いた光起電力半
導体装置において、前記のPN接合間に、P形およびN形
半導体のいずれよりも、バンドエネルギーギャップが小
で、かつノンドープないし、低ドープの第3半導体層を
配設し、前記の第3半導体層に対して、界面近傍に形成
される各キャリア層に対するP形オーミックコンタクト
と、N形オーミックコンタクトを夫々形成して、光起電
力装置を構成することを特徴とする半導体装置を提供す
るにある。
(Summary of the Invention) The present invention provides a photovoltaic semiconductor device using a PN junction formed on a substrate, which has a smaller band energy gap between the P and N semiconductors than the P and N semiconductors. A non-doped or low-doped third semiconductor layer is provided, and a P-type ohmic contact and an N-type ohmic contact for each carrier layer formed near the interface are formed with respect to the third semiconductor layer. Then, there is provided a semiconductor device characterized by constituting a photovoltaic device.

本発明は基板上に形成されたPN接合を用いた光起電力半
導体装置において、前記のPN接合間に、P形およびN形
半導体のいずれよりも、バンドエネルギーギャップが小
で、かつノンドープないし、低ドープの第3半導体層を
配設し、前記の第3半導体層に対して、界面近傍に形成
される各キャリア層に対する2個のN形オーミック電極
を形成し、前記の電極間にバイアス電圧を与えて光電流
検出装置を構成し、また同一結晶の他の領域で前記の第
3半導体層に対して界面近傍に形成される各キャリア層
に対するP形およびN形オーミック電極を形成して、光
起電力装置を構成し、前記の光起電力装置を、前記の光
電流検出装置のバイアス電源として用い、無バイアス光
電流検出装置を構成することを特徴とする半導体装置を
提供するにある。
The present invention provides a photovoltaic semiconductor device using a PN junction formed on a substrate, which has a band energy gap between the PN junctions smaller than that of P-type and N-type semiconductors and is non-doped or A low-doped third semiconductor layer is provided, two N-type ohmic electrodes for each carrier layer formed near the interface are formed on the third semiconductor layer, and a bias voltage is applied between the electrodes. To form a photocurrent detection device, and to form P-type and N-type ohmic electrodes for each carrier layer formed near the interface with the third semiconductor layer in another region of the same crystal, It is an object of the present invention to provide a semiconductor device, which constitutes a photovoltaic device, uses the photovoltaic device as a bias power source of the photocurrent detection device, and constitutes a non-biased photocurrent detection device.

(従来技術及び発明が解決しようとする問題点) (a)PN接合を利用した光起電力半導体装置としては、
第11図に示すように従来、P形半導体1,N形半導体2の
各々に直接コンタクト電極4,5を設けた素子が提供され
ていた。(参考文献:J.R.Davis et al:Conf.Rec.7th Ph
otovoltaic Spec.Conf.(9618)p.85) しかし、この素子では起電力はP形半導体1とN形半導
体2との間に生じるため、図中4,5のように本質的にコ
ンタクト電極はPN接合面3に対して各々反対側につけな
ければならず、高性能化のため受光面を大きくするのに
不利であつた。
(Problems to be Solved by Prior Art and Invention) (a) As a photovoltaic semiconductor device using a PN junction,
As shown in FIG. 11, conventionally, there has been provided an element in which a P-type semiconductor 1 and an N-type semiconductor 2 are directly provided with contact electrodes 4 and 5, respectively. (Reference: JR Davis et al: Conf.Rec. 7th Ph
otovoltaic Spec.Conf. (9618) p.85) However, since an electromotive force is generated between the P-type semiconductor 1 and the N-type semiconductor 2 in this element, the contact electrodes are essentially The PN junction surface 3 must be attached on the opposite side, which is disadvantageous in increasing the size of the light receiving surface for higher performance.

また、光照射によつて生じた電子・ホール等のキヤリヤ
ーは、第12図に示した原理図のようにPN接合面と垂直方
向に不純物結晶中を拡散によつて伝導せねばならず、直
列抵抗が大きくまたキヤリヤーの再結合等による消失も
大きく光−起電力変換効率を上げるのに困難さがあつ
た。図中6は励起光、7は光励起電子、8は光励起ホー
ル、9はN形半導体、10はP形半導体を示す。
In addition, carriers such as electrons and holes generated by light irradiation must be conducted by diffusion in the impurity crystal in the direction perpendicular to the PN junction plane by diffusion as shown in the principle diagram shown in Fig. 12. The resistance was large and the carrier was lost due to recombination, etc., and it was difficult to increase the photovoltaic-electromotive force conversion efficiency. In the figure, 6 is excitation light, 7 is photoexcited electrons, 8 is photoexcited holes, 9 is N-type semiconductor, and 10 is P-type semiconductor.

(b)また、光導電効果を利用した光電流検出装置とし
ては、第13図に示したように、従来、単に半導体12に2
個のN形オーミツク電極13,14を形成し励起光11による
励起電流を検出するものがあつた。(参考文献:R.H.Bub
e et al.:Phys.Rev.128(1962)532) この場合、半導体中を流れる光電流は、半導体中の不純
物による電子の散乱のため小さくなるという欠点があつ
た。
(B) Further, as a photocurrent detection device utilizing the photoconductive effect, as shown in FIG.
There is a device in which N-type ohmic electrodes 13 and 14 are formed and the excitation current by the excitation light 11 is detected. (Reference: RHBub
e et al.:Phys.Rev.128 (1962) 532) In this case, the photocurrent flowing in the semiconductor is small due to the scattering of electrons by impurities in the semiconductor.

(c)一方、光検出用のバイアス電圧を外部から印加す
る必要のない無バイアス光検出器としては、従来第14図
に原理的を示すように、励起光15によつて生じた電子16
を結晶の内部電界によつて集め、このヘテロ界面にチヤ
ネルと基板間の起電力をバイアス電圧として利用したも
のがあつた。図中17は光励起ホール、18はN−AlGaAs
側、19はノンドープ(P-,N-)GaAs側、20はヘテロ界
面、21は2次元電子ガスを示す。(参考文献:C.Y.Chen
et al:Appl.Phys.Lett.41(3)p282(1982)) これは、第15図に示すように基板側に電極をとらねばな
らないという素子形成上の欠点のため、工程が複雑とな
り、かつ同一結晶膜上に、他の素子と一緒に平面構成す
ることが困難であつた。
(C) On the other hand, as a non-biased photodetector which does not need to apply a bias voltage for photodetection from the outside, the electron 16 generated by the excitation light 15 is conventionally generated as shown in FIG.
Was collected by the internal electric field of the crystal, and this hetero interface used the electromotive force between the channel and the substrate as the bias voltage. In the figure, 17 is a photoexcitation hole and 18 is N-AlGaAs.
Side, 19 is a non-doped (P , N ) GaAs side, 20 is a hetero interface, and 21 is a two-dimensional electron gas. (Reference: CYChen
et al: Appl.Phys.Lett.41 (3) p282 (1982)) This is because of the defect in device formation that electrodes must be caught on the substrate side, as shown in FIG. In addition, it is difficult to form a planar structure together with other elements on the same crystal film.

また従来の一般の半導体による光電池,光検出器,フオ
トトランジスタ,電子回路等は、各各必要とする結晶層
構造,電極設置法がまちまちであつたため、同一結晶基
板上に、プレーナ形に組み合わせ構成するのは困難とい
う欠点があつた。
In addition, conventional photocells, photodetectors, phototransistors, electronic circuits, etc. made of general semiconductors have various required crystal layer structures and electrode installation methods. Therefore, they are combined in a planar form on the same crystal substrate. It had the drawback of being difficult to do.

(d)また、半導体ヘテロ界面に生じたN形およびP形
のキヤリヤーを用いる両種トランジスタ(参考文献:T.M
imura et al:Jan.J.Appl.Phys.20(1981)p598,H.L.Sto
mer et al:Appl.Phys.Lett.44(11)1,(1984)p1062)
によるコンプリメンタリー回路の構成法としては、従来
の個々のデバイスから容易に類推できる方法としては、
第16図に示すように、個々のデバイスを多層に積み重ね
るものが考えられるが、これは結晶成長上は上層結晶の
結晶品質の劣化という欠点、プロセス上は非プレーナ形
で工程が複雑になり、段差による配線切れなど多くの欠
点があつた。なお、図中85は基板、86はP−AlGaAs、87
はノンドープ(P-,N-)GaAs、88はN−AlGaAs、89は2
次元ホールガス、90は2次元電子ガス、91,93はソー
ス,ドレイン電極、92はゲート電極、94,96はソース,
ドレイン電極、95はゲート電極、97はPチヤネルFET、9
8はNチヤネルFETを示す。
(D) Further, both types of transistors using N-type and P-type carriers generated at the semiconductor hetero interface (reference: TM
imura et al: Jan.J.Appl.Phys.20 (1981) p598, HLSto
mer et al: Appl.Phys.Lett.44 (11) 1, (1984) p1062)
As a method of constructing a complementary circuit by, as a method that can be easily inferred from conventional individual devices,
As shown in Fig. 16, it is possible to stack individual devices in multiple layers, but this is a drawback that the crystal quality of the upper layer crystal deteriorates in terms of crystal growth, and the process is non-planar and the process becomes complicated, There were many defects such as wiring breaks due to steps. In the figure, 85 is a substrate, 86 is P-AlGaAs, 87
The non-doped (P -, N -) GaAs , 88 are N-AlGaAs, 89 is 2
Dimensional hole gas, 90 is two-dimensional electron gas, 91 and 93 are source and drain electrodes, 92 is a gate electrode, 94 and 96 are sources,
Drain electrode, 95 is gate electrode, 97 is P channel FET, 9
8 indicates an N channel FET.

(問題点を解決するための手段) 本発明の目的は、PN接合光起電力装置において、キヤリ
ヤーが不純物ドープされた半導体内を走行することによ
る特性劣化を防ぎ、またプレーナ形とすることで電極設
置位置からくる工程,素子構造への制限をとりのぞき、
簡便で高性能な光起電力装置を実現すること、また、こ
れを用いて、高性能な無バイアス光電流検出器,無バイ
アスフオトトランジスタを実現することにある。また同
時に、同一結晶を用いて、プレーナ形の簡便なN形およ
びP形のしきい値制御可能な電界効果トランジスタを形
成して、コンプリメンタリー回路を実現すること、かつ
上記のさまざまな素子を同一結晶上に組み合わせて、光
電子回路を実現することにある。
(Means for Solving Problems) It is an object of the present invention to prevent deterioration of characteristics due to a carrier traveling in an impurity-doped semiconductor in a PN junction photovoltaic device, and to provide a planar type electrode. Except for restrictions on the process and element structure that come from the installation position,
It is to realize a simple and high-performance photovoltaic device, and to use it to realize a high-performance non-biased photocurrent detector and non-biased phototransistor. At the same time, a simple planar N-type and P-type threshold-controllable field-effect transistor is formed using the same crystal to realize a complementary circuit, and the various elements described above are the same. It is to realize optoelectronic circuits by combining them on a crystal.

上記の目的を達成するため、本発明はPN接合間にエネル
ギーギヤツプの小さい、ノンドープ第3半導体を設置
し、ヘテロ界面に生じる2次元ガスの伝導を利用するこ
とにより、光励起された結晶の内部電界によつて加速さ
れたキヤリヤーを、結晶膜面に平行に、かつノンドープ
半導体中を走行させることを第1の主要な特徴とする。
従来の技術とは、結晶層構造が、第3半導体の設置とい
う点で異なり、またオーミツク電極の設置がすべて結晶
の同一表面上でよいという点で異なる。
In order to achieve the above-mentioned object, the present invention provides a non-doped third semiconductor having a small energy gap between PN junctions and utilizes the conduction of a two-dimensional gas generated at a hetero interface to form a photoexcited crystal. The first main feature is that the carrier accelerated by the internal electric field is made to run parallel to the crystal film surface and in the non-doped semiconductor.
It differs from the prior art in that the crystal layer structure is provided with the third semiconductor and that the ohmic electrodes are all provided on the same surface of the crystal.

(実施例) 次に本発明の実施例を説明する。なお実施例は一つの例
示であつて、本発明の精神を逸脱しない範囲で、種々の
変更あるいは改良を行いうることは言うまでもない。
(Example) Next, the Example of this invention is described. Needless to say, the embodiment is merely an example, and various modifications and improvements can be made without departing from the spirit of the present invention.

(I)第1図は、本発明による実施例の結晶構造の模式
図、第2図はそのバンドダイヤグラムである。
(I) FIG. 1 is a schematic diagram of a crystal structure of an example according to the present invention, and FIG. 2 is a band diagram thereof.

第1図に示した例のように、ノンドープのGaAs30をPド
ープのAl0.5Ga0.5As29とNドープのAl0.5Ga0.5As31では
さむと、第1図のようにGaAs30のP−Al0.5Ga0.5As29側
ヘテロ界面には2次元ホールガス40、N−Al0.5Ga0.5As
側ヘテロ界面には2次元電子ガス39が生じる。35は基
板、36は光照射面を示す。
As shown in FIG. 1, when undoped GaAs30 is sandwiched between P-doped Al 0.5 Ga 0.5 As29 and N-doped Al 0.5 Ga 0.5 As31, P-Al 0.5 Ga 0.5 of GaAs 30 is formed as shown in FIG. Two-dimensional hole gas 40, N-Al 0.5 Ga 0.5 As on As29 side hetero interface
A two-dimensional electron gas 39 is generated at the side hetero interface. Reference numeral 35 denotes a substrate, and 36 denotes a light irradiation surface.

ここで、ノンドープGaAs42中には第2図に示すようにポ
テンシヤルの傾斜が生じ、そこには従つてきわめて大き
な内部電界が生じることとなる。例として、ノンドープ
GaAs層厚を1000Åとし、GaAsバンドエネルギーギヤツプ
を1.4eVと仮定すると、計算上平均内部界面は140KV/cm
にも達する。41はN−AlGaAs、43はP−AlGaAsを示す。
Here, a potential gradient occurs in the non-doped GaAs 42 as shown in FIG. 2, and accordingly, an extremely large internal electric field is generated. As an example, undoped
Assuming a GaAs layer thickness of 1000Å and a GaAs band energy gap of 1.4 eV, the calculated average internal interface is 140 KV / cm.
Also reaches. 41 indicates N-AlGaAs and 43 indicates P-AlGaAs.

従つて、このノンドープGaAs層42中に光照射44によつて
電子37,ホール38が生ずると、各各のキヤリヤーは大き
な内部電界によつてほとんど飽和速度でヘテロ界面へと
流れ込む。従つて、ノンドープGaAsチヤネル層に対し
て、P形およびN形のオーミツクコンタクトを夫々Beイ
オン,Siイオン等によるイオン注入およびAuZnNi/Ti/Au,
AuGe/Ni等によるアロイにより、結晶膜平面上に形成
し、電気的に接続すると、第3図に示すようにこの両電
極間には、最高〜1.4V(GaAsのバンドエネルギーギヤツ
プ)の光起電力が生じる。図中45はP形オーミツク電
極、46はN形オーミツク電極、47はメサ分離、48は励起
光、49は光照射半導体を示す。ヘテロ界面を結晶膜平面
と平行に伝導するキヤリヤーは、従来のPN接合光電池と
異なりチヤネルがノンドープGaAs内にあるため不純物散
乱が小さく低抵抗となり、また再結合もしにくい。この
ため、光−起電力変換効率はきわめてよいものになる。
また、生ずるキヤリヤーの総数は光受光面積に比例し、
プレーナ形構成であるため受光面は簡便に任意に大きく
できることも、従来装置と異なるものである。
Therefore, when electrons 37 and holes 38 are generated in the non-doped GaAs layer 42 by the light irradiation 44, the carriers in each of the carriers flow into the hetero interface at a saturated velocity due to the large internal electric field. Therefore, P-type and N-type ohmic contacts are ion-implanted with Be ions, Si ions, etc., and AuZnNi / Ti / Au,
When formed on a crystal film plane by an alloy of AuGe / Ni and electrically connected, a maximum of ~ 1.4V (GaAs band energy gap) between both electrodes is obtained as shown in FIG. Photovoltaic is generated. In the figure, 45 is a P-type ohmic electrode, 46 is an N-type ohmic electrode, 47 is mesa separation, 48 is excitation light, and 49 is a light irradiation semiconductor. Unlike the conventional PN junction photovoltaic cell, the carrier that conducts the hetero interface parallel to the plane of the crystal film has a small impurity scattering and low resistance because the channel is in non-doped GaAs, and recombination is also difficult. Therefore, the photovoltaic-electromotive force conversion efficiency becomes extremely good.
Also, the total number of carriers generated is proportional to the light receiving area,
It is different from the conventional device in that the light receiving surface can be arbitrarily increased in size due to the planar structure.

(II)一方、上記結晶に第4図に示したように、2個の
N形のオーミツク電極55,56を形成し、これらの電極55,
56間にバイアス電圧52を印加し、これらの電極にはさま
れた半導体領域54に照射光50をあて、キヤリヤーを励起
すると、光電流53が両電極間に流れることになる。この
際のキヤリヤーの生成からヘテロ界面への伝導、ヘテロ
界面上の伝導に関しては、(I)と同様大きな結晶内部
電界により光励起されたキヤリヤーがまず加速され、次
にキヤリヤーは不純物散乱の少ないノンドープ結晶ヘテ
ロ界面を高速で流れるので、検出速度,検出効率が一般
のものより向上する。
(II) On the other hand, as shown in FIG. 4, two N-type ohmic electrodes 55, 56 are formed on the crystal, and these electrodes 55,
When a bias voltage 52 is applied between 56 and irradiation light 50 is applied to the semiconductor region 54 sandwiched between these electrodes to excite the carrier, a photocurrent 53 flows between both electrodes. Regarding the conduction from the generation of the carrier to the hetero interface and the conduction on the hetero interface in this case, the carrier photo-excited by the large internal electric field of the crystal is accelerated first, and then the carrier is the non-doped crystal with less impurity scattering. Since the hetero interface flows at a high speed, the detection speed and detection efficiency are improved as compared with general ones.

(III)第5図は同一結晶を用いて(I)にて示した光
電池を(II)にて示した光電流検出器のバイアス電圧源
として用いることにより、無バイアスの光検出器を構成
する場合の例である。図中57は励起光、58はメサ分離、
59はN形オーミツク電極、60はP形オーミツク電極、6
1,62はN形オーミツク電極、63,64は光照射半導体を示
す。すなわちN形オーミツク電極59,P形オーミツク電極
60間に生じた光起電力を、N形オーミツク電極61,62間
にバイアスとして加える。ここで電極59,60間の光起電
圧を1.4Vとして、この電極間の距離を5μmとすると、
ヘテロ界面のキヤリヤーには3KV/cm程度の電界が働き、
十分にキヤリヤーを加速することができる。
(III) FIG. 5 shows a non-biased photodetector using the same crystal and using the photocell shown in (I) as the bias voltage source of the photocurrent detector shown in (II). This is an example of the case. In the figure, 57 is excitation light, 58 is mesa separation,
59 is an N-type ohmic electrode, 60 is a P-type ohmic electrode, 6
Reference numeral 1,62 denotes an N-type ohmic electrode, and 63,64 denote light irradiation semiconductors. That is, N-type ohmic electrode 59, P-type ohmic electrode
The photoelectromotive force generated between 60 is applied as a bias between the N-type ohmic electrodes 61 and 62. Here, assuming that the photovoltaic voltage between the electrodes 59 and 60 is 1.4 V and the distance between the electrodes is 5 μm,
An electric field of about 3 KV / cm works on the carrier at the hetero interface,
Can fully accelerate the carrier.

このように単に平面上に配置された各種オーミツク電極
間の配線組み合わせのみによつて無バイアスの光検出器
を簡便に実現できる。
In this way, the bias-free photodetector can be easily realized only by the wiring combination between the various ohmic electrodes arranged on the plane.

(IV)第6図は同一結晶を用いて(II)にて示した光検
出装置を形成し、この2個のオーミツク電極66,67間の
半導体68上に、Ti,Au等のシヨツトキーゲート電極69を
設置し、N形電界効果トランジスタないしフオトトラン
ジスタを構成する例である。65はメサ分離を示す。
(IV) In FIG. 6, the photodetector shown in (II) is formed by using the same crystal, and a Schottky key of Ti, Au, etc. is formed on the semiconductor 68 between the two ohmic electrodes 66, 67. This is an example in which a gate electrode 69 is provided to form an N-type field effect transistor or a phototransistor. 65 indicates mesa separation.

この場合のゲート電極下のバンド・ダイヤグラムを第7
図に示すが、ゲート印加電圧によりヘテロ界面の2次元
ガスを制御する機構は、通常の2次元電子ガスヘテロ構
造FETと同じである。
The band diagram under the gate electrode in this case is
As shown in the figure, the mechanism for controlling the two-dimensional gas at the hetero interface by the voltage applied to the gate is the same as that of a normal two-dimensional electron gas heterostructure FET.

従つて、ゲート電極を透明度の高いものにすれば高性能
のフオトトランジスタを形成できる。フオトトランジス
タは光を照射しなければ、通常の電界効果トランジスタ
と同様に機能する。また(III)と同様、同一結晶に形
成した光電池と組み合わせれば、無バイアスのフオトト
ランジスタを構成することもできる。
Therefore, a high-performance phototransistor can be formed by using a highly transparent gate electrode. The phototransistor functions like a normal field effect transistor unless it is irradiated with light. Further, as in (III), an unbiased phototransistor can be formed by combining with a photovoltaic cell formed in the same crystal.

第7図はバンドダイヤグラムを示す。図中70はゲート電
極、71はN−AlGaAs、72はノンドープ(P-,N-)GaAs、7
3はP−AlGaAs、143は2次元電子ガス、144は励起光、1
45は光励起電子を示す。
FIG. 7 shows a band diagram. Figure 70 is a gate electrode, 71 is N-AlGaAs, 72 is non-doped (P -, N -) GaAs , 7
3 is P-AlGaAs, 143 is a two-dimensional electron gas, 144 is excitation light, 1
45 indicates a photoexcited electron.

(V)また第7図と同じ原理に基づき、ゲート電圧に負
に印加することでP形結晶とのヘテロ界面に生じた2次
元ホールガスの濃度をコントロールすることにより(第
8図参照)、P形トランジスタも同一結晶で構成でき
る。第8図において、99はゲート電極、100はP−AlGaA
s、101はノンドープ(P-,N-)GaAs、102はN−AlGaAs、
103は2次元電子ガス、104は2次元ホールガスを示す。
この場合は、オーミツク電極をP形のものを使用する。
N形とP形のトランジスタも同一結晶上にプレーナ形に
形成することができるので、従来のものより、はるかに
簡便にコンプリメンタリー回路を構成できる(第9図参
照)。第9図において、105は基板、106はP−AlGaAs、
107はノンドープAlGaAs、108はN−AlGaAs、109はノン
ドープAlGaAs、110はノンドープGaAs、111はノンドープ
GaAs、112は2次元ホールガス、113は2次元電子ガス、
114,116はP形オーミツク電極、115はゲート電極、117,
119はN形オーミツク電極、118はゲート電極、120,121
はPイオン注入領域、122,123はNイオン注入領域、124
は素子間分離を示す。
(V) Based on the same principle as in FIG. 7, by negatively applying the gate voltage to control the concentration of the two-dimensional hole gas generated at the hetero interface with the P-type crystal (see FIG. 8), The P-type transistor can also be composed of the same crystal. In FIG. 8, 99 is a gate electrode and 100 is P-AlGaA.
s, 101 is non-doped (P -, N -) GaAs , 102 are N-AlGaAs,
103 is a two-dimensional electron gas and 104 is a two-dimensional hole gas.
In this case, a P-type ohmic electrode is used.
Since the N-type and P-type transistors can also be formed in a planar type on the same crystal, a complementary circuit can be constructed much more easily than the conventional one (see FIG. 9). In FIG. 9, 105 is a substrate, 106 is P-AlGaAs,
107 is undoped AlGaAs, 108 is N-AlGaAs, 109 is undoped AlGaAs, 110 is undoped GaAs, and 111 is undoped.
GaAs, 112 is a two-dimensional hole gas, 113 is a two-dimensional electron gas,
114, 116 are P-type ohmic electrodes, 115 are gate electrodes, 117,
119 is an N-type ohmic electrode, 118 is a gate electrode, and 120 and 121.
Is a P ion implantation region, 122 and 123 are N ion implantation regions, 124
Indicates isolation between elements.

この手法によるコンプリメンタリー回路構成では、N
形,P形へのドーピング濃度の制御ないしN形,P形の両ト
ランジスタのゲート下のリセスエツチ量の制御(第10図
参照)により、しきい値を整合でき高性能を図れるとい
う利点がある。第10図において、125は基板、126はN−
AlGaAs、127はノンドープAlGaAs、128はノンドープGaA
s、129はノンドープAlGaAs、130はP−AlGaAs、131はノ
ンドープGaAs、132,134はP形オーミツク電極,133はゲ
ート電極、135,137はN形オーミツク電極、136はゲート
電極、138は2次元ホールガス、139は2次元電子ガス、
140,141はリセス・エツチ、142は素子間分離を示す。ま
た、Niをゲートメタルとして用い熱処理によりメタルを
沈下させ、しきい値制御するという方法も適用できる。
(参考文献:IEEE.EDL.Vol.EDL−5No.7 1984p241) 更に、後述のように、P形半導体を上層にしN形半導体
を下層にすることで、P形のコンタミによるパラレルコ
ンダクシヨンによるリーク電流の影響を除去できるた
め、回路の低消費電力化にも利点がある。
In the complementary circuit configuration by this method, N
By controlling the doping concentration of the N-type and P-type transistors or the amount of recess etching under the gates of both N-type and P-type transistors (see FIG. 10), there is an advantage that threshold values can be matched and high performance can be achieved. In FIG. 10, 125 is a substrate and 126 is N-
AlGaAs, 127 is undoped AlGaAs, 128 is undoped GaA
s and 129 are non-doped AlGaAs, 130 is P-AlGaAs, 131 is non-doped GaAs, 132 and 134 are P-type ohmic electrodes, 133 is a gate electrode, 135 and 137 are N-type ohmic electrodes, 136 is a gate electrode, 138 is a two-dimensional hole gas, 139 Is a two-dimensional electron gas,
Reference numerals 140 and 141 denote recess etching, and 142 denotes element isolation. Alternatively, a method of using Ni as the gate metal to cause the metal to sink by heat treatment and controlling the threshold value can also be applied.
(Reference: IEEE.EDL.Vol.EDL-5 No.7 1984p241) Furthermore, as will be described later, by using a P-type semiconductor as an upper layer and an N-type semiconductor as a lower layer, leakage due to parallel conduction due to P-type contamination. Since the influence of the current can be removed, there is an advantage in reducing the power consumption of the circuit.

(VI)以上のように光電池,光電流検出器,N形およびP
形電界効果トランジスタ,フオトトランジスタはすべて
同一結晶を用いてプレーナ形に形成できるため、同一ウ
エハ−上にこれらを組み合わせて形成し様々な光電子回
路を構成することができる。
(VI) Photocell, photocurrent detector, N type and P
Since the field effect transistor and the phototransistor can be formed in a planar shape using the same crystal, various optoelectronic circuits can be formed by combining them on the same wafer.

(VII)なお、以上に用いた結晶の層構造としては、第
9図および第10図に示したようにヘテロ界面近傍のAl
0.5Ga0.5Asの不純物濃度を小さくすると、不純物の拡散
や散乱の効果を抑制して素子性能の向上に有効である。
また、混晶のAl組成比は0.5以外のものでも可能であ
る。更に、P,N半導体について、これらへのドーピング
濃度を、ヘテロ界面に近いほど大きく、遠いほど小さく
して分布させ丁度ヘテロ界面へのキヤリヤーの供給によ
つてPN半導体層は空乏化するように構成すると、オーミ
ツクコンタクトをとつた際に、高移動度の2次元ガス以
外のパラレルコンダクシヨンをひろわないですむ。
(VII) The layer structure of the crystal used above is, as shown in FIGS. 9 and 10, Al near the hetero interface.
Reducing the impurity concentration of 0.5 Ga 0.5 As is effective in improving the device performance by suppressing the effects of impurity diffusion and scattering.
The Al composition ratio of the mixed crystal may be other than 0.5. Further, regarding P and N semiconductors, the doping concentration to these is distributed so that it becomes larger as it is closer to the hetero interface and smaller as it is far, and the PN semiconductor layer is depleted just by supplying the carrier to the hetero interface. Then, when an ohmic contact is made, it is not necessary to spread parallel conduction other than high mobility two-dimensional gas.

また、一般にMBE結晶では結晶がP-形のコンタミを持つ
ため、P形のパラレルコンダクシヨンを防ぐ手法とし
て、結晶の上層をP形として、下層をN形とする方法が
ある。このように構成すればP形オーミツクを結晶厚方
向に深くしすぎなければ容易に、P形のパラレルコンダ
クシヨンを除去できる。Al0.5Ga0.5As表面に保護用のノ
ンドープGaAs層をキヤツプとして設けると、表面酸化等
から防ぐことができる。
In general, since an MBE crystal has a P -type contamination, as a method for preventing P-type parallel conduction, there is a method in which the upper layer of the crystal is P-type and the lower layer is N-type. According to this structure, the P-type parallel conduction can be easily removed without making the P-type ohmic too deep in the crystal thickness direction. Providing a protective non-doped GaAs layer as a cap on the Al 0.5 Ga 0.5 As surface can prevent surface oxidation and the like.

(発明の効果) 以上説明したように、本発明によれば、光励起キヤリヤ
ーに働く内部電界が大きく、かつ、2次元電子ガス,2次
元ホールガスの利用により不純物散乱・再結合による特
性劣化の少ない、高性能の光起電力装置,光電流検出装
置,フオトトランジスタ、またこれらの組み合わせによ
る無バイアスの光検出器,無バイアスのフオトトランジ
スタ等を同一結晶上に製作が容易なプレーナ形に構成で
きる。これは、光センサー,光電源等に応用できる。
(Effect of the Invention) As described above, according to the present invention, the internal electric field acting on the photoexcited carrier is large, and the characteristic deterioration due to impurity scattering and recombination due to the use of the two-dimensional electron gas and the two-dimensional hole gas is small. , A high-performance photovoltaic device, a photocurrent detection device, a phototransistor, and a non-biased photodetector, a non-biased phototransistor and the like by combining them can be configured in a planar type which can be easily manufactured on the same crystal. This can be applied to optical sensors, optical power supplies, etc.

また更に、同一結晶上に、高移動度の2次元ガスをキヤ
リヤーとして用いる高性能のN形,P形の電界効果トラン
ジスタをしきい値整合して形成し、高性能のコンプリメ
ンタリー回路を同様にプレーナ形に構成できる。これら
様々な光電子素子を同一結晶上に組み合わせて構成し高
性能の光電子回路を実現し、計算機,中継器等の光通信
機器などに応用することができる。
Furthermore, high-performance N-type and P-type field-effect transistors using a high-mobility two-dimensional gas as a carrier are formed on the same crystal in a threshold-matching manner, and a high-performance complementary circuit is also formed. Can be configured as a planar type. It is possible to realize a high-performance optoelectronic circuit by combining these various optoelectronic elements on the same crystal and apply it to optical communication equipment such as computers and repeaters.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明による光起電力装置の結晶構造を示す
図、第2図は本発明の第一の特徴を最もよく表わしてい
る光起電力装置の原理を示すバンドダイヤグラム、第3
図は本発明による光起電力装置の構成図、第4図は本発
明による光電流検出装置の構成図、第5図は本発明によ
る無バイアス光電流検出装置の構成図、第6図は本発明
による(光)電界効果トランジスタの構成図、第7図は
本発明による(光)電界効果トランジスタの原理を示す
バンドダイヤグラム、第8図は本発明の第二の特徴を最
もよく表わしているコンプリメンタリー回路の原理を示
すバンドダイヤグラム、第9図は本発明によるコンプリ
メンタリー回路構成の一実施例、第10図は本発明による
コンプリメンタリー回路構成の他の実施例、第11図は従
来のPN接合光起電力装置の模式図、第12図は従来のPN接
合光起電力装置の原理を示したバンドダイヤグラム、第
13図は従来の光電流検出器の模式図、第14図は従来の無
バイアス光電流検出器の原理を示したバンドダイヤグラ
ム、第15図は従来の無バイアス光電流検出器の模式図、
第16図は従来のコンプリメンタリー回路の構成模式図を
示す。 1,10……P型半導体 2,9,13,14……N型半導体 3……PN接合面 4,32,45,60,91,93,114,116,132,134……P形オーミツク
電極 5,22,23,33,46,55,56,59,61,62,66,67,94,96,117,119,1
35,137……N形オーミツク電極 6,11,15,34,44,48,50,57,144……励起光 7,16,37,145……光励起電子 97……PチヤネルFET 98……NチヤネルFET 8,17,38……光励起ホール 12,24,36,49,54,63,64……光被照射半導体 25……導電層 47,51,58,65……メサ分離 18,31,41,71,88,102,108,126……N−AlGaAs 107,109,127,129……ノンドープ(P-,N-)AlGaAs 19,30,42,72,82,101,110,111,128,131……ノンドープ
(P-,N-)GaAs 20……ヘテロ界面 120,121……P+イオン注入領域 122,123……N+イオン注入領域 21,39,90,103,113,139,143……2次元電子ガス 40,89,104,112,138……2次元ホールガス 124,142……素子間分離 26,52……バイアス電圧 27,53……光電流 140,141……リセス・エツチ 29,43,73,86,100,106,130……P−AlGaAs 35,85,105,125……バツフアー層,基板等 69,70,92,95,99,115,118,133,136……ゲート電極
FIG. 1 is a diagram showing a crystal structure of a photovoltaic device according to the present invention, and FIG. 2 is a band diagram showing the principle of the photovoltaic device which best represents the first feature of the present invention.
FIG. 4 is a configuration diagram of a photovoltaic device according to the present invention, FIG. 4 is a configuration diagram of a photocurrent detection device according to the present invention, FIG. 5 is a configuration diagram of a non-biased photocurrent detection device according to the present invention, and FIG. FIG. 7 is a configuration diagram of an (optical) field effect transistor according to the invention, FIG. 7 is a band diagram showing the principle of the (optical) field effect transistor according to the invention, and FIG. 8 is a complete diagram showing the second feature of the invention. FIG. 9 is a band diagram showing the principle of a mental circuit, FIG. 9 is an embodiment of the complementary circuit structure according to the present invention, FIG. 10 is another embodiment of the complementary circuit structure according to the present invention, and FIG. 11 is a conventional PN junction. Fig. 12 is a schematic diagram of a photovoltaic device, and Fig. 12 is a band diagram showing the principle of a conventional PN junction photovoltaic device.
13 is a schematic diagram of a conventional photocurrent detector, FIG. 14 is a band diagram showing the principle of a conventional non-biased photocurrent detector, FIG. 15 is a schematic diagram of a conventional non-biased photocurrent detector,
FIG. 16 shows a schematic diagram of the configuration of a conventional complementary circuit. 1,10 …… P-type semiconductor 2,9,13,14 …… N-type semiconductor 3 …… PN junction surface 4,32,45,60,91,93,114,116,132,134 …… P-type ohmic electrode 5,22,23,33 , 46,55,56,59,61,62,66,67,94,96,117,119,1
35,137 …… N-type ohmic electrode 6,11,15,34,44,48,50,57,144 …… Excitation light 7,16,37,145 …… Photoexcited electron 97 …… P channel FET 98 …… N channel FET 8,17 , 38 …… Photoexcitation hole 12,24,36,49,54,63,64 …… Light-irradiated semiconductor 25 …… Conductive layer 47,51,58,65 …… Mesa separation 18,31,41,71,88,102,108,126 ...... N-AlGaAs 107,109,127,129 ...... undoped (P -, N -) AlGaAs 19,30,42,72,82,101,110,111,128,131 ...... undoped (P -, N -) GaAs 20 ...... hetero interface 120,121 ...... P + ion implantation region 122,123 …… N + ion implantation region 21,39,90,103,113,139,143 …… two-dimensional electron gas 40,89,104,112,138 …… two-dimensional hole gas 124,142 …… isolation between elements 26,52 …… bias voltage 27,53 …… photocurrent 140,141… … Recess Etch 29,43,73,86,100,106,130 …… P-AlGaAs 35,85,105,125 …… Buffer layer, substrate 69,70,92,95,99,115,118,133,136 …… Gate electrode

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 7630−4M H01L 31/08 L ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Office reference number FI technical display location 7630-4M H01L 31/08 L

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】基板上に形成されたPN接合を用いた光起電
力半導体装置において、前記のPN接合間に、P形および
N形半導体のいずれよりも、バンドエネルギーギャップ
が小で、かつノンドープないし、低ドープの第3半導体
層を配設し、前記の第3半導体層に対して、界面近傍に
形成される各キャリア層に対するP形オーミックコンタ
クトと、N形オーミックコンタクトを夫々形成して、光
起電力装置を構成することを特徴とする半導体装置。
1. A photovoltaic semiconductor device using a PN junction formed on a substrate, wherein a band energy gap between the PN junctions is smaller than that of a P-type semiconductor and an N-type semiconductor and is non-doped. Alternatively, a low-doped third semiconductor layer is provided, and a P-type ohmic contact and an N-type ohmic contact for each carrier layer formed near the interface are formed on the third semiconductor layer, respectively. A semiconductor device comprising a photovoltaic device.
【請求項2】基板上に形成されたPN接合を用いた光起電
力半導体装置において、前記のPN接合間に、P形および
N形半導体のいずれよりも、バンドエネルギーギャップ
が小で、かつノンドープないし、低ドープの第3半導体
層を配設し、前記の第3半導体層に対して、界面近傍に
形成される各キャリア層に対する2個のN形オーミック
電極を形成し、前記の電極間にバイアス電圧を与えて光
電流検出装置を構成し、また同一結晶の他の領域で前記
の第3半導体層に対して界面近傍に形成される各キャリ
ア層に対するP形およびN形オーミック電極を形成し
て、光起電力装置を構成し、前記の光起電力装置を、前
記の光電流検出装置のバイアス電源として用い、無バイ
アス光電流検出装置を構成することを特徴とする半導体
装置。
2. A photovoltaic semiconductor device using a PN junction formed on a substrate, wherein a band energy gap between the PN junction is smaller than that of a P-type semiconductor and an N-type semiconductor, and is non-doped. Alternatively, a low-doped third semiconductor layer is provided, two N-type ohmic electrodes for each carrier layer formed near the interface are formed on the third semiconductor layer, and between the electrodes. A bias current is applied to form a photocurrent detection device, and P-type and N-type ohmic electrodes for each carrier layer formed near the interface with the third semiconductor layer in another region of the same crystal are formed. And a photovoltaic device, wherein the photovoltaic device is used as a bias power source of the photocurrent detection device to form a non-biased photocurrent detection device.
JP60129966A 1985-06-17 1985-06-17 Semiconductor device Expired - Lifetime JPH0728046B2 (en)

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Application Number Priority Date Filing Date Title
JP60129966A JPH0728046B2 (en) 1985-06-17 1985-06-17 Semiconductor device

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Application Number Priority Date Filing Date Title
JP60129966A JPH0728046B2 (en) 1985-06-17 1985-06-17 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS61288474A JPS61288474A (en) 1986-12-18
JPH0728046B2 true JPH0728046B2 (en) 1995-03-29

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