JPH0728228B2 - Convolutional encoder - Google Patents

Description

The present invention relates to an error correction code encoder, and more particularly to a convolutional encoder having a code coding rate of 1/2 and constraint lengths of 4 and 7.

[Conventional technology]

Conventionally, in this type of encoder, the circuit for generating the check bit is separately configured by the constraint length K of the target error correction code as shown in FIGS. 4 (a) and 4 (b). FIG. 4 (a) shows a case where the constraint length K is 4, serial information data is input from the terminal 31 to the four-stage shift register 51, and when x ⁴ + x ² + x is used as the generator polynomial, the shift register 51 is used.
The exclusive OR of the outputs of the first, second, and fourth stages of the above is taken by the exclusive OR circuit 52, and x ⁴ + x ³ + x ^{2 is obtained} as a generator polynomial.
When + x is used, the exclusive OR circuit 53 takes the exclusive OR of the outputs of the first, second, third, and fourth stages of the shift register 51 to generate each check bit. It is output from the terminals 41 and 42.

Similarly, FIG. 4 (b) shows the case where the constraint length K is 7, the serial information data 31 is input from the terminal 32 to the shift register 54 of 7 stages, and x ⁷ + x ⁵ + x ⁴ + x ² + x is generated as a generator polynomial. When used, the exclusive OR circuit of the outputs of the first, second, fourth, fifth and seventh stages of the shift register 54 is an exclusive OR circuit.
In 55, when x ⁷ + x ⁵ + x ⁴ + x ³ + x ² + x is used as the generator polynomial, the first stage, second stage, third stage, fourth stage, fifth stage, and seventh stage of the shift register 54 The exclusive OR of the respective outputs is taken by the exclusive OR circuit 56, and the respective check bits are generated and output from the terminals 43 and 44.

Each check bit output from each terminal 41, 42, 43, 44 is sequentially combined with a bit of input information data by a circuit (not shown) in the encoder to generate a convolutional code in each case. .

[Problems to be solved by the invention]

The above-mentioned convolutional encoders having the coding rate of 1/2 and the constraint lengths of 4 and 7 are configured separately for the constraint length of 4 and the constraint length of 7, respectively, A convolutional encoder with a constraint length of 7 cannot be used also as a convolutional encoder with a constraint length of 4, and a conventional convolutional encoder with a coding rate of 1/2 and constraint lengths of 4 and 7 is However, since the input information data is serially input, the encoder is required to operate according to the speed of the data, and there is a drawback that it is difficult to cope with the speedup.

[Means for solving problems]

The convolutional encoder of the present invention is a four-stage first configuration in which each serial bit of serial information data is serially / parallel-converted by 2 bits and each 1 bit of the parallel data is input.
The second shift register and the outputs of the third and fourth stages of the first shift register are blocked when the constraint length is designated as 4 by an external control signal, and the constraint length is designated as 7. The first and second gates which respectively output when they are driven, and the outputs of the third and fourth stages of the second shift register,
When the constraint length is designated as 4 by the control signal, the respective gates are blocked when the constraint length is designated as 7, and output when the constraint length is designated as 7, and 1 of the first shift register.
A first exclusive OR circuit for receiving the output of the second stage, the outputs of the second and third stages of the second shift register, and the outputs of the first and second gates; and 1st stage and 2
A second exclusive OR circuit that inputs the output of the first stage, the output of the first stage of the second shift register, and the outputs of the third and fourth gates, and the output of the first exclusive OR circuit And a third exclusive OR circuit that inputs the second-stage output of the first shift register, an output of the second exclusive-OR circuit, and an output of the second stage of the second shift register. It has a circuit for generating a check bit which is composed of a fourth exclusive OR circuit.

In this way, by switching the external signal to turn off or turn on the gate circuit, it is possible to obtain the check bit in each case with the same circuit depending on whether the constraint length is 4 or 7. Since the information data is processed in parallel, the encoder can handle high speed according to the data speed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a circuit for generating check bits in an embodiment of a convolutional encoder of the present invention, and FIG. 2 is a block diagram showing a circuit configuration when the constraint length K is 4 in the present embodiment. FIG. 3 is a block diagram showing a circuit configuration when the constraint length K is set to 7 in this embodiment.

The serial information data input to the encoder is converted into 2-bit parallel data in order from the first bit by a serial-parallel conversion circuit (not shown), and the first shift register 1 having four stages has terminals 11 to 2 connected thereto. One odd bit of the bits is sequentially input. Similarly, an even-numbered 1-bit of 2 bits is sequentially input from the terminal 12 to the second shift register 2 having a four-stage configuration. The first and second gates 7 and 8 receive a signal inputted from the terminal 13 so that the constraint length K of the target code is K.
Are turned off when 4 is 4 and turned on when the constraint length K is 7, and the first shift register 1 is turned on.
The output of the third and fourth stages is blocked and output again. Similarly, the third and fourth gates 9 and 10 are both turned off when the restraint length K is 4 and turned on when the restraint length K is 7 by the signal, and are respectively turned to the second gate. The output of the third stage and the output of the fourth stage of the shift register 2 are blocked or output. The first exclusive OR circuit 3 outputs the first stage output of the first shift register 1 and the second shift register 2
The outputs of the third and third stages and the outputs of the first gate 7 and the second gate 8 are input, the exclusive OR from the inputs is taken, and the result is output to the terminal 21. The second exclusive OR circuit 4 is
The outputs of the first and second stages of the first shift register 1,
The output of the first stage of the second shift register 2 and the outputs of the third gate 9 and the fourth gate 10 are input, their exclusive ORs are taken, and output to the terminal 22. The third exclusive OR circuit 5 inputs the output of the second stage of the first shift register 1 and the output of the first exclusive OR circuit 3 and takes the exclusive OR of these terminals. Output to 23. The fourth exclusive-OR circuit 6 inputs the output of the second stage of the second shift register 2 and the output of the second exclusive-OR circuit 4 and takes the exclusive-OR of them to obtain a terminal 24. Output to.

Next, the operation of this embodiment will be described.

(1) First, the case where the constraint length K is 4 will be described.

In this case, since all the gates 7, 8, 9, 10 are turned off, the outputs of the third and fourth stages of the first and second shift registers 1 and 2 are the same as those of the second shift register. Since all but a part of the output of the stage is blocked, the circuit configuration shown in FIG. 2 is obtained. If the bit sequence of the input serial information data at a certain point is ..., it, it _{+ 1} , it _{+ 2} , it _{+ 3} , ... (where t is an odd number), a serial-parallel conversion circuit (not shown) By 2
Since it is converted into a pair of parallel signals of bits (it, it ₊₁ ) and (it ₊₂ , it ₊₃ ) and is sequentially input from the terminals 11 and 12, the first shift register 1 and the second stage 1 Bit it and bit in the tier
it ₊₂ is the second stage and the first stage of the second shift register bits it ₊₁ and bit it ₊₃ is input. Therefore,
From the terminal 22, a signal of the exclusive OR of the bit it, the bit it ₊₂ and the bit it ₊₃ is obtained through the second exclusive OR circuit 4, which is the conventional signal of FIG. 4 (a). The signal is exactly the same as the signal when the generator polynomial x ⁴ + x ² + x described in the above circuit is used. Similarly, from the terminal 24, the signal of the exclusive OR of the bit it, the bit it _{+ 1} , the bit it _{+ 2,} and the bit it _{+ 3} is sent via the second and fourth exclusive OR circuits 4 and 6. Obtained, this is the 4th
Generator polynomial x ⁴ + x ³ + x ² explained in the conventional circuit of FIG.
The signal is exactly the same as when using + x. These signals output from the terminals 22 and 24 are respectively subjected to check bits in the last bit it ₊₃ and combined by a circuit (not shown) so that the coding rate is 1/2 and the constraint length K is 4 Is output as a convolutional code.

(2) Next, a case where the constraint length K is 7 will be described.

In this case, since all the gates 7, 8, 9, 10 are turned on, the outputs of the third and fourth stages of the first and second shift registers 1 and 2 are all output. The circuit configuration shown in the figure is obtained. In this case as well, by setting the bit sequence of the input serial information data at a certain point in time to ..., it, it _{+ 1} , ..., it _{+ 6} , it _{+ 7} , the above-mentioned constraint length K is 4 In exactly the same way, the same signal as that when the generator polynomial x ⁷ + x ⁵ + x ⁴ + x ² + x described in the conventional circuit of FIG. the conventional signal and the same signal when using the generator polynomial ^{x 7 + x 5 + x 4} + x 3 + x 2 + x in the circuit of FIG. 4 (b) is output, can be easily inferred. These signals output from the terminals 21 and 23 are connected to the last bit it ₊₆ as a check bit by a circuit (not shown), and the coding rate is 1/2 and the constraint length K is 7 It is output as an embedded code.

The convolutional code thus also influences the coding of each block within which the information bits of the preceding block are within the constraint length.

In the present embodiment, the first shift register 1 receives the odd-order bits of the serial input information data and the second shift register 2 receives the even-order bits, but the opposite is true. However, it does not matter, and although the operation is described using a specific generator polynomial, it can be easily analogized that it can be applied to the case of using another generator polynomial.

〔The invention's effect〕

As described above, according to the present invention, in the convolutional encoder having the coding rate of 1/2 and the constraint lengths of 4 and 7, two shift registers having four stages and four exclusive OR circuits are provided. A circuit for generating a check bit is configured by using four gates, all gates are turned off when the constraint length is 4 and all the gates are turned off when the constraint length is 7 by using an external control signal. By turning on the gate, a check bit can be generated in one circuit when the constraint length is 4 or 7, and since the information data processed in parallel is handled, it is processed in the conventional circuit. It has the effect of being able to handle constraint data processing that could not be done.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit for generating check bits, which is an embodiment of a convolutional encoder of the present invention. FIG. 2 is a block diagram when the constraint length K is 4 in FIG. 1, and FIG. Is a block diagram when the constraint length K is set to 7 in FIG.
FIGS. 4 (a) and 4 (b) are block diagrams showing a check bit generation circuit of a conventional circuit corresponding to this embodiment. 1,2 …… Shift register, 3,4,5,6 …… Exclusive OR circuit, 7,8,9,10 …… Gate, 11,12 …… Parallel data input terminal, 13 …… Restricted length Control signal input terminal, 21,22,23,24 …… inspection bit output terminal, K …… restraint length, it to it _{+ 7} …… input information data bit.

Claims (1)

[Claims] 1. In a convolutional encoder, serial information data that has been input is serial-parallel converted by 2 bits in order, and 1-bit each of the parallel data is input, and first and second four-stage configurations are provided. The output of the shift register and the output of the third and fourth stages of the first shift register are blocked when the constraint length is designated as 4 by an external control signal, and when the constraint length is designated as 7. The output of the first and second gates and the outputs of the third and fourth stages of the second shift register are respectively blocked when the constraint length is designated as 4 by the control signal. The third and fourth gates which respectively output when designated as 7, the output of the first stage of the first shift register, the output of the second and third stages of the second shift register, and the first and the first First exclusive theory of inputting each output of two gates A logical sum circuit, a second exclusive input for inputting the outputs of the first and second stages of the first shift register, the output of the first stage of the second shift register, and the outputs of the third and fourth gates. Of the first exclusive OR circuit and the third exclusive OR circuit for inputting the output of the first exclusive OR circuit and the output of the second stage of the first shift register, and the second exclusive OR circuit. A convolutional encoder having a circuit for generating a check bit, which comprises an output and a fourth exclusive OR circuit for receiving the output of the second stage of the second shift register.