JPH0728281B2 - Sync signal detector - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for transmitting or recording / reproducing a digital signal, and more particularly to a sync signal detecting device suitable for a system using digital modulation. 2. Description of the Related Art A conventional synchronizing signal detecting device is disclosed in, for example, Japanese Patent Application Laid-Open No. 55-107360, "110".
By applying a pattern such as "0" to a synchronization signal pattern that is repeated a plurality of times and digitally detecting the repetition of the pattern as described above, the accuracy and stability of synchronization detection are improved, and an error in the signal is detected. Even if the number is large, there is one that can detect the synchronization, but no consideration was given to the case where the synchronization signal pattern is not the repetitive pattern as described above. The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and even in the case of a sync signal which is not a repetition of a short pattern such as an m-sequence signal pattern which is usually used, a sync detection can be performed accurately and stably, and an error occurs in the signal. SUMMARY OF THE INVENTION It is an object of the present invention to provide a synchronization signal detecting device capable of detecting synchronization even when there are many cases. To this end, the present invention provides a device for processing an output signal of a digital demodulator which has a synchronizing signal inserted as a digital pattern in transmission data and demodulates a signal which is digitally modulated and transmitted. When a counter for sequentially counting the polarity inversion intervals of the digital signal output from the digital demodulator and the count output of the counter are connected and the combination of the count values matches the combination of the count values of a predetermined synchronization signal pattern and transmission When a coincidence is found with a combination of one or more count values obtained by a synchronization signal pattern including an error pattern with a high probability of occurring in the digital modulation signal used for It is characterized in that a decoder for outputting a detection pulse is provided. [Operation] As described above, the stability of synchronization detection is ensured by detecting all error patterns with a high probability of occurrence as synchronization signals, and the synchronization signal patterns appearing in the signal data other than the synchronization signal portion. The accuracy of synchronization detection can be improved by lowering the probability of erroneously detecting a pattern similar to that as a synchronization pattern, and reducing the circuit scale of the decoder if the number of patterns that output synchronization detection pulses is reduced. An embodiment of the present invention will now be described with reference to the drawings, in which a case where the present invention is applied to a signal processing circuit of a compact disc will be described. 11-bit "1" + 11-bit "0" or 11-bit "0" + 11-bit "1" pattern is used It is but, from "0" to "1", or "1" from a high probability of occurrence of errors in the change point to the "0".
Therefore, in addition to the correct pattern, 10 bits “1” +
If four patterns of 12 bits “0”, 10 bits “0” +12 bits “1”, 12 bits “1” +10 bits “0”, 12 bits “0” +10 bits “1” are detected, synchronization is achieved. It is possible to increase the stability of detection. FIG. 1 is a block diagram showing an embodiment of a synchronization detecting device according to the present invention, in which 1 is a data input terminal, 2 is a clock input terminal, 4a is a decode pulse generating circuit, and 4a.
b to 4d are RS flip-flops, 4e to 4g are AND
Gates 4h, 4i are OR gates, 5 is an output terminal, and 6 is a counter. In the figure, the digital signal reproduced from the disc is transferred from the data input terminal 1 to the G of the counter 6.
Input to the terminal. At the same time, a clock synchronized with digital data is input to the clock input terminal 2 and input to the CLK terminal of the counter 6. The counter 6 is reset at each edge of the digital signal input to the G terminal,
The number of clock signals input from the CLK terminal in the "0" section or "1" section of the digital signal is counted, and the output is supplied to the decode pulse generating circuit 4a. The decode pulse generation circuit 4a checks the count value of the counter 6 for each edge of the digital signal, and outputs a pulse from each output terminal when the count value is 10, 11, 12 or other cases. If the sync signal is correct, first, 11 bits are counted,
The RS flip-flop 4c is set and the AND gate 4f is opened. Then, when 11 bits are counted,
A pulse is output via the AND gate 4f, and a synchronization detection pulse is output from the output terminal 5 via the OR gate 4h. Then, the RS flip-flop 4c is reset via the OR gate 4i, and the AND gate 4f is closed.
An error has occurred and the synchronization pattern is 10 bits "1" + 12
When the bit becomes "0", first, 10 bits are counted, the RS flip-flop 4b is set to open the AND gate 4e, and subsequently, when 12 bits are counted, the AND gate 4e and the OR gate are 4h
A sync detection pulse is output via the OR gate 4i, the RS flip-flop 4b is reset via the OR gate 4i, and the AND gate 4e is closed. When the synchronization pattern is 12 bits “1” +10 bits “0”, etc.
The synchronization detection pulse is output by the flip-flop 4d and the AND gate 4g via the OR gate 4h. Further, when a pattern other than these is input, a pulse is output from the "X" terminal of the decode pulse generation circuit 4a, and the RS flip-flop 4 via the OR gate 4i.
Since b to 4d are reset, the sync detection pulse is not output. As described above, for example, when the synchronization signal is inserted in the transmission data as a pattern in which the polarity is inverted with a predetermined pulse width, the input signal is input to the counter,
If a decoder that outputs a sync detection pulse when the combination of the count values of this counter matches the sync signal pattern is used, the sync signal pattern can be accurately and stably no matter what the digital pattern is. Sync detection is possible. In this method, in order to enable the synchronization detection even when there are many errors in the signal, the decoder used for pattern detection is used not only for the correct synchronization signal pattern but also for the synchronization pattern including an error. The synchronous detection pulse may be output. For example, even if the polarity change point of the sync signal pattern includes a 1-bit error in the time axis direction as in the present embodiment, in order to enable the sync detection, a correct sync pattern and two 1-bit time axis directions are required. A decoder that outputs a synchronization pulse may be used when the combination of the count values of the counter matches any one of the three types of error synchronization patterns. Such a decoder can be easily configured by using a ROM or PLA. By the way, like the audio signal of satellite broadcasting,
When the transmission data is 4-phase differential PSK modulation,
When differentially demodulating at the receiver, error propagation occurs and a paired error of 2 bits occurs. In such a system having a high probability of occurrence of a 2-bit error, in order to enable the synchronization detection even in the case of a synchronization pattern including an error, one bit that is propagated by an error before and after the synchronization pattern and generated in the synchronization pattern In consideration of the error, the decoder used for detecting the synchronization pattern is configured to output the synchronization detection pulse even to the combination of the count values of the counter in the case of the synchronization pattern including all the 1 and 2 bit errors, and the modulation is performed. The synchronization detection may be performed after the signal demodulation. For example, like satellite broadcasting,
When using a 16-bit sync signal pattern,
The sync detection pulse may be output for all 120 patterns of 2 bit errors in 16 bits, 16 patterns of all 1 bit errors, and a total of 137 patterns of correct sync patterns. On the other hand, due to the nature of the transmission method and modulation / demodulation method used in the system including the synchronization pattern including these errors, even if the number of error bits is the same, the synchronization detection is performed for the pattern having a lower probability of occurrence. If the decoder is configured so as not to output a pulse, a great effect is produced. That is, all the error patterns with a high probability of occurrence are detected as the synchronization signal to ensure the stability of the synchronization detection, and a pattern similar to the synchronization signal pattern appearing in the signal data other than the synchronization signal portion is erroneously detected. The accuracy of synchronization detection can be improved by reducing the probability of detection as a synchronization pattern. If the number of patterns for outputting the sync detection pulse is reduced, the circuit scale of the decoder can be reduced. For example, in satellite broadcasting, a digital signal is 4-phase differential PSK modulated, and due to its nature, a paired error of 2 bits occurs in the demodulated digital signal, but the error pattern is 2 bits continuous. There are three types of error: 1-bit correct bit sandwiching 2-bit error, 2-bit correct bit sandwiching 2-bit error. Therefore,
In this case, the sync pattern detection decoder is used to set the 2-bit continuous error pattern 15 in the 16-bit sync signal pattern.
Pattern and 2-bit error pattern every other bit 14
Pattern and 2-bit error pattern every 2 bits 13
The latter half of the 2-bit error that occurs before the pattern and the sync signal pattern is the 1-bit error in the sync signal, and the latter half of the 2-bit error that occurs in the sync signal pattern is the latter half of the sync signal pattern. The sync detection pulse may be output for a total of 48 patterns of 1-bit error 3 patterns which are data errors and a correct sync signal pattern. In this case, the size of the decoder can be reduced to about 1/3 as compared with the case of detecting all patterns of 1 or 2 bit error. As mentioned above, the present invention is also effective for a sync signal pattern such as a compact disc, and can be applied to other modulation methods. Furthermore, even if the length of the pattern is not an integer multiple of the bit length, it can be handled by selecting the frequency of the clock used for detection.
A pattern such as +4.5 bit "0" can also be detected. As described above, according to the present invention,
Since it is possible to detect a sync signal pattern having an error pattern with a high probability of occurrence with a small circuit scale and prevent detection as a sync signal for more patterns than necessary, it is possible to accurately and accurately detect even if there are many errors in the signal. A synchronization signal can be stably detected, and a synchronization signal detection device having an excellent function can be provided excluding the above-mentioned drawbacks of the prior art.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a synchronization signal detecting device according to the present invention. [Description of Reference Signs] 1 ... Data input terminal, 2 ... Clock input terminal, 4a ... Decode pulse generation circuit, 4b-4d ... RS flip-flop, 4e-4g ... AND gate, 4h, 4i ... OR gate, 5 ... Output terminal , 6 ... Counter.

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Claims (1)

[Claims] 1. It has a sync signal inserted as a digital pattern in the transmitted data, and the digital modulation method is a 4-phase differential PS.
In a device for processing an output signal of a digital demodulator for demodulating a K transmitted signal, a digitally modulated digital signal or a digital signal of the output of the digital demodulator is input, and a "0" level section of the digital signal, " A counter for measuring the length of a 1 "level section and an error which is connected to the output of the counter and has a high probability that the value measured by the counter will occur in a predetermined synchronization signal pattern and a digital modulation signal used for transmission 1 one or a plurality of a decoder for outputting a sync detection pulse when the match one of the one or more synchronization signal pattern including the error probable to occur in the synchronization signal pattern or digital modulation demodulated by the decoder, 2 B
Continuous error, 2 bit error every other bit, 2 bit
An error pattern due to three types of 2-bit error
When a sync signal pattern containing the
A synchronization signal detecting device characterized in that it is adapted to output .