JPH0728398B2 - LCD panel drive - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal panel driving device used for driving a panel of a liquid crystal television.

Configuration of Conventional Example and Its Problems Conventional liquid crystal panel (LCD) driving is, for example, as shown in FIG. 1, when the number of picture elements is 240 (vertical) × 252 (horizontal), a bipolar transistor circuit with a clock frequency of 5 MHz as V _CO Or T
It is oscillated by TL-IC, etc., and it is driven in addition to the Y driver arranged on only one side of the panel without multiplying it.

However, the driving device configured as described above has the following problems.

(A), large power consumption. That is, the frequency is high,
Since a bipolar transistor circuit is used for stable operation, the IC consumes a large amount of current and consumes a large amount of power.

(B) Large unnecessary radiation. That is, since there is a large amount of power, there are also many harmonic interferences of the clock signal.

(C) It is disadvantageous in cost reduction and size reduction. For cost reduction and miniaturization, it is desirable to use one chip as much as possible, but in the conventional one, most of the controller circuits are C-MOS circuits, so only the oscillator (VCO) is on a separate chip as before. In that case, the IC cannot be miniaturized, which is disadvantageous in terms of cost.

(D) It is disadvantageous in terms of mounting. In the mounting means for connecting the terminals of the LCD and the terminals of the IC, it is difficult to mount because the terminal spacing is narrow.

An object of the present invention is to solve the above-mentioned conventional problems and to reduce the power consumption so that the visible time can be extended even in the case of battery operation, and to reduce the size and thickness of the circuit. It is an object of the present invention to provide a liquid crystal panel drive device which can be highly integrated and can be easily mounted on a chip.

The liquid crystal driving device according to the present invention is provided with a circuit for multiplying the frequency of the pulse output of the oscillator in which the PLL system is locked by the TV synchronizing signal, and driving the one driver of the LCD by the multiplied pulse, The clock is passed through an inverter and the phase is inverted 180 ° to drive the other driver.

Description of Embodiments An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an overall block diagram of a liquid crystal television in which the present invention can be implemented. Among these, a detailed block diagram of a conventional synchronous control circuit (controller) is shown in a broken line in FIG.

In Fig. 1, the TV signal from the antenna 1 is VI in the tuner 2.
The signals are converted into F, SIF signals, amplified by the IF amplification circuit 3, and detected by the video detection circuit 4. Then, it is branched for video and for audio. The audio signal is applied to the audio circuit 5 and the speaker 6. 7 is an AGC circuit. The detected video signal is input to the synchronization control circuit (controller) 8 of the display unit,
It generates timing pulses to the X and Y drivers 10 and 12 for driving the LCD panel 11. A video amplifier circuit 9 supplies a video signal to the Y driver 10.

FIG. 2 is a block diagram of a conventional controller circuit, in which the voltage controlled oscillator 13 is a frequency divider circuit (I) 14 and a phase comparator.
A PLL system using the horizontal synchronizing signal as a reference signal is constructed by using the low frequency filter 16, the low frequency filter 16 and the sync separating circuit 17 to stabilize the frequency. The signal from the VCO 13 is used directly (without multiplication) as the Y driver clock signal. For example, when the number of picture elements is 252, the clock frequency is 5 MHz.

However, this method has various problems as described above. Therefore, in the present invention, first, a digital frequency multiplier that lowers the oscillation frequency is required.

FIG. 3 shows the voltage controlled oscillator (VC
FIG. 4 is a more detailed block diagram of O), and FIG. 4 is a block diagram of a controller IC of a liquid crystal driving device using the same. 5 and 6 are explanatory views of the operation.

The clock signal is CLY to the Y driver, and is about 5 MHz when the number of picture elements is 252. As the clock signal to the X driver, the horizontal period signal of the TV is 15.75KHz.
Is. Also, as a data signal, DY is sent to the Y driver.
So it is 15.75KHz and 60Hz to the X driver. The Y driver supplies a vertical signal of the panel, and the X driver is for line scanning of the panel.

FIG. 4 is a block diagram of the controller and panel drive. Reference numeral 10a is a driver on the upper surface side of the Y driver, and 10b is a lower Y driver. The waveforms of the clock pulses input to the respective drivers are shown in FIG. CLYA and CLYB have a phase of 180
° Different. And the arrow means that the driver works at the up edge.

Further, in the figure, 12a is an X driver arranged on the left side of the panel 11, and 12b is an X driver arranged on the right side of the panel 11, which are arranged alternately on the left side and the right side of the panel 11. Each of them is connected to a vertical electrode (not shown). X
A clock pulse CLx supplied from the frequency dividing circuit 14 at a timing of 1H is input to both the drivers 12a and 12b.

FIG. 6 shows how the terminals of the panel and the Y driver are connected. For example, 10a connects to the odd number of terminals and 10b connects to the even number of the panel. Reference numeral 19 is an inverter for phase inversion. Reference numeral 14 is a frequency dividing circuit for setting the clock frequency to the horizontal frequency (H) of the television, and 18 is a frequency dividing circuit for setting 2H to 60H. 25 is the terminal number of the LCD panel.

Next, the operation will be described. First, as shown in FIG. 3, the output pulse waveform of the oscillator 21 whose duty ratio is not 50% is shaped into the duty ratio of 50% by the correction circuit 22, and then the frequency is multiplied by the frequency multiplication circuit 23. Manipulation of these pulse waveforms is easy.

However, since this is not sufficient, the pulse with a duty ratio of 50% that has been multiplied is directly used as the drive pulse CLYA for the shift register of the upper Y driver 10a, while the other pulse for the lower Y driver 10b is A pulse CLYB is used, which is 180 ° phase-shifted by inverting the phase of the pulse with an inverter.

This is the Y driver 10 on the upper surface of the panel as shown in FIG.
a is connected to the one with an odd terminal number and
The driver 10b is connected to an even numbered terminal number on the panel. The clock signal CLYA is input to the Y driver 10a, and CLYB is input to the Y driver 10b.

As shown in Fig. 5, CLYA and CLYB are 180 degrees out of phase. If the Y driver operates in the up-edge mode, the panel can be equivalently driven at twice the clock. Therefore, as a whole, the panel can be driven at a frequency of 4 times. Therefore, the VCO oscillation frequency is 5MHz in the past.
In that case, in the present embodiment, the VCO has a completely similar function at a frequency of 5/4 = 1.25 MHz.

As described above, according to the present invention, the oscillation frequency of the oscillator can be lowered, power can be reduced in the case of an IC, and the configuration can be simplified. Will also be possible. Therefore, there are advantages of downsizing and cost reduction. Also, due to the reduction of power, the harmonic interference of the clock is reduced. Also, by connecting the X driver to the left and right by dividing the panel terminals, which are alternately arranged on the left side and the right side with respect to the electrodes, it is possible to double the distance between the terminals to be connected. This makes it easier to improve the productivity of a small LCD TV with a screen size of 11 inches or less. Further, by providing the X drivers on the left and right sides and inputting the clock pulse at the same time, it is possible to prevent the decrease in the brightness due to the line resistance, which occurs in the case of the large-inch liquid crystal panel, and to prevent the uneven brightness from occurring.

[Brief description of drawings]

FIG. 1 is a block diagram of a liquid crystal panel driving device of a conventional example, FIG. 2 is a detailed block diagram of a main portion thereof, and FIGS. 3 and 4 are main portions of a liquid crystal panel driving device according to an embodiment of the present invention. 5 is a waveform diagram thereof, and FIG. 6 is a block diagram of its main part. 8 ... Synchronous control circuit, 10,10a, 10b ... Y driver, 12
...... X driver, 13 …… Voltage control oscillator, 21 …… Original voltage control oscillator, 22 …… Correction circuit, 23 …… Frequency multiplication circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-57-52088 (JP, A) JP-A-57-207287 (JP, A) JP-A-55-8161 (JP, A)

Claims (1)

[Claims] 1. A voltage controlled oscillator comprising a source voltage controlled oscillator, a duty correction circuit for shaping and outputting a duty ratio of an output pulse waveform, and a frequency multiplication circuit for multiplying and outputting the output frequency. And first and second X drivers for line scanning of the liquid crystal panel, which are arranged on the upper, lower, left and right sides of the liquid crystal panel for driving the liquid crystal panel,
A first Y driver for supplying a vertical signal of the liquid crystal panel, and a first Y driver of the liquid crystal panel and an output multiplication clock of the output multiplication clock of the frequency multiplication circuit.
The second Y driver is driven by a clock whose phase is inverted by 0 °, a data signal obtained by dividing the output multiplication clock is supplied to each Y driver, and the data signal is supplied to the first and second X drivers. A liquid crystal panel drive device that is supplied as a clock signal to the driver.