JPH0731215B2 - Latch type overcurrent detection circuit - Google Patents
Latch type overcurrent detection circuitInfo
- Publication number
- JPH0731215B2 JPH0731215B2 JP219288A JP219288A JPH0731215B2 JP H0731215 B2 JPH0731215 B2 JP H0731215B2 JP 219288 A JP219288 A JP 219288A JP 219288 A JP219288 A JP 219288A JP H0731215 B2 JPH0731215 B2 JP H0731215B2
- Authority
- JP
- Japan
- Prior art keywords
- josephson
- source
- current
- fet
- detection circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000001514 detection method Methods 0.000 title claims description 21
- 241000238366 Cephalopoda Species 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 3
- 239000008186 active pharmaceutical agent Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
Landscapes
- Measuring Magnetic Variables (AREA)
- Measurement Of Current Or Voltage (AREA)
- Emergency Protection Circuit Devices (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、超伝導素子を用いた回路に関し、特にラッチ
式過電流検出回路に関する。The present invention relates to a circuit using a superconducting element, and more particularly to a latch type overcurrent detection circuit.
［従来の技術］ 従来、この種の過電流検出回路は、第３図に示すように
被測定電流線12に直列に挿入される検出抵抗11と前記検
出抵抗の両端電圧を検出するオペアンプ９とオペアンプ
９の出力側に接続されたサイリスタ14と、検出抵抗11と
オペアンプ９間に接続される基準電圧源10及び抵抗13に
よって構成されていて、上記オペアンプ９で上記検出抵
抗11の両端電圧を検出すると共に、そのオペアンプ９の
出力によりサイリスタ14を駆動することにより検出を実
行していた。[Prior Art] Conventionally, as shown in FIG. 3, an overcurrent detection circuit of this type includes a detection resistor 11 which is inserted in series with a current line 12 to be measured, and an operational amplifier 9 which detects a voltage across the detection resistor 11. It is composed of a thyristor 14 connected to the output side of the operational amplifier 9, a reference voltage source 10 and a resistor 13 connected between the detection resistor 11 and the operational amplifier 9, and the operational amplifier 9 detects the voltage across the detection resistor 11. At the same time, the detection is performed by driving the thyristor 14 with the output of the operational amplifier 9.
［発明が解決しようとする問題点］ 上述した従来の過電流検出回路は、被測定電流線に直列
に検出抵抗11を挿入して構成しているため、検出ロスが
生じるという欠点がある。[Problems to be Solved by the Invention] Since the conventional overcurrent detection circuit described above is configured by inserting the detection resistor 11 in series with the current line to be measured, there is a drawback that a detection loss occurs.
［問題点を解決するための手段］ 上記従来の問題点を解決する本発明のラッチ式過電流検
出回路は、２素子SQUIDに第１の定電流源を接続し、前
記２素子SQUIDと被測定電流線を近接させ、前記２素子S
QUIDの一方のジョセフソン素子の両端をジョセフソンFE
Tのゲートとソースに接続し、前記ジョセフソンFETドレ
イン−ソース間に第２の定電流源を接続し、前記ジョセ
フソンFETのドレインを出力端子に接続した構成として
いる。[Means for Solving Problems] A latch-type overcurrent detection circuit according to the present invention which solves the above-mentioned conventional problems is configured by connecting a first constant current source to a two-element SQUID and measuring the two-element SQUID and the device under test. The current lines are brought close to each other, and the two elements S
Connect both ends of one Josephson element of the QUID to the Josephson FE
The gate and source of T are connected, a second constant current source is connected between the drain and source of the Josephson FET, and the drain of the Josephson FET is connected to the output terminal.
［実施例］ 次に、本発明の一実施例について図面を参照して詳細に
説明する。[Embodiment] Next, an embodiment of the present invention will be described in detail with reference to the drawings.
第１図は本発明の一実施例を示す回路図である。FIG. 1 is a circuit diagram showing an embodiment of the present invention.
第１図において、１は被測定電流線、2,3は定電流源、
４は２素子SQUID（Superconducting Quantum Interfere
nce Device）、5,6はジョセフソン素子、７はジョセフ
ソンFET、８は出力端子である。In FIG. 1, 1 is the current line to be measured, 2 and 3 are constant current sources,
4 is a 2-element SQUID (Superconducting Quantum Interfere)
nce Device), 5 and 6 are Josephson elements, 7 is a Josephson FET, and 8 is an output terminal.
本実施例のラッチ式過電流検出回路は、２素子SQUID4に
定電流源２を接続し、２素子SQUID4と被測定電流線１を
近接され、２素子SQUID4の一方のジョセフソン素子６の
両端をジョセフソンFET7のゲート及びソースに接続する
と共に、ジョセフソンFET7のドレイン−ソース間に定電
流源３を接続し、ジョセフソンFET7のドレインを出力端
子８に接続して構成されている。In the latch type overcurrent detection circuit of this embodiment, the constant current source 2 is connected to the two-element SQUID4, the two-element SQUID4 and the measured current line 1 are brought close to each other, and both ends of one Josephson element 6 of the two-element SQUID4 are connected. In addition to connecting to the gate and source of the Josephson FET 7, a constant current source 3 is connected between the drain and source of the Josephson FET 7, and the drain of the Josephson FET 7 is connected to the output terminal 8.
ここで、この回路の動作を簡単に説明する。Here, the operation of this circuit will be briefly described.
定電流源２から２素子SQUID4にIBなるバイアス電流が流
れ、ジョセフソン素子5,6にはそれぞれIB/2なる電流が
流れている。被測定電流線１にICなる電流が流れると、
２素子SQUID4にKIC（Ｋは変換定数）の電流が流れ、ジ
ョセフソン素子６にはIB/2＋KICなる電流が流れる。A bias current I B flows from the constant current source 2 to the two-element SQUID 4, and a current I B / 2 flows to each of the Josephson elements 5 and 6. When a current I C flows through the measured current line 1,
Current flows in the two elements SQUID4 KI C (K is a conversion constant), the Josephson device 6 I B / 2 + KI C becomes current flows.
ここで、ジョセフソン素子６の臨界電流をIOとすると、 IB/2＋KIC≧IO のとき、ジョセフソン素子5,6の両端に電圧が発生し、
ジョセフソンFET7のゲート電圧がハイになることによ
り、ジョセフソンFET7のドレイン−ソース間の臨界電流
が小さくなる（IO→IO′）。定電流源３によるバイアス
電流がジョセフソンFET7の臨界電流IO′より大きくなる
と、ジョセフソンFET7のドレイン−ソース間に電圧が発
生し、出力端子８はハイになり、ジョセフソンFETのゲ
ート電圧がローになっても、出力端子８はハイのままラ
ッチしている。ラッチが起きるのは、第２図に示すよう
にジョセフソンFET7の電流−電圧特性のヒステリシスの
ためである。Here, assuming that the critical current of the Josephson element 6 is I O , when I B / 2 + KI C ≧ I O , a voltage is generated across the Josephson elements 5 and 6,
When the gate voltage of the Josephson FET 7 becomes high, the critical current between the drain and the source of the Josephson FET 7 becomes small (I O → I O ′). When the bias current by the constant current source 3 becomes larger than the critical current I O ′ of the Josephson FET 7, a voltage is generated between the drain and the source of the Josephson FET 7, the output terminal 8 becomes high, and the gate voltage of the Josephson FET becomes Even when it goes low, the output terminal 8 remains latched high. The latching occurs because of the hysteresis of the current-voltage characteristic of the Josephson FET 7 as shown in FIG.
なお、検出電流ICの設定は、 IO＝KIC＋IB/2より 定電流源２によるバイアス電流IBにて設定する。The detection current I C is set by the bias current I B from the constant current source 2 from I O = KI C + I B / 2.
また、第２図中、IDSはジョセフソンFET7のドレイン−
ソース間電流、VDSはドレイン−ソース間電圧である。Further, in FIG. 2, I DS is the drain of Josephson FET7-
The source-to-source current, V DS is the drain-to-source voltage.
［発明の効果］ 以上説明したように本発明は、被測定電流線の電流をSQ
UIDで検出し、検出信号をジョセフソンFETでラッチする
ことにより、検出ロスのないラッチ式過電流検出回路を
簡単につくることができる。[Effects of the Invention] As described above, according to the present invention, the current of the current line to be measured is SQ.
By detecting with the UID and latching the detection signal with the Josephson FET, a latch-type overcurrent detection circuit with no detection loss can be easily created.
第１図は本発明の一実施例に係るラッチ式過電流検出回
路の回路図、第２図はジョセフソンFETの電流−電圧特
性を示す図、第３図は従来の過電流検出回路の回路図で
ある。 1:被測定電流線、2,3:定電流線 4:2素子SQUID 5,6:ジョセフソン素子 7:ジョセフソンFET 8:出力端子、9:オペアンプ 10:基準電圧源、11:検出抵抗 12:被測定電流線、13:抵抗 14:サイリスタFIG. 1 is a circuit diagram of a latch type overcurrent detection circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing current-voltage characteristics of a Josephson FET, and FIG. 3 is a circuit of a conventional overcurrent detection circuit. It is a figure. 1: Current line to be measured, 2, 3: Constant current line 4: 2 elements SQUID 5,6: Josephson element 7: Josephson FET 8: Output terminal, 9: Operational amplifier 10: Reference voltage source, 11: Detection resistor 12 : Measured current line, 13: Resistance 14: Thyristor
Claims (1)
前記２素子SQUIDと被測定電流線を近接させ、前記２素
子SQUIDの一方のジョセフソン素子の両端をジョセフソ
ンFETゲートとソースに接続し、前記ジョセフソンFETの
ドレイン−ソース間に第２の定電流源を接続し、前記ジ
ョセフソンFETのドレインを出力端子に接続したことを
特徴とするラッチ式過電流検出回路。1. A first constant current source is connected to a two-element SQUID,
The two-element SQUID and the current line to be measured are brought close to each other, one end of one Josephson element of the two-element SQUID is connected to the Josephson FET gate and the source, and a second constant is established between the drain and the source of the Josephson FET. A latch-type overcurrent detection circuit, characterized in that a current source is connected and the drain of the Josephson FET is connected to an output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP219288A JPH0731215B2 (en) | 1988-01-08 | 1988-01-08 | Latch type overcurrent detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP219288A JPH0731215B2 (en) | 1988-01-08 | 1988-01-08 | Latch type overcurrent detection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01178874A JPH01178874A (en) | 1989-07-17 |
| JPH0731215B2 true JPH0731215B2 (en) | 1995-04-10 |
Family
ID=11522499
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP219288A Expired - Lifetime JPH0731215B2 (en) | 1988-01-08 | 1988-01-08 | Latch type overcurrent detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0731215B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5100734B2 (en) * | 2009-10-07 | 2012-12-19 | 中国電力株式会社 | Transmission line protection device |
-
1988
- 1988-01-08 JP JP219288A patent/JPH0731215B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01178874A (en) | 1989-07-17 |
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